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GET /api/patches/1410/?format=api
{ "id": 1410, "url": "https://patches.dpdk.org/api/patches/1410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416530816-2159-4-git-send-email-jingjing.wu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416530816-2159-4-git-send-email-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416530816-2159-4-git-send-email-jingjing.wu@intel.com", "date": "2014-11-21T00:46:37", "name": "[dpdk-dev,v6,03/22] i40e: initialize flexible payload setting", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "da4e8f101a2c9dd92b955dae527c813bb1c68ec3", "submitter": { "id": 47, "url": "https://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416530816-2159-4-git-send-email-jingjing.wu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1410/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1410/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 143E17F98;\n\tFri, 21 Nov 2014 01:36:44 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 01C207F0C\n\tfor <dev@dpdk.org>; Fri, 21 Nov 2014 01:36:41 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP; 20 Nov 2014 16:44:58 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 20 Nov 2014 16:47:11 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id sAL0l6Fq003130;\n\tFri, 21 Nov 2014 08:47:06 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid sAL0l4Vp002214; Fri, 21 Nov 2014 08:47:06 +0800", "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sAL0l4KX002210; \n\tFri, 21 Nov 2014 08:47:04 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.07,426,1413270000\"; d=\"scan'208\";a=\"611514476\"", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 21 Nov 2014 08:46:37 +0800", "Message-Id": "<1416530816-2159-4-git-send-email-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "References": "<1414654006-7472-1-git-send-email-jingjing.wu@intel.com>\n\t<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "Subject": "[dpdk-dev] [PATCH v6 03/22] i40e: initialize flexible payload\n\tsetting", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "set flexible payload related registers to default value at initialization time.\n\nSigned-off-by: jingjing.wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 36 ++++++++++++++++++++++++++++++++\n lib/librte_pmd_i40e/i40e_ethdev.h | 35 +++++++++++++++++++++++++++++++\n lib/librte_pmd_i40e/i40e_fdir.c | 43 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 114 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex ac68540..e57b9b4 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -333,6 +333,35 @@ static struct rte_driver rte_i40e_driver = {\n \n PMD_REGISTER_DRIVER(rte_i40e_driver);\n \n+/*\n+ * Initialize registers for flexible payload, which should be set by NVM.\n+ * This should be removed from code once it is fixed in NVM.\n+ */\n+#ifndef I40E_GLQF_ORT\n+#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))\n+#endif\n+#ifndef I40E_GLQF_PIT\n+#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))\n+#endif\n+\n+static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)\n+{\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);\n+\n+\t/* GLQF_PIT Registers */\n+\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);\n+}\n+\n static int\n eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n struct rte_eth_dev *dev)\n@@ -396,6 +425,13 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n \t\treturn ret;\n \t}\n \n+\t/*\n+\t * To work around the NVM issue,initialize registers\n+\t * for flexible payload by software.\n+\t * It should be removed once issues are fixed in NVM.\n+\t */\n+\ti40e_flex_payload_reg_init(hw);\n+\n \t/* Initialize the parameters for adminq */\n \ti40e_init_adminq_parameter(hw);\n \tret = i40e_init_adminq(hw);\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex 7ad6501..341599d 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -57,6 +57,17 @@\n /* Always assign pool 0 to main VSI, VMDQ will start from 1 */\n #define I40E_VMDQ_POOL_BASE 1\n \n+/* index flex payload per layer */\n+enum i40e_flxpld_layer_idx {\n+\tI40E_FLXPLD_L2_IDX = 0,\n+\tI40E_FLXPLD_L3_IDX = 1,\n+\tI40E_FLXPLD_L4_IDX = 2,\n+\tI40E_MAX_FLXPLD_LAYER = 3,\n+};\n+#define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */\n+#define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */\n+#define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */\n+\n /* i40e flags */\n #define I40E_FLAG_RSS (1ULL << 0)\n #define I40E_FLAG_DCB (1ULL << 1)\n@@ -244,6 +255,24 @@ struct i40e_vmdq_info {\n };\n \n /*\n+ * Structure to store flex pit for flow diretor.\n+ */\n+struct i40e_fdir_flex_pit {\n+\tuint8_t src_offset; /* offset in words from the beginning of payload */\n+\tuint8_t size; /* size in words */\n+\tuint8_t dst_offset; /* offset in words of flexible payload */\n+};\n+\n+struct i40e_fdir_flex_mask {\n+\tuint8_t word_mask; /**< Bit i enables word i of flexible payload */\n+\tstruct {\n+\t\tuint8_t offset;\n+\t\tuint16_t mask;\n+\t} bitmask[I40E_FDIR_BITMASK_NUM_WORD];\n+};\n+\n+#define I40E_FILTER_PCTYPE_MAX 64\n+/*\n * A structure used to define fields of a FDIR related info.\n */\n struct i40e_fdir_info {\n@@ -253,6 +282,12 @@ struct i40e_fdir_info {\n \tstruct i40e_rx_queue *rxq;\n \tvoid *prg_pkt; /* memory for fdir program packet */\n \tuint64_t dma_addr; /* physic address of packet memory*/\n+\t/*\n+\t * the rule how bytes stream is extracted as flexible payload\n+\t * for each payload layer, the setting can up to three elements\n+\t */\n+\tstruct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];\n+\tstruct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];\n };\n \n /*\ndiff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex 9b678ce..ed61f2a 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -265,6 +265,47 @@ i40e_fdir_empty(struct i40e_hw *hw)\n }\n \n /*\n+ * Initialize the configuration about bytes stream extracted as flexible payload\n+ * and mask setting\n+ */\n+static inline void\n+i40e_init_flx_pld(struct i40e_pf *pf)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint8_t pctype;\n+\tint i, index;\n+\n+\t/*\n+\t * Define the bytes stream extracted as flexible payload in\n+\t * field vector. By default, select 8 words from the beginning\n+\t * of payload as flexible payload.\n+\t */\n+\tfor (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {\n+\t\tindex = i * I40E_MAX_FLXPLD_FIED;\n+\t\tpf->fdir.flex_set[index].src_offset = 0;\n+\t\tpf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;\n+\t\tpf->fdir.flex_set[index].dst_offset = 0;\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\tI40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\tI40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/\n+\t}\n+\n+\t/* initialize the masks */\n+\tfor (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n+\t pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {\n+\t\tpf->fdir.flex_mask[pctype].word_mask = 0;\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);\n+\t\tfor (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {\n+\t\t\tpf->fdir.flex_mask[pctype].bitmask[i].offset = 0;\n+\t\t\tpf->fdir.flex_mask[pctype].bitmask[i].mask = 0;\n+\t\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);\n+\t\t}\n+\t}\n+}\n+\n+/*\n * Configure flow director related setting\n */\n int\n@@ -294,6 +335,8 @@ i40e_fdir_configure(struct rte_eth_dev *dev)\n \t\t/* enable FDIR filter */\n \t\tval |= I40E_PFQF_CTL_0_FD_ENA_MASK;\n \t\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);\n+\n+\t\ti40e_init_flx_pld(pf); /* set flex config to default value */\n \t} else {\n \t\t/* disable FDIR filter */\n \t\tval &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;\n", "prefixes": [ "dpdk-dev", "v6", "03/22" ] }