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GET /api/patches/140047/?format=api
{ "id": 140047, "url": "https://patches.dpdk.org/api/patches/140047/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240514032131.153409-1-rongweil@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240514032131.153409-1-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240514032131.153409-1-rongweil@nvidia.com", "date": "2024-05-14T03:21:31", "name": "[v1] net/mlx5/hws: match VXLAN all fields", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "eee7b0419508a9fb317b5662d52ed785fa21f4d9", "submitter": { "id": 2223, "url": "https://patches.dpdk.org/api/people/2223/?format=api", "name": "rongwei liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240514032131.153409-1-rongweil@nvidia.com/mbox/", "series": [ { "id": 31916, "url": "https://patches.dpdk.org/api/series/31916/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31916", "date": "2024-05-14T03:21:31", "name": "[v1] net/mlx5/hws: match VXLAN all fields", "version": 1, "mbox": "https://patches.dpdk.org/series/31916/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/140047/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/140047/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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Sosnowski <dsosnowski@nvidia.com>", "Subject": "[PATCH v1] net/mlx5/hws: match VXLAN all fields", "Date": "Tue, 14 May 2024 06:21:31 +0300", "Message-ID": "<20240514032131.153409-1-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN1PEPF00004682:EE_|BL1PR12MB5922:EE_", "X-MS-Office365-Filtering-Correlation-Id": "18863941-0080-44b1-9157-08dc73c50525", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400017|376005|36860700004|1800799015;", "X-Microsoft-Antispam-Message-Info": "\n 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"X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Support VxLAN all fields support.\nTo match GBP or GPE extension, the user needs to set\nthe right UDP destination port plus the desired VxLAN\nflag bits.\n\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nReviewed-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 18 +++++++-------\n drivers/net/mlx5/hws/mlx5dr_definer.c | 36 ++++++---------------------\n drivers/net/mlx5/hws/mlx5dr_definer.h | 4 +--\n 3 files changed, 19 insertions(+), 39 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 9b2fe07fd3..dcc1beb812 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -302,21 +302,21 @@ Limitations\n size and ``txq_inline_min`` settings and may be from 2 (worst case forced by maximal\n inline settings) to 58.\n \n-- Match on VXLAN supports the following fields only:\n+- Match on VXLAN supports any bits in the tunnel header\n \n- - VNI\n- - Last reserved 8-bits\n-\n- Last reserved 8-bits matching is only supported When using DV flow\n- engine (``dv_flow_en`` = 1).\n- For ConnectX-5, the UDP destination port must be the standard one (4789).\n- Group zero's behavior may differ which depends on FW.\n- Matching value equals 0 (value & mask) is not supported.\n+ - Flag 8-bits and first 24-bits reserved fields matching is only supported When using DV flow\n+ engine (``dv_flow_en`` = 2).\n+ - For ConnectX-5, the UDP destination port must be the standard one (4789).\n+ - Group zero's behavior may differ which depends on FW.\n+ - Default UDP destination is 4789 if not explicitly specified.\n+ - User should set different flags when matching on VXLAN-GPE/GBP: like I and GPE bits for\n+ GPE and G bit for GBP.\n \n - Matching on VXLAN-GPE header fields:\n \n - ``rsvd0``/``rsvd1`` matching support depends on FW version\n when using DV flow engine (``dv_flow_en`` = 1).\n+ - ``protocol`` should be explicitly specified in HWS steering (``dv_flow_en`` = 2).\n \n - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex a0f95c6923..63381c1111 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -203,7 +203,8 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tgtp_next_ext_hdr,\tGTP_PDU_SC,\t\trte_flow_item_gtp_psc) \\\n \tX(SET,\t\tgtp_ext_hdr_pdu,\tv->hdr.type,\t\trte_flow_item_gtp_psc) \\\n \tX(SET,\t\tgtp_ext_hdr_qfi,\tv->hdr.qfi,\t\trte_flow_item_gtp_psc) \\\n-\tX(SET,\t\tvxlan_flags,\t\tv->flags,\t\trte_flow_item_vxlan) \\\n+\tX(SET_BE32,\tvxlan_vx_flags,\t\tv->hdr.vx_flags,\trte_flow_item_vxlan) \\\n+\tX(SET_BE32,\tvxlan_vx_vni,\t\tv->hdr.vx_vni,\t\trte_flow_item_vxlan) \\\n \tX(SET,\t\tvxlan_udp_port,\t\tUDP_VXLAN_PORT,\t\trte_flow_item_vxlan) \\\n \tX(SET,\t\tvxlan_gpe_udp_port,\tUDP_VXLAN_GPE_PORT,\trte_flow_item_vxlan_gpe) \\\n \tX(SET,\t\tvxlan_gpe_flags,\tv->flags,\t\trte_flow_item_vxlan_gpe) \\\n@@ -600,16 +601,6 @@ mlx5dr_definer_gre_key_set(struct mlx5dr_definer_fc *fc,\n \tDR_SET_BE32(tag, *v, fc->byte_off, fc->bit_off, fc->bit_mask);\n }\n \n-static void\n-mlx5dr_definer_vxlan_vni_set(struct mlx5dr_definer_fc *fc,\n-\t\t\t const void *item_spec,\n-\t\t\t uint8_t *tag)\n-{\n-\tconst struct rte_flow_item_vxlan *v = item_spec;\n-\n-\tmemcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));\n-}\n-\n static void\n mlx5dr_definer_ipv6_tos_set(struct mlx5dr_definer_fc *fc,\n \t\t\t const void *item_spec,\n@@ -1555,13 +1546,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd,\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n-\tif (m && (m->rsvd0[0] != 0 || m->rsvd0[1] != 0 || m->rsvd0[2] != 0 ||\n-\t m->rsvd1 != 0)) {\n-\t\tDR_LOG(ERR, \"reserved fields are not supported\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn rte_errno;\n-\t}\n-\n \tif (inner) {\n \t\tDR_LOG(ERR, \"Inner VXLAN item not supported\");\n \t\trte_errno = ENOTSUP;\n@@ -1590,22 +1574,18 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd,\n \tif (!m)\n \t\treturn 0;\n \n-\tif (m->flags) {\n-\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS];\n+\tif (m->hdr.vx_flags) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_DW0];\n \t\tfc->item_idx = item_idx;\n-\t\tfc->tag_set = &mlx5dr_definer_vxlan_flags_set;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_vx_flags_set;\n \t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n-\t\tfc->bit_mask = __mlx5_mask(header_vxlan, flags);\n-\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan, flags);\n \t}\n \n-\tif (!is_mem_zero(m->vni, 3)) {\n-\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI];\n+\tif (m->hdr.vx_vni) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_DW1];\n \t\tfc->item_idx = item_idx;\n-\t\tfc->tag_set = &mlx5dr_definer_vxlan_vni_set;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_vx_vni_set;\n \t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n-\t\tfc->bit_mask = __mlx5_mask(header_vxlan, vni);\n-\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan, vni);\n \t}\n \n \treturn 0;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex a42ba9b81a..8f34ea64c8 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -122,8 +122,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_FLEX_PARSER_6,\n \tMLX5DR_DEFINER_FNAME_FLEX_PARSER_7,\n \tMLX5DR_DEFINER_FNAME_VPORT_REG_C_0,\n-\tMLX5DR_DEFINER_FNAME_VXLAN_FLAGS,\n-\tMLX5DR_DEFINER_FNAME_VXLAN_VNI,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_DW0,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_DW1,\n \tMLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS,\n \tMLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0,\n \tMLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO,\n", "prefixes": [ "v1" ] }