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GET /api/patches/139993/?format=api
{ "id": 139993, "url": "https://patches.dpdk.org/api/patches/139993/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240508082944.24564-1-fengchengwen@huawei.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240508082944.24564-1-fengchengwen@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240508082944.24564-1-fengchengwen@huawei.com", "date": "2024-05-08T08:29:44", "name": "dma/hisilicon: remove support for HIP09 platform", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bcb12206d68df8ab554eff33399b01ca6247aa0b", "submitter": { "id": 2146, "url": "https://patches.dpdk.org/api/people/2146/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240508082944.24564-1-fengchengwen@huawei.com/mbox/", "series": [ { "id": 31892, "url": "https://patches.dpdk.org/api/series/31892/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31892", "date": "2024-05-08T08:29:44", "name": "dma/hisilicon: remove support for HIP09 platform", "version": 1, "mbox": "https://patches.dpdk.org/series/31892/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139993/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/139993/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E213443FDA;\n\tWed, 8 May 2024 10:32:27 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BA20640A6E;\n\tWed, 8 May 2024 10:32:25 +0200 (CEST)", "from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189])\n by mails.dpdk.org (Postfix) with ESMTP id 61BAF402AF\n for <dev@dpdk.org>; Wed, 8 May 2024 10:32:23 +0200 (CEST)", "from mail.maildlp.com (unknown [172.19.163.48])\n by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4VZ7by218LzNwH4;\n Wed, 8 May 2024 16:29:34 +0800 (CST)", "from dggpeml500024.china.huawei.com (unknown [7.185.36.10])\n by mail.maildlp.com (Postfix) with ESMTPS id E59F3180065;\n Wed, 8 May 2024 16:32:20 +0800 (CST)", "from localhost.localdomain (10.50.165.33) by\n dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.1.2507.35; Wed, 8 May 2024 16:32:20 +0800" ], "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<thomas@monjalon.net>, <dev@dpdk.org>", "Subject": "[PATCH] dma/hisilicon: remove support for HIP09 platform", "Date": "Wed, 8 May 2024 08:29:44 +0000", "Message-ID": "<20240508082944.24564-1-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.50.165.33]", "X-ClientProxiedBy": "dggems706-chm.china.huawei.com (10.3.19.183) To\n dggpeml500024.china.huawei.com (7.185.36.10)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The DMA for HIP09 is no longer available, so delete it.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n doc/guides/dmadevs/hisilicon.rst | 1 -\n doc/guides/rel_notes/release_24_07.rst | 2 ++\n drivers/dma/hisilicon/hisi_dmadev.c | 40 +-------------------------\n drivers/dma/hisilicon/hisi_dmadev.h | 35 +---------------------\n 4 files changed, 4 insertions(+), 74 deletions(-)", "diff": "diff --git a/doc/guides/dmadevs/hisilicon.rst b/doc/guides/dmadevs/hisilicon.rst\nindex 8c1f0f8886..974bc49376 100644\n--- a/doc/guides/dmadevs/hisilicon.rst\n+++ b/doc/guides/dmadevs/hisilicon.rst\n@@ -13,7 +13,6 @@ Supported Kunpeng SoCs\n ----------------------\n \n * Kunpeng 920\n-* Kunpeng 930\n \n \n Device Setup\ndiff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst\nindex a69f24cf99..4b27e5dbe8 100644\n--- a/doc/guides/rel_notes/release_24_07.rst\n+++ b/doc/guides/rel_notes/release_24_07.rst\n@@ -68,6 +68,8 @@ Removed Items\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* dma/hisilicon: remove support for HIP09 platform\n+\n \n API Changes\n -----------\ndiff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c\nindex 22303e7bef..067c9513f6 100644\n--- a/drivers/dma/hisilicon/hisi_dmadev.c\n+++ b/drivers/dma/hisilicon/hisi_dmadev.c\n@@ -39,8 +39,6 @@ hisi_dma_queue_base(struct hisi_dma_dev *hw)\n {\n \tif (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)\n \t\treturn HISI_DMA_HIP08_QUEUE_BASE;\n-\telse if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)\n-\t\treturn HISI_DMA_HIP09_QUEUE_BASE;\n \telse\n \t\treturn 0;\n }\n@@ -216,25 +214,6 @@ hisi_dma_init_hw(struct hisi_dma_dev *hw)\n \t\t\t\tHISI_DMA_HIP08_QUEUE_INT_MASK_M, true);\n \t\thisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,\n \t\t\t\tHISI_DMA_HIP08_QUEUE_INT_MASK_M, true);\n-\t} else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {\n-\t\thisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);\n-\t\thisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_INT_MASK_M, true);\n-\t\thisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_INT_MASK_M, true);\n-\t\thisi_dma_update_queue_mbit(hw,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);\n-\t\thisi_dma_update_queue_mbit(hw,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);\n-\t\thisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);\n-\t\thisi_dma_update_bit(hw,\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),\n-\t\t\t\tHISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,\n-\t\t\t\ttrue);\n \t}\n }\n \n@@ -256,8 +235,6 @@ hisi_dma_reg_layout(uint8_t revision)\n {\n \tif (revision == HISI_DMA_REVISION_HIP08B)\n \t\treturn HISI_DMA_REG_LAYOUT_HIP08;\n-\telse if (revision >= HISI_DMA_REVISION_HIP09A)\n-\t\treturn HISI_DMA_REG_LAYOUT_HIP09;\n \telse\n \t\treturn HISI_DMA_REG_LAYOUT_INVALID;\n }\n@@ -328,14 +305,11 @@ hisi_dma_info_get(const struct rte_dma_dev *dev,\n \t\t struct rte_dma_info *dev_info,\n \t\t uint32_t info_sz)\n {\n-\tstruct hisi_dma_dev *hw = dev->data->dev_private;\n+\tRTE_SET_USED(dev);\n \tRTE_SET_USED(info_sz);\n \n \tdev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |\n \t\t\t RTE_DMA_CAPA_OPS_COPY;\n-\tif (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)\n-\t\tdev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS;\n-\n \tdev_info->max_vchans = 1;\n \tdev_info->max_desc = HISI_DMA_MAX_DESC_NUM;\n \tdev_info->min_desc = HISI_DMA_MIN_DESC_NUM;\n@@ -514,18 +488,6 @@ hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)\n \t\t{ HISI_DMA_REG_LAYOUT_HIP08,\n \t\t HISI_DMA_HIP08_DUMP_START_REG,\n \t\t HISI_DMA_HIP08_DUMP_END_REG },\n-\t\t{ HISI_DMA_REG_LAYOUT_HIP09,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_A_START_REG,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_A_END_REG },\n-\t\t{ HISI_DMA_REG_LAYOUT_HIP09,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_B_START_REG,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_B_END_REG },\n-\t\t{ HISI_DMA_REG_LAYOUT_HIP09,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_C_START_REG,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_C_END_REG },\n-\t\t{ HISI_DMA_REG_LAYOUT_HIP09,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_D_START_REG,\n-\t\t HISI_DMA_HIP09_DUMP_REGION_D_END_REG },\n \t};\n \tuint32_t i;\n \ndiff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h\nindex 5a17f9f69e..a57b5c759a 100644\n--- a/drivers/dma/hisilicon/hisi_dmadev.h\n+++ b/drivers/dma/hisilicon/hisi_dmadev.h\n@@ -25,22 +25,14 @@\n #define HISI_DMA_DEVICE_ID\t\t\t0xA122\n #define HISI_DMA_PCI_REVISION_ID_REG\t\t0x08\n #define HISI_DMA_REVISION_HIP08B\t\t0x21\n-#define HISI_DMA_REVISION_HIP09A\t\t0x30\n \n #define HISI_DMA_MAX_HW_QUEUES\t\t\t4\n #define HISI_DMA_MAX_DESC_NUM\t\t\t8192\n #define HISI_DMA_MIN_DESC_NUM\t\t\t32\n \n-/**\n- * The HIP08B(HiSilicon IP08) and HIP09B(HiSilicon IP09) are DMA iEPs, they\n- * have the same pci device id but different pci revision.\n- * Unfortunately, they have different register layouts, so two layout\n- * enumerations are defined.\n- */\n enum {\n \tHISI_DMA_REG_LAYOUT_INVALID = 0,\n-\tHISI_DMA_REG_LAYOUT_HIP08,\n-\tHISI_DMA_REG_LAYOUT_HIP09\n+\tHISI_DMA_REG_LAYOUT_HIP08\n };\n \n /**\n@@ -69,9 +61,6 @@ enum {\n * length of queue-region. The global offset for a single queue register is\n * calculated by:\n * offset = queue-base + (queue-id * queue-region) + reg-offset-in-region.\n- *\n- * The first part of queue region is basically the same for HIP08 and HIP09\n- * register layouts, therefore, HISI_QUEUE_* registers are defined for it.\n */\n #define HISI_DMA_QUEUE_SQ_BASE_L_REG\t\t0x0\n #define HISI_DMA_QUEUE_SQ_BASE_H_REG\t\t0x4\n@@ -110,28 +99,6 @@ enum {\n #define HISI_DMA_HIP08_DUMP_START_REG\t\t\t0x2000\n #define HISI_DMA_HIP08_DUMP_END_REG\t\t\t0x2280\n \n-/**\n- * HiSilicon IP09 DMA register and field define:\n- */\n-#define HISI_DMA_HIP09_QUEUE_BASE\t\t\t0x2000\n-#define HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M\t\tGENMASK(31, 28)\n-#define HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B\t\t2\n-#define HISI_DMA_HIP09_QUEUE_INT_MASK_M\t\t\t0x1\n-#define HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG\t\t0x48\n-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG\t\t0x4C\n-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M\t\tGENMASK(18, 1)\n-#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id)\t\t(0x800 + \\\n-\t\t\t\t\t\t\t (queue_id) * 0x20)\n-#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B\t16\n-#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG\t\t0x0\n-#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG\t\t0x368\n-#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG\t\t0x800\n-#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG\t\t0xA08\n-#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG\t\t0x1800\n-#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG\t\t0x1A4C\n-#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG\t\t0x1C00\n-#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG\t\t0x1CC4\n-\n /**\n * In fact, there are multiple states, but it need to pay attention to\n * the following three states for the driver:\n", "prefixes": [] }