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GET /api/patches/139675/?format=api
{ "id": 139675, "url": "https://patches.dpdk.org/api/patches/139675/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240425085853.97888-6-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240425085853.97888-6-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240425085853.97888-6-mattias.ronnblom@ericsson.com", "date": "2024-04-25T08:58:52", "name": "[RFC,v2,5/6] eal: add atomic bit operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "cc8dbac1cfe03c9aa274eb8435e48602703d0b8f", "submitter": { "id": 1077, "url": "https://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240425085853.97888-6-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31818, "url": "https://patches.dpdk.org/api/series/31818/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31818", "date": "2024-04-25T08:58:47", "name": "Improve EAL bit operations API", "version": 2, "mbox": "https://patches.dpdk.org/series/31818/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139675/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/139675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2202A43F04;\n\tThu, 25 Apr 2024 11:10:22 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 443BE436DD;\n\tThu, 25 Apr 2024 11:10:05 +0200 (CEST)", "from EUR03-DBA-obe.outbound.protection.outlook.com\n (mail-dbaeur03on2067.outbound.protection.outlook.com [40.107.104.67])\n by mails.dpdk.org (Postfix) with ESMTP id 0BAEE436C8\n for <dev@dpdk.org>; Thu, 25 Apr 2024 11:10:02 +0200 (CEST)", "from DUZP191CA0028.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:4f8::24)\n by DBAPR07MB6807.eurprd07.prod.outlook.com (2603:10a6:10:19f::18) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Thu, 25 Apr\n 2024 09:09:59 +0000", "from DU2PEPF0001E9C2.eurprd03.prod.outlook.com\n (2603:10a6:10:4f8:cafe::52) by DUZP191CA0028.outlook.office365.com\n (2603:10a6:10:4f8::24) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.25 via Frontend\n Transport; Thu, 25 Apr 2024 09:09:59 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DU2PEPF0001E9C2.mail.protection.outlook.com (10.167.8.71) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7519.19 via Frontend Transport; Thu, 25 Apr 2024 09:09:59 +0000", "from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.65) with Microsoft SMTP Server\n id 15.2.1258.12; Thu, 25 Apr 2024 11:09:59 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>,\n \"Stephen Hemminger\" <stephen@networkplumber.org>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>, =?utf-8?q?Mattias_R=C3=B6nnb?=\n\t=?utf-8?q?lom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v2 5/6] eal: add atomic bit operations", "Date": "Thu, 25 Apr 2024 10:58:52 +0200", "Message-ID": "<20240425085853.97888-6-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240425085853.97888-1-mattias.ronnblom@ericsson.com>", "References": "<20240302135328.531940-2-mattias.ronnblom@ericsson.com>\n <20240425085853.97888-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DU2PEPF0001E9C2:EE_|DBAPR07MB6807:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a656cc31-d8ad-4bb5-5e8f-08dc65077c01", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?I+8TyHoetdndPMF8NL534sGUk3Y1jdX?=\n\t=?utf-8?q?H2C6RPhgWod0c6/DvDDV1v7bSrGmZTk51jN45Q0Eh2MXwHX8cEgQc6bna2r0QScmy?=\n\t=?utf-8?q?Xd/+ev2m9QZvJjmrOi22bo1wbBKM1k8yYaEDlfrm3B7JvVKHdyHi/RBDhIMBxxJ6h?=\n\t=?utf-8?q?JaEzOk4cUEHg93I5/6wVm4AppeiGFD/nqWh8qOPKiPvx96r3dGqqm7qEe3YCiVV/S?=\n\t=?utf-8?q?cwfliVnEp/fD/CkJhX+TaapRQ7a/REg7DpPP2Dw/evs/q2E3HIND92U3myJifmCcR?=\n\t=?utf-8?q?6QfRU3kaNC7pRcYr81IOTGuELn/uQg1Dd48tnPlzBWYnDBMHkL1yk/FVoNhL4QB3z?=\n\t=?utf-8?q?Dd+jndQ/+8UXNmpHCPDsYKvdauhF7lsY2wwp3X+Pc/06ALef7bFGhgNg9TYA5UlHH?=\n\t=?utf-8?q?Q9DO49Dzhi/rEcpftalIc2UHu+2CDlUQPMmgAJMOzf6TEQ48BgNTo4AdxJn+xjdQf?=\n\t=?utf-8?q?1iOv1n1/TkrWup+bgh1fDr2+QcNZWZTkJhL7tdWT93CcRIEkPdP1z+nJRiYM6iVeQ?=\n\t=?utf-8?q?4xTEohRpiOkI5eEuK4El3zowvn2OJU3GzQ3TKjtnh0AFiCXjuRpOWkoARX1uLYVbe?=\n\t=?utf-8?q?8ZM5QOsOtCuAlanzysqjS1Wg1s76RyOOPcG/clhKzMbXEm7hdmGAxOSkpVY8qQHJo?=\n\t=?utf-8?q?xRdb5flCI35x/FDDsyYMm0nf1/FsWjvHnUUpc+uUGMdsVaNWspBDz2F9pbtVm9/lT?=\n\t=?utf-8?q?vThGfqCtlfMK26lnIhbHIv122ppJwy86ldmNdYu1/7dAygPplBnWCwRL9QWFybgkp?=\n\t=?utf-8?q?l6R0efr4TRw2sNiFOJg58W1ecD7VeI7EnYv+pK8xJFGe1DRUxE70RAtQc8/w2J/kr?=\n\t=?utf-8?q?PpCamgJCw4UOlqEojaTsJZHNqbzcib+7M8a+hlaV+TYH6tJoBRYVQtRPxGk2LWADx?=\n\t=?utf-8?q?8a/VT/7qcos8dJx2+drZSyKms8fABUJVycuYS9Lu0Ry5/DjJ1Z5DKHehaEJCYt0su?=\n\t=?utf-8?q?7lZCTlg9B2n2MBMxDtvWcfbzpc32aGPZMxs5uSmJPjAdPvAEVtydabTZvbLiK2qd0?=\n\t=?utf-8?q?3edb3lt9MmhfMBia+SGuX5HHqC3NDULKTJHeF4oaNklxItdL8wsPe3sChlhlXiAcM?=\n\t=?utf-8?q?yDCHVa8pJVq+74d/LfudHvT9v6jPE2dh1la0GJBRhn43bDlaHZPkW/nvcQiwg/MHB?=\n\t=?utf-8?q?E8qBvtWsno5OBpNuuRy/4Okr1G9QADE/OChVJN2eDAfxBmT4+90/9chjWqs5PF9Z7?=\n\t=?utf-8?q?k871z+zsVhk2kXKhJ3LLnCX3GWav2Z3ZdlAOpzDzOtqgFhewBH6oo+7soaPkKbaeY?=\n\t=?utf-8?q?Icnx+Hu2/9yASSzKsx9BKhFhx4dEMvgnEERa5wipONyqyRNOpnsqsAVLoFcc0AyYH?=\n\t=?utf-8?q?RhJ7lU6B5Dw8?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014)(1800799015);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Apr 2024 09:09:59.8471 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a656cc31-d8ad-4bb5-5e8f-08dc65077c01", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DU2PEPF0001E9C2.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DBAPR07MB6807", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add atomic bit test/set/clear/assign and test-and-set/clear functions.\n\nAll atomic bit functions allow (and indeed, require) the caller to\nspecify a memory order.\n\nRFC v2:\n o Add rte_bit_atomic_test_and_assign() (for consistency).\n o Fix bugs in rte_bit_atomic_test_and_[set|clear]().\n o Use <rte_stdatomics.h> to support MSVC.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\n---\n lib/eal/include/rte_bitops.h | 297 +++++++++++++++++++++++++++++++++++\n 1 file changed, 297 insertions(+)", "diff": "diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h\nindex a2746e657f..8c38a1ac03 100644\n--- a/lib/eal/include/rte_bitops.h\n+++ b/lib/eal/include/rte_bitops.h\n@@ -21,6 +21,7 @@\n \n #include <rte_compat.h>\n #include <rte_debug.h>\n+#include <rte_stdatomic.h>\n \n #ifdef __cplusplus\n extern \"C\" {\n@@ -342,6 +343,177 @@ extern \"C\" {\n \t\t uint32_t *: __rte_bit_once_assign32,\t\t\t\\\n \t\t uint64_t *: __rte_bit_once_assign64)(addr, nr, value)\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Test if a particular bit in a word is set with a particular memory\n+ * order.\n+ *\n+ * Test a bit with the resulting memory load ordered as per the\n+ * specified memory order.\n+ *\n+ * @param addr\n+ * A pointer to the word to query.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit is set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically set bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to '1', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_set(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_set32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically clear bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to '0', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_clear(addr, nr, memory_order)\t\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_clear32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically assign a value to bit in word.\n+ *\n+ * Atomically set bit specified by @c nr in the word pointed to by @c\n+ * addr to the value indicated by @c value, with the memory ordering\n+ * as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+#define rte_bit_atomic_assign(addr, nr, value, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_assign32,\t\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \\\n+\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and set a bit in word.\n+ *\n+ * Atomically test and set bit specified by @c nr in the word pointed\n+ * to by @c addr to '1', with the memory ordering as specified with @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_set(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_set32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr,\t\\\n+\t\t\t\t\t\t\t memory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and clear a bit in word.\n+ *\n+ * Atomically test and clear bit specified by @c nr in the word\n+ * pointed to by @c addr to '0', with the memory ordering as specified\n+ * with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_clear(addr, nr, memory_order)\t\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_clear32,\t\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \\\n+\t\t\t\t\t\t\t\tmemory_order)\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Atomically test and assign a bit in word.\n+ *\n+ * Atomically test and assign bit specified by @c nr in the word\n+ * pointed to by @c addr the value specified by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the word to modify.\n+ * @param nr\n+ * The index of the bit.\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order)\t\\\n+\t_Generic((addr),\t\t\t\t\t\t\\\n+\t\t uint32_t *: __rte_bit_atomic_test_and_assign32,\t\\\n+\t\t uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \\\n+\t\t\t\t\t\t\t\t value, \\\n+\t\t\t\t\t\t\t\t memory_order)\n+\n #define __RTE_GEN_BIT_TEST(name, size, qualifier)\t\t\t\\\n \tstatic inline bool\t\t\t\t\t\t\\\n \tname(const qualifier uint ## size ## _t *addr, unsigned int nr)\t\\\n@@ -429,6 +601,131 @@ __rte_bit_once_assign64(volatile uint64_t *addr, unsigned int nr, bool value)\n \t\t__rte_bit_once_clear64(addr, nr);\n }\n \n+#define __RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test ## size(const uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tconst RTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(const RTE_ATOMIC(uint ## size ## _t) *)addr;\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\treturn rte_atomic_load_explicit(a_addr, memory_order) & mask; \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_set ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_clear ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\trte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_assign ## size(uint ## size ## _t *addr,\t\\\n+\t\t\t\t\tunsigned int nr, bool value,\t\\\n+\t\t\t\t\tint memory_order)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tif (value)\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_set ## size(addr, nr, memory_order); \\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\t__rte_bit_atomic_clear ## size(addr, nr,\t\\\n+\t\t\t\t\t\t memory_order);\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \\\n+\t\t\t\t\t\t unsigned int nr,\t\\\n+\t\t\t\t\t\t bool value,\t\t\\\n+\t\t\t\t\t\t int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ATOMIC(uint ## size ## _t) *a_addr =\t\t\\\n+\t\t\t(RTE_ATOMIC(uint ## size ## _t) *)addr;\t\t\\\n+\t\tuint ## size ## _t before;\t\t\t\t\\\n+\t\tuint ## size ## _t target;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tbefore = rte_atomic_load_explicit(a_addr,\t\t\\\n+\t\t\t\t\t\t rte_memory_order_relaxed); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\ttarget = before;\t\t\t\t\\\n+\t\t\t__rte_bit_assign ## size(&target, nr, value);\t\\\n+\t\t} while (!rte_atomic_compare_exchange_weak_explicit(\t\\\n+\t\t\t\ta_addr, &before, target,\t\t\\\n+\t\t\t\trte_memory_order_relaxed,\t\t\\\n+\t\t\t\tmemory_order));\t\t\t\t\\\n+\t\treturn __rte_bit_test ## size(&before, nr);\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_OPS(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\n+\n+__RTE_GEN_BIT_ATOMIC_OPS(32)\n+__RTE_GEN_BIT_ATOMIC_OPS(64)\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, true,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr,\n+\t\t\t\tint memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, false,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, true,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n+__rte_experimental\n+static inline bool\n+__rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, false,\n+\t\t\t\t\t\t memory_order);\n+}\n+\n /*------------------------ 32-bit relaxed operations ------------------------*/\n \n /**\n", "prefixes": [ "RFC", "v2", "5/6" ] }