Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/139556/?format=api
{ "id": 139556, "url": "https://patches.dpdk.org/api/patches/139556/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-5-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240419195310.21432-5-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240419195310.21432-5-andrew.boyer@amd.com", "date": "2024-04-19T19:53:08", "name": "[4/6] crypto/ionic: add device object and vdev support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "ec96f73c81bcc0ef28623fec11ff3e9c0bf33238", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-5-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31795, "url": "https://patches.dpdk.org/api/series/31795/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31795", "date": "2024-04-19T19:53:04", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 1, "mbox": "https://patches.dpdk.org/series/31795/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139556/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/139556/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 796AB43EB5;\n\tFri, 19 Apr 2024 21:54:15 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 31D4C40A7F;\n\tFri, 19 Apr 2024 21:53:57 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2076.outbound.protection.outlook.com [40.107.220.76])\n by mails.dpdk.org (Postfix) with ESMTP id DAEF740A72\n for <dev@dpdk.org>; Fri, 19 Apr 2024 21:53:55 +0200 (CEST)", "from SA0PR12CA0019.namprd12.prod.outlook.com (2603:10b6:806:6f::24)\n by SJ2PR12MB8806.namprd12.prod.outlook.com (2603:10b6:a03:4d0::8)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.41; Fri, 19 Apr\n 2024 19:53:50 +0000", "from SA2PEPF00001506.namprd04.prod.outlook.com\n (2603:10b6:806:6f:cafe::32) by SA0PR12CA0019.outlook.office365.com\n (2603:10b6:806:6f::24) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7495.31 via Frontend\n Transport; Fri, 19 Apr 2024 19:53:50 +0000", "from SATLEXMB04.amd.com (165.204.84.17) by\n SA2PEPF00001506.mail.protection.outlook.com (10.167.242.38) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.20.7452.22 via Frontend Transport; Fri, 19 Apr 2024 19:53:50 +0000", "from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com\n (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 19 Apr\n 2024 14:53:48 -0500" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=gG94afX2thagsOb36zpq93YqHtXfIltX/TT9CUxobiU+61AkAekU/nLViiCBIG70cI38M/t7/bUWrYRkpoFRqvmLrNqEyG6fXscPHnxKfFO5KG4ToP5VEEIUpBR2H2q9WWlSlGvWcl38HrqeaVKOAhzqeGfopQYHDi2+wCs0ljpJ25vV1Ivlpx8NQwqLbXthNH7trXxS8T+9myhAwrt8U017oybRPi9Gq/Yr3nKkmCYaCsRbx45ZF8G8sYPlkPV4vrR81VhJRHDQzd3Req/hN0XG5vXcVhy0m4VVbd83Oy8oN/9GEFtpET4VIITWSBXNvw7QTI4WoJc5fVuZPC1+Mg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=rds9JQkFmRDQ/DfGbhd9V9UNm0zC7RNm1Oar/8Jf3dY=;\n b=oarRNQ29kwfHBfw2w6KRbU8TsY19X3h+K84AiVJnRL93fs2bZviHCGrSwbiLhimU1vOiRhYkzEWuNNl5oQooFJFQ0NWY85ARXp4Jr9GAberLvzjUOqzTidb9vSZnHOvzx06EiOTCgGQHWdVO8SK3uh8nVIzSA7YJ/piyq8ydBTtZPmYvNF0yvWIPWQ0n9n6rx+RXI44NlYKL/ZBNd/h+qPu0pzv8Am4D6ZxX3IvWFIJedCfRAvZSvLDqeUw4mgqQ0nHOm1aNAhTk+fmRhnhR0aBiDENN8Lxi4mJzXyVud8fz/ylzBbYshgsGKTCii2EsXp00ii0k9/vjcx3IaZ/BFw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 165.204.84.17) smtp.rcpttodomain=dpdk.org smtp.mailfrom=amd.com; dmarc=pass\n (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=rds9JQkFmRDQ/DfGbhd9V9UNm0zC7RNm1Oar/8Jf3dY=;\n b=0xz4e9LE2Oe3ipKO/XhIyIHyuA3Xyi1oExEBR4jss4jYr8RWEwamCfEo7BofW4jn2DuhdXIrFN5ezJtmQF3GB1C2ZtAbjAB73NGxn7oZujPK4d4Vtvu8IcJ1jd+enjP2ogVi2rak0VTC4B/W2c9vZKeR/TvCMloy3a5xjz/SsAc=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Akhil Goyal <gakhil@marvell.com>, Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 4/6] crypto/ionic: add device object and vdev support", "Date": "Fri, 19 Apr 2024 12:53:08 -0700", "Message-ID": "<20240419195310.21432-5-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240419195310.21432-1-andrew.boyer@amd.com>", "References": "<20240419195310.21432-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF00001506:EE_|SJ2PR12MB8806:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2117f918-2203-46a0-3a3f-08dc60aa6ee9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +rkCfdV30IXJQAZP8INX/WOATJJArlF+4Zx9mQs+LR/VD964FHgGKVTFJuh4DmjxvTH3zMVdtaBNRYWH+fQFGhEnrDqjReHLVfh0p7TrnHFP32I9oYhIGjp0ArPvzh5pBaGe1DCp/mJgdG2E1n24h7H/tN/S1d2/jDQ0vzfWvlACl+NZ/0LHkU8uNfTQaQQTHtj10pFNl5qUE+d6LZD+71PD/1FNccdhgRAOV+FHLtXEkCMC290KFX/ctJddmU+5RlVEYZVgdCm9LIApqYULubTEfJivS7id2JzLNx+2TAzkwIu/MTBWwl0cB6ivjqIoyW9HnCvha7kRUEIj3fFGxH/E8o87ljxvWfvd8dtoGU/2/vu47PoK2aQmbkoByUhgTzmGf8dLRRabx0BSMSOxI2mzr7YRO6hDlvYOD8SqFwLTcj6AIYVXWG0w4bxI6p7TsgIJ2H8z2/6c+sNydyDTveVpOiW+FHxGAr1jG0NuuSagzo7G8gC0kN+hJSpgwqsb/Are7b62LSMsqMocElpGopuGiyYvNDTe9aq+eONAzb5l+xekmFDUVKzJtxtX6NtyOXs4/cnMr0tICKrIp5tRfXNMc+dDB5nKdGvfXCCFdUayw+ji9c43AAMBXrB0CpYGc3Hb4lSzrngaKCZ+g8D/YcSV1xjRw9DccwNe8haxczJInqXQp7coA9rPE08Mrb6o/8qizZDnKi1DtDXQ9ELdj6OLdLBf7TeoT9uZ6Or31Vpq2/WmrnNn9bZkFx27Yt7SFj4vB2KwFmofGJ3b/tw9zDdj0umOLCQkW9XCCtRFoG95xwoKvU2SCxuwXYH78d3ayPUOODbGmM/jqXqqItViGQL3tz0awzdrbL2A6zO3FfRvx7a7YIUGAJDwC+qz0VB880Gekyqrr09ZieJD8PWaBahBd1Kf+FzQKy2EfTswido5oqVqs2BKEVfGKz8bhooQ6K39LNBVm/G27wZoqlQcjOYJKN2rUz7sNDNNGgOixE3XJty0K4lh1/+nEm5pYrserQ1KEX14MmQHYh0QHpr+loDdzShG0+a1Ak9nvNVeqIFTh46/XWH2HMzLgZRAPltgWDdIXChzMynZ6OdpDz6c7Cwo43vXI2nVbnkyPNUbzuHMs8USlC1FTvAne1J7S+py3n461jE4j9GBt02mpzfvxceFFZd4ShT/Xlnftrp36AIbzWfYm2i1YZiFbIwfV7jEp8YxDIJs5g/A2xjt5ePeAGwOASWySO/1cTeMzXhJtGS6zonEwtxVbpCys/LBolxpmYs9BzxB79uiL99XRhlxfjVp9vZdkm1YV3FkLZfRrPCs9aYcJU6vI6Et2NvMTo+0BVxckONtBBfOspFYcylu2RsyxZkt3teMvTFBobu5eAo=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(376005)(1800799015)(82310400014)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Apr 2024 19:53:50.0628 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2117f918-2203-46a0-3a3f-08dc60aa6ee9", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF00001506.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8806", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This defines the main device object routines and the vdev\nsupport code. The vdev code uses the common library.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/crypto/ionic/ionic_crypto.h | 89 ++++\n drivers/crypto/ionic/ionic_crypto_main.c | 538 +++++++++++++++++++++++\n drivers/crypto/ionic/ionic_crypto_vdev.c | 128 ++++++\n drivers/crypto/ionic/meson.build | 2 +\n 4 files changed, 757 insertions(+)\n create mode 100644 drivers/crypto/ionic/ionic_crypto_vdev.c", "diff": "diff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h\nindex 958e611337..d048f7aa51 100644\n--- a/drivers/crypto/ionic/ionic_crypto.h\n+++ b/drivers/crypto/ionic/ionic_crypto.h\n@@ -20,6 +20,11 @@\n #include \"ionic_crypto_if.h\"\n #include \"ionic_regs.h\"\n \n+/* Devargs */\n+/* NONE */\n+\n+#define IOCPT_MAX_RING_DESC\t\t32768\n+#define IOCPT_MIN_RING_DESC\t\t16\n #define IOCPT_ADMINQ_LENGTH\t\t16\t/* must be a power of two */\n \n #define IOCPT_CRYPTOQ_WAIT\t\t10\t/* 1s */\n@@ -32,6 +37,64 @@ extern int iocpt_logtype;\n \n #define IOCPT_PRINT_CALL() IOCPT_PRINT(DEBUG, \" >>\")\n \n+static inline void iocpt_struct_size_checks(void)\n+{\n+\tRTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8);\n+\tRTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32);\n+\tRTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8);\n+\n+\tRTE_BUILD_BUG_ON(sizeof(union iocpt_dev_regs) != 4096);\n+\tRTE_BUILD_BUG_ON(sizeof(union iocpt_dev_info_regs) != 2048);\n+\tRTE_BUILD_BUG_ON(sizeof(union iocpt_dev_cmd_regs) != 2048);\n+\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_admin_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_admin_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_nop_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_nop_comp) != 16);\n+\n+\t/* Device commands */\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_dev_identify_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_dev_identify_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_dev_reset_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_dev_reset_comp) != 16);\n+\n+\t/* LIF commands */\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_identify_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_identify_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_init_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_init_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_reset_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_getattr_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_getattr_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_setattr_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_lif_setattr_comp) != 16);\n+\n+\t/* Queue commands */\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_q_identify_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_q_identify_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_q_init_cmd) != 64);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_q_init_comp) != 16);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_q_control_cmd) != 64);\n+\n+\t/* Crypto */\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_crypto_desc) != 32);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_crypto_sg_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(struct iocpt_crypto_comp) != 16);\n+}\n+\n+struct iocpt_dev_bars {\n+\tstruct ionic_dev_bar bar[IONIC_BARS_MAX];\n+\tuint32_t num_bars;\n+};\n+\n+/* Queue watchdog */\n+#define IOCPT_Q_WDOG_SESS_IDX\t\t0\n+#define IOCPT_Q_WDOG_KEY_LEN\t\t16\n+#define IOCPT_Q_WDOG_IV_LEN\t\t12\n+#define IOCPT_Q_WDOG_PLD_LEN\t\t4\n+#define IOCPT_Q_WDOG_TAG_LEN\t\t16\n+#define IOCPT_Q_WDOG_OP_TYPE\t\tRTE_CRYPTO_OP_TYPE_UNDEFINED\n+\n struct iocpt_qtype_info {\n \tuint8_t\t version;\n \tuint8_t\t supported;\n@@ -108,8 +171,10 @@ struct iocpt_admin_q {\n struct iocpt_dev {\n \tconst char *name;\n \tchar fw_version[IOCPT_FWVERS_BUFLEN];\n+\tstruct iocpt_dev_bars bars;\n \tstruct iocpt_identity ident;\n \n+\tconst struct iocpt_dev_intf *intf;\n \tvoid *bus_dev;\n \tstruct rte_cryptodev *crypto_dev;\n \n@@ -130,6 +195,8 @@ struct iocpt_dev {\n \n \tstruct iocpt_admin_q *adminq;\n \n+\tstruct rte_bitmap *sess_bm;\t/* SET bit indicates index is free */\n+\n \tuint64_t features;\n \tuint32_t hw_features;\n \n@@ -144,6 +211,20 @@ struct iocpt_dev {\n \tstruct rte_cryptodev_stats stats_base;\n };\n \n+struct iocpt_dev_intf {\n+\tint (*setup_bars)(struct iocpt_dev *dev);\n+\tvoid (*unmap_bars)(struct iocpt_dev *dev);\n+};\n+\n+static inline int\n+iocpt_setup_bars(struct iocpt_dev *dev)\n+{\n+\tif (dev->intf->setup_bars == NULL)\n+\t\treturn -EINVAL;\n+\n+\treturn (*dev->intf->setup_bars)(dev);\n+}\n+\n /** iocpt_admin_ctx - Admin command context.\n * @pending_work:\tFlag that indicates a completion.\n * @cmd:\t\tAdmin command (64B) to be copied to the queue.\n@@ -155,6 +236,14 @@ struct iocpt_admin_ctx {\n \tunion iocpt_adminq_comp comp;\n };\n \n+int iocpt_probe(void *bus_dev, struct rte_device *rte_dev,\n+\tstruct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf,\n+\tuint8_t driver_id, uint8_t socket_id);\n+int iocpt_remove(struct rte_device *rte_dev);\n+\n+void iocpt_configure(struct iocpt_dev *dev);\n+void iocpt_deinit(struct iocpt_dev *dev);\n+\n int iocpt_dev_identify(struct iocpt_dev *dev);\n int iocpt_dev_init(struct iocpt_dev *dev, rte_iova_t info_pa);\n int iocpt_dev_adminq_init(struct iocpt_dev *dev);\ndiff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c\nindex 7b26080bd1..84aff65f22 100644\n--- a/drivers/crypto/ionic/ionic_crypto_main.c\n+++ b/drivers/crypto/ionic/ionic_crypto_main.c\n@@ -12,6 +12,32 @@\n \n int iocpt_logtype;\n \n+static int\n+iocpt_cq_init(struct iocpt_cq *cq, uint16_t num_descs)\n+{\n+\tif (!rte_is_power_of_2(num_descs) ||\n+\t num_descs < IOCPT_MIN_RING_DESC ||\n+\t num_descs > IOCPT_MAX_RING_DESC) {\n+\t\tIOCPT_PRINT(ERR, \"%u descriptors (min: %u max: %u)\",\n+\t\t\tnum_descs, IOCPT_MIN_RING_DESC, IOCPT_MAX_RING_DESC);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcq->num_descs = num_descs;\n+\tcq->size_mask = num_descs - 1;\n+\tcq->tail_idx = 0;\n+\tcq->done_color = 1;\n+\n+\treturn 0;\n+}\n+\n+static void\n+iocpt_cq_map(struct iocpt_cq *cq, void *base, rte_iova_t base_pa)\n+{\n+\tcq->base = base;\n+\tcq->base_pa = base_pa;\n+}\n+\n uint32_t\n iocpt_cq_service(struct iocpt_cq *cq, uint32_t work_to_do,\n \t\t iocpt_cq_cb cb, void *cb_arg)\n@@ -33,10 +59,522 @@ iocpt_cq_service(struct iocpt_cq *cq, uint32_t work_to_do,\n \treturn work_done;\n }\n \n+static int\n+iocpt_q_init(struct iocpt_queue *q, uint8_t type, uint32_t index,\n+\t uint16_t num_descs, uint16_t num_segs, uint32_t socket_id)\n+{\n+\tuint32_t ring_size;\n+\n+\tif (!rte_is_power_of_2(num_descs))\n+\t\treturn -EINVAL;\n+\n+\tring_size = rte_log2_u32(num_descs);\n+\tif (ring_size < 2 || ring_size > 16)\n+\t\treturn -EINVAL;\n+\n+\tq->type = type;\n+\tq->index = index;\n+\tq->num_descs = num_descs;\n+\tq->num_segs = num_segs;\n+\tq->size_mask = num_descs - 1;\n+\tq->head_idx = 0;\n+\tq->tail_idx = 0;\n+\n+\tq->info = rte_calloc_socket(\"iocpt\",\n+\t\t\t\tnum_descs * num_segs, sizeof(void *),\n+\t\t\t\trte_mem_page_size(), socket_id);\n+\tif (q->info == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate queue info\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+iocpt_q_map(struct iocpt_queue *q, void *base, rte_iova_t base_pa)\n+{\n+\tq->base = base;\n+\tq->base_pa = base_pa;\n+}\n+\n+static void\n+iocpt_q_sg_map(struct iocpt_queue *q, void *base, rte_iova_t base_pa)\n+{\n+\tq->sg_base = base;\n+\tq->sg_base_pa = base_pa;\n+}\n+\n+static void\n+iocpt_q_free(struct iocpt_queue *q)\n+{\n+\tif (q->info != NULL) {\n+\t\trte_free(q->info);\n+\t\tq->info = NULL;\n+\t}\n+}\n+\n+static const struct rte_memzone *\n+iocpt_dma_zone_reserve(const char *type_name, uint16_t qid, size_t size,\n+\t\t\tunsigned int align, int socket_id)\n+{\n+\tchar zone_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\tint err;\n+\n+\terr = snprintf(zone_name, sizeof(zone_name),\n+\t\t\t\"iocpt_%s_%u\", type_name, qid);\n+\tif (err >= RTE_MEMZONE_NAMESIZE) {\n+\t\tIOCPT_PRINT(ERR, \"Name %s too long\", type_name);\n+\t\treturn NULL;\n+\t}\n+\n+\tmz = rte_memzone_lookup(zone_name);\n+\tif (mz != NULL)\n+\t\treturn mz;\n+\n+\treturn rte_memzone_reserve_aligned(zone_name, size, socket_id,\n+\t\t\tRTE_MEMZONE_IOVA_CONTIG, align);\n+}\n+\n+static int\n+iocpt_commonq_alloc(struct iocpt_dev *dev,\n+\t\tuint8_t type,\n+\t\tsize_t struct_size,\n+\t\tuint32_t socket_id,\n+\t\tuint32_t index,\n+\t\tconst char *type_name,\n+\t\tuint16_t flags,\n+\t\tuint16_t num_descs,\n+\t\tuint16_t num_segs,\n+\t\tuint16_t desc_size,\n+\t\tuint16_t cq_desc_size,\n+\t\tuint16_t sg_desc_size,\n+\t\tstruct iocpt_common_q **comq)\n+{\n+\tstruct iocpt_common_q *new;\n+\tuint32_t q_size, cq_size, sg_size, total_size;\n+\tvoid *q_base, *cq_base, *sg_base;\n+\trte_iova_t q_base_pa = 0;\n+\trte_iova_t cq_base_pa = 0;\n+\trte_iova_t sg_base_pa = 0;\n+\tsize_t page_size = rte_mem_page_size();\n+\tint err;\n+\n+\t*comq = NULL;\n+\n+\tq_size\t= num_descs * desc_size;\n+\tcq_size = num_descs * cq_desc_size;\n+\tsg_size = num_descs * sg_desc_size;\n+\n+\t/*\n+\t * Note: aligning q_size/cq_size is not enough due to cq_base address\n+\t * aligning as q_base could be not aligned to the page.\n+\t * Adding page_size.\n+\t */\n+\ttotal_size = RTE_ALIGN(q_size, page_size) +\n+\t\tRTE_ALIGN(cq_size, page_size) + page_size;\n+\tif (flags & IOCPT_Q_F_SG)\n+\t\ttotal_size += RTE_ALIGN(sg_size, page_size) + page_size;\n+\n+\tnew = rte_zmalloc_socket(\"iocpt\", struct_size,\n+\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (new == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tnew->dev = dev;\n+\n+\terr = iocpt_q_init(&new->q, type, index, num_descs, num_segs,\n+\t\t\tsocket_id);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Queue initialization failed\");\n+\t\tgoto err_free_q;\n+\t}\n+\n+\terr = iocpt_cq_init(&new->cq, num_descs);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Completion queue initialization failed\");\n+\t\tgoto err_deinit_q;\n+\t}\n+\n+\tnew->base_z = iocpt_dma_zone_reserve(type_name, index, total_size,\n+\t\t\t\t\tIONIC_ALIGN, socket_id);\n+\tif (new->base_z == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot reserve queue DMA memory\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_deinit_cq;\n+\t}\n+\n+\tnew->base = new->base_z->addr;\n+\tnew->base_pa = new->base_z->iova;\n+\n+\tq_base = new->base;\n+\tq_base_pa = new->base_pa;\n+\tiocpt_q_map(&new->q, q_base, q_base_pa);\n+\n+\tcq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, page_size);\n+\tcq_base_pa = RTE_ALIGN(q_base_pa + q_size, page_size);\n+\tiocpt_cq_map(&new->cq, cq_base, cq_base_pa);\n+\n+\tif (flags & IOCPT_Q_F_SG) {\n+\t\tsg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,\n+\t\t\tpage_size);\n+\t\tsg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, page_size);\n+\t\tiocpt_q_sg_map(&new->q, sg_base, sg_base_pa);\n+\t}\n+\n+\tIOCPT_PRINT(DEBUG, \"q_base_pa %#jx cq_base_pa %#jx sg_base_pa %#jx\",\n+\t\tq_base_pa, cq_base_pa, sg_base_pa);\n+\n+\t*comq = new;\n+\n+\treturn 0;\n+\n+err_deinit_cq:\n+err_deinit_q:\n+\tiocpt_q_free(&new->q);\n+err_free_q:\n+\trte_free(new);\n+\treturn err;\n+}\n+\n struct ionic_doorbell *\n iocpt_db_map(struct iocpt_dev *dev, struct iocpt_queue *q)\n {\n \treturn dev->db_pages + q->hw_type;\n }\n \n+static int\n+iocpt_adminq_alloc(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_admin_q *aq;\n+\tuint16_t num_descs = IOCPT_ADMINQ_LENGTH;\n+\tuint16_t flags = 0;\n+\tint err;\n+\n+\terr = iocpt_commonq_alloc(dev,\n+\t\tIOCPT_QTYPE_ADMINQ,\n+\t\tsizeof(struct iocpt_admin_q),\n+\t\trte_socket_id(),\n+\t\t0,\n+\t\t\"admin\",\n+\t\tflags,\n+\t\tnum_descs,\n+\t\t1,\n+\t\tsizeof(struct iocpt_admin_cmd),\n+\t\tsizeof(struct iocpt_admin_comp),\n+\t\t0,\n+\t\t(struct iocpt_common_q **)&aq);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\taq->flags = flags;\n+\n+\tdev->adminq = aq;\n+\n+\treturn 0;\n+}\n+\n+static int\n+iocpt_adminq_init(struct iocpt_dev *dev)\n+{\n+\treturn iocpt_dev_adminq_init(dev);\n+}\n+\n+static void\n+iocpt_adminq_deinit(struct iocpt_dev *dev)\n+{\n+\tdev->adminq->flags &= ~IOCPT_Q_F_INITED;\n+}\n+\n+static void\n+iocpt_adminq_free(struct iocpt_admin_q *aq)\n+{\n+\tif (aq->base_z != NULL) {\n+\t\trte_memzone_free(aq->base_z);\n+\t\taq->base_z = NULL;\n+\t\taq->base = NULL;\n+\t\taq->base_pa = 0;\n+\t}\n+\n+\tiocpt_q_free(&aq->q);\n+\n+\trte_free(aq);\n+}\n+\n+static int\n+iocpt_alloc_objs(struct iocpt_dev *dev)\n+{\n+\tuint32_t bmsize, i;\n+\tuint8_t *bm;\n+\tint err;\n+\n+\tIOCPT_PRINT(DEBUG, \"Crypto: %s\", dev->name);\n+\n+\trte_spinlock_init(&dev->adminq_lock);\n+\trte_spinlock_init(&dev->adminq_service_lock);\n+\n+\terr = iocpt_adminq_alloc(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate admin queue\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_out;\n+\t}\n+\n+\tdev->info_sz = RTE_ALIGN(sizeof(*dev->info), rte_mem_page_size());\n+\tdev->info_z = iocpt_dma_zone_reserve(\"info\", 0, dev->info_sz,\n+\t\t\t\t\tIONIC_ALIGN, dev->socket_id);\n+\tif (dev->info_z == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate dev info memory\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err_free_adminq;\n+\t}\n+\n+\tdev->info = dev->info_z->addr;\n+\tdev->info_pa = dev->info_z->iova;\n+\n+\tbmsize = rte_bitmap_get_memory_footprint(dev->max_sessions);\n+\tbm = rte_malloc_socket(\"iocpt\", bmsize,\n+\t\t\tRTE_CACHE_LINE_SIZE, dev->socket_id);\n+\tif (bm == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate %uB bitmap memory\", bmsize);\n+\t\terr = -ENOMEM;\n+\t\tgoto err_free_dmazone;\n+\t}\n+\n+\tdev->sess_bm = rte_bitmap_init(dev->max_sessions, bm, bmsize);\n+\tif (dev->sess_bm == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot initialize bitmap\");\n+\t\terr = -EFAULT;\n+\t\tgoto err_free_bm;\n+\t}\n+\tfor (i = 0; i < dev->max_sessions; i++)\n+\t\trte_bitmap_set(dev->sess_bm, i);\n+\n+\treturn 0;\n+\n+err_free_bm:\n+\trte_free(bm);\n+err_free_dmazone:\n+\trte_memzone_free(dev->info_z);\n+\tdev->info_z = NULL;\n+\tdev->info = NULL;\n+\tdev->info_pa = 0;\n+err_free_adminq:\n+\tiocpt_adminq_free(dev->adminq);\n+\tdev->adminq = NULL;\n+err_out:\n+\treturn err;\n+}\n+\n+static int\n+iocpt_init(struct iocpt_dev *dev)\n+{\n+\tint err;\n+\n+\tmemset(&dev->stats_base, 0, sizeof(dev->stats_base));\n+\n+\t/* Uses dev_cmds */\n+\terr = iocpt_dev_init(dev, dev->info_pa);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\terr = iocpt_adminq_init(dev);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tdev->state |= IOCPT_DEV_F_INITED;\n+\n+\treturn 0;\n+}\n+\n+void\n+iocpt_configure(struct iocpt_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+void\n+iocpt_deinit(struct iocpt_dev *dev)\n+{\n+\tIOCPT_PRINT_CALL();\n+\n+\tif (!(dev->state & IOCPT_DEV_F_INITED))\n+\t\treturn;\n+\n+\tiocpt_adminq_deinit(dev);\n+\n+\tdev->state &= ~IOCPT_DEV_F_INITED;\n+}\n+\n+static void\n+iocpt_free_objs(struct iocpt_dev *dev)\n+{\n+\tIOCPT_PRINT_CALL();\n+\n+\tif (dev->sess_bm != NULL) {\n+\t\trte_bitmap_free(dev->sess_bm);\n+\t\trte_free(dev->sess_bm);\n+\t\tdev->sess_bm = NULL;\n+\t}\n+\n+\tif (dev->adminq != NULL) {\n+\t\tiocpt_adminq_free(dev->adminq);\n+\t\tdev->adminq = NULL;\n+\t}\n+\n+\tif (dev->info != NULL) {\n+\t\trte_memzone_free(dev->info_z);\n+\t\tdev->info_z = NULL;\n+\t\tdev->info = NULL;\n+\t\tdev->info_pa = 0;\n+\t}\n+}\n+\n+static int\n+iocpt_devargs(struct rte_devargs *devargs, struct iocpt_dev *dev)\n+{\n+\tRTE_SET_USED(devargs);\n+\tRTE_SET_USED(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+iocpt_probe(void *bus_dev, struct rte_device *rte_dev,\n+\tstruct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf,\n+\tuint8_t driver_id, uint8_t socket_id)\n+{\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t\"iocpt\",\n+\t\tsizeof(struct iocpt_dev),\n+\t\tsocket_id,\n+\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS\n+\t};\n+\tstruct rte_cryptodev *cdev;\n+\tstruct iocpt_dev *dev;\n+\tuint32_t i, sig;\n+\tint err;\n+\n+\t/* Check structs (trigger error at compilation time) */\n+\tiocpt_struct_size_checks();\n+\n+\t/* Multi-process not supported */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\terr = -EPERM;\n+\t\tgoto err;\n+\t}\n+\n+\tcdev = rte_cryptodev_pmd_create(rte_dev->name, rte_dev, &init_params);\n+\tif (cdev == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"OOM\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tdev = cdev->data->dev_private;\n+\tdev->crypto_dev = cdev;\n+\tdev->bus_dev = bus_dev;\n+\tdev->intf = intf;\n+\tdev->driver_id = driver_id;\n+\tdev->socket_id = socket_id;\n+\n+\tfor (i = 0; i < bars->num_bars; i++) {\n+\t\tstruct ionic_dev_bar *bar = &bars->bar[i];\n+\n+\t\tIOCPT_PRINT(DEBUG,\n+\t\t\t\"bar[%u] = { .va = %p, .pa = %#jx, .len = %lu }\",\n+\t\t\ti, bar->vaddr, bar->bus_addr, bar->len);\n+\t\tif (bar->vaddr == NULL) {\n+\t\t\tIOCPT_PRINT(ERR, \"Null bar found, aborting\");\n+\t\t\terr = -EFAULT;\n+\t\t\tgoto err_destroy_crypto_dev;\n+\t\t}\n+\n+\t\tdev->bars.bar[i].vaddr = bar->vaddr;\n+\t\tdev->bars.bar[i].bus_addr = bar->bus_addr;\n+\t\tdev->bars.bar[i].len = bar->len;\n+\t}\n+\tdev->bars.num_bars = bars->num_bars;\n+\n+\terr = iocpt_devargs(rte_dev->devargs, dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot parse device arguments\");\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_setup_bars(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot setup BARs: %d, aborting\", err);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\tsig = ioread32(&dev->dev_info->signature);\n+\tif (sig != IOCPT_DEV_INFO_SIGNATURE) {\n+\t\tIOCPT_PRINT(ERR, \"Incompatible firmware signature %#x\", sig);\n+\t\terr = -EFAULT;\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\tfor (i = 0; i < IOCPT_FWVERS_BUFLEN; i++)\n+\t\tdev->fw_version[i] = ioread8(&dev->dev_info->fw_version[i]);\n+\tdev->fw_version[IOCPT_FWVERS_BUFLEN - 1] = '\\0';\n+\tIOCPT_PRINT(DEBUG, \"%s firmware: %s\", dev->name, dev->fw_version);\n+\n+\terr = iocpt_dev_identify(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot identify device: %d, aborting\",\n+\t\t\terr);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_alloc_objs(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot alloc device objects: %d\", err);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_init(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot init device: %d, aborting\", err);\n+\t\tgoto err_free_objs;\n+\t}\n+\n+\treturn 0;\n+\n+err_free_objs:\n+\tiocpt_free_objs(dev);\n+err_destroy_crypto_dev:\n+\trte_cryptodev_pmd_destroy(cdev);\n+err:\n+\treturn err;\n+}\n+\n+int\n+iocpt_remove(struct rte_device *rte_dev)\n+{\n+\tstruct rte_cryptodev *cdev;\n+\tstruct iocpt_dev *dev;\n+\n+\tcdev = rte_cryptodev_pmd_get_named_dev(rte_dev->name);\n+\tif (cdev == NULL) {\n+\t\tIOCPT_PRINT(DEBUG, \"Cannot find device %s\", rte_dev->name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev = cdev->data->dev_private;\n+\n+\tiocpt_deinit(dev);\n+\n+\tiocpt_dev_reset(dev);\n+\n+\tiocpt_free_objs(dev);\n+\n+\trte_cryptodev_pmd_destroy(cdev);\n+\n+\treturn 0;\n+}\n+\n RTE_LOG_REGISTER_DEFAULT(iocpt_logtype, NOTICE);\ndiff --git a/drivers/crypto/ionic/ionic_crypto_vdev.c b/drivers/crypto/ionic/ionic_crypto_vdev.c\nnew file mode 100644\nindex 0000000000..d15acf660a\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_vdev.c\n@@ -0,0 +1,128 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <stdint.h>\n+#include <errno.h>\n+\n+#include <rte_errno.h>\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_eal.h>\n+#include <bus_vdev_driver.h>\n+#include <rte_dev.h>\n+#include <rte_string_fns.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+#define IOCPT_VDEV_DEV_BAR 0\n+#define IOCPT_VDEV_INTR_CTL_BAR 1\n+#define IOCPT_VDEV_INTR_CFG_BAR 2\n+#define IOCPT_VDEV_DB_BAR 3\n+#define IOCPT_VDEV_BARS_MAX 4\n+\n+#define IOCPT_VDEV_DEV_INFO_REGS_OFFSET 0x0000\n+#define IOCPT_VDEV_DEV_CMD_REGS_OFFSET 0x0800\n+\n+#define IOCPT_VDEV_FW_WAIT_US 1000 /* 1ms */\n+#define IOCPT_VDEV_FW_WAIT_MAX 5000 /* 5s */\n+\n+static int\n+iocpt_vdev_setup_bars(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_dev_bars *bars = &dev->bars;\n+\tuint8_t *bar0_base;\n+\tuint32_t fw_waits = 0;\n+\tuint8_t fw;\n+\n+\tIOCPT_PRINT_CALL();\n+\n+\t/* BAR0: dev_cmd */\n+\tbar0_base = bars->bar[IOCPT_VDEV_DEV_BAR].vaddr;\n+\tdev->dev_info = (union iocpt_dev_info_regs *)\n+\t\t&bar0_base[IOCPT_VDEV_DEV_INFO_REGS_OFFSET];\n+\tdev->dev_cmd = (union iocpt_dev_cmd_regs *)\n+\t\t&bar0_base[IOCPT_VDEV_DEV_CMD_REGS_OFFSET];\n+\n+\t/* BAR1: interrupts */\n+\tdev->intr_ctrl = (void *)bars->bar[IOCPT_VDEV_INTR_CTL_BAR].vaddr;\n+\n+\t/* BAR3: doorbells */\n+\tdev->db_pages = (void *)bars->bar[IOCPT_VDEV_DB_BAR].vaddr;\n+\n+\t/* Wait for the FW to indicate readiness */\n+\twhile (1) {\n+\t\tfw = ioread8(&dev->dev_info->fw_status);\n+\t\tif ((fw & IOCPT_FW_STS_F_RUNNING) != 0)\n+\t\t\tbreak;\n+\n+\t\tif (fw_waits > IOCPT_VDEV_FW_WAIT_MAX) {\n+\t\t\tIOCPT_PRINT(ERR, \"Firmware readiness bit not set\");\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\n+\t\tfw_waits++;\n+\t\trte_delay_us_block(IOCPT_VDEV_FW_WAIT_US);\n+\t}\n+\tIOCPT_PRINT(DEBUG, \"Firmware ready (%u waits)\", fw_waits);\n+\n+\tdev->name = rte_vdev_device_name(dev->bus_dev);\n+\n+\treturn 0;\n+}\n+\n+static void\n+iocpt_vdev_unmap_bars(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_dev_bars *bars = &dev->bars;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < IOCPT_VDEV_BARS_MAX; i++)\n+\t\tionic_uio_rel_rsrc(dev->name, i, &bars->bar[i]);\n+}\n+\n+static uint8_t iocpt_vdev_driver_id;\n+static const struct iocpt_dev_intf iocpt_vdev_intf = {\n+\t.setup_bars = iocpt_vdev_setup_bars,\n+\t.unmap_bars = iocpt_vdev_unmap_bars,\n+};\n+\n+static int\n+iocpt_vdev_probe(struct rte_vdev_device *vdev)\n+{\n+\tstruct iocpt_dev_bars bars = {};\n+\tconst char *name = rte_vdev_device_name(vdev);\n+\tunsigned int i;\n+\n+\tIOCPT_PRINT(NOTICE, \"Initializing device %s%s\", name,\n+\t\trte_eal_process_type() == RTE_PROC_SECONDARY ?\n+\t\t\t\" [SECONDARY]\" : \"\");\n+\n+\tionic_uio_scan_mcrypt_devices();\n+\n+\tfor (i = 0; i < IOCPT_VDEV_BARS_MAX; i++)\n+\t\tionic_uio_get_rsrc(name, i, &bars.bar[i]);\n+\n+\tbars.num_bars = IOCPT_VDEV_BARS_MAX;\n+\n+\treturn iocpt_probe((void *)vdev, &vdev->device,\n+\t\t\t&bars, &iocpt_vdev_intf,\n+\t\t\tiocpt_vdev_driver_id, rte_socket_id());\n+}\n+\n+static int\n+iocpt_vdev_remove(struct rte_vdev_device *vdev)\n+{\n+\treturn iocpt_remove(&vdev->device);\n+}\n+\n+static struct rte_vdev_driver rte_vdev_iocpt_pmd = {\n+\t.probe = iocpt_vdev_probe,\n+\t.remove = iocpt_vdev_remove,\n+};\n+\n+static struct cryptodev_driver rte_vdev_iocpt_drv;\n+\n+RTE_PMD_REGISTER_VDEV(crypto_ionic, rte_vdev_iocpt_pmd);\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(rte_vdev_iocpt_drv, rte_vdev_iocpt_pmd.driver,\n+\t\tiocpt_vdev_driver_id);\ndiff --git a/drivers/crypto/ionic/meson.build b/drivers/crypto/ionic/meson.build\nindex 6eaef41196..a6e0a1d415 100644\n--- a/drivers/crypto/ionic/meson.build\n+++ b/drivers/crypto/ionic/meson.build\n@@ -1,11 +1,13 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright 2021-2024 Advanced Micro Devices, Inc.\n \n+deps += ['bus_vdev']\n deps += ['common_ionic']\n \n sources = files(\n 'ionic_crypto_cmds.c',\n 'ionic_crypto_main.c',\n+ 'ionic_crypto_vdev.c',\n )\n name = 'ionic_crypto'\n \n", "prefixes": [ "4/6" ] }