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GET /api/patches/139554/?format=api
{ "id": 139554, "url": "https://patches.dpdk.org/api/patches/139554/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-3-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240419195310.21432-3-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240419195310.21432-3-andrew.boyer@amd.com", "date": "2024-04-19T19:53:06", "name": "[2/6] crypto/ionic: add device and admin command handlers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4f236785a43530e1109740d4c3313ff595930106", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20240419195310.21432-3-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31795, "url": "https://patches.dpdk.org/api/series/31795/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=31795", "date": "2024-04-19T19:53:04", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 1, "mbox": "https://patches.dpdk.org/series/31795/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/139554/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/139554/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=p4Zu10FNFCoPYbj+XUMZy4OXcl0oF7ReUB21nQI2jzyvOR5ILG4PkX7exPhHLtl57NP0sLttTtBhRT8euZEw0J7Imc+RFvUHdvtbhe1Fs9MZKWDsNzaJDDz3BCrE5Cs31qZMZj2VoaVhdsG2yMzwvRRsH7cqoDG0RwB/oXKwjXs=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Akhil Goyal <gakhil@marvell.com>, Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 2/6] crypto/ionic: add device and admin command handlers", "Date": "Fri, 19 Apr 2024 12:53:06 -0700", "Message-ID": "<20240419195310.21432-3-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": 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"X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(376005)(82310400014)(36860700004)(1800799015); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Apr 2024 19:53:44.9705 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7c1d268b-6255-4ae0-369b-08dc60aa6be0", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF0000150B.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB8131", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This defines the handlers used for device (register-based) and\nadmin (adminq-based) commands.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/crypto/ionic/ionic_crypto.h | 210 ++++++++\n drivers/crypto/ionic/ionic_crypto_cmds.c | 651 +++++++++++++++++++++++\n drivers/crypto/ionic/ionic_crypto_main.c | 42 ++\n drivers/crypto/ionic/meson.build | 12 +\n 4 files changed, 915 insertions(+)\n create mode 100644 drivers/crypto/ionic/ionic_crypto.h\n create mode 100644 drivers/crypto/ionic/ionic_crypto_cmds.c\n create mode 100644 drivers/crypto/ionic/ionic_crypto_main.c\n create mode 100644 drivers/crypto/ionic/meson.build", "diff": "diff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h\nnew file mode 100644\nindex 0000000000..958e611337\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto.h\n@@ -0,0 +1,210 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef _IONIC_CRYPTO_H_\n+#define _IONIC_CRYPTO_H_\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include <rte_log.h>\n+#include <rte_bitmap.h>\n+\n+#include \"ionic_common.h\"\n+#include \"ionic_crypto_if.h\"\n+#include \"ionic_regs.h\"\n+\n+#define IOCPT_ADMINQ_LENGTH\t\t16\t/* must be a power of two */\n+\n+#define IOCPT_CRYPTOQ_WAIT\t\t10\t/* 1s */\n+\n+extern int iocpt_logtype;\n+#define RTE_LOGTYPE_IOCPT iocpt_logtype\n+\n+#define IOCPT_PRINT(level, ...)\t\t\t\t\t\t\\\n+\tRTE_LOG_LINE_PREFIX(level, IOCPT, \"%s(): \", __func__, __VA_ARGS__)\n+\n+#define IOCPT_PRINT_CALL() IOCPT_PRINT(DEBUG, \" >>\")\n+\n+struct iocpt_qtype_info {\n+\tuint8_t\t version;\n+\tuint8_t\t supported;\n+\tuint64_t features;\n+\tuint16_t desc_sz;\n+\tuint16_t comp_sz;\n+\tuint16_t sg_desc_sz;\n+\tuint16_t max_sg_elems;\n+\tuint16_t sg_desc_stride;\n+};\n+\n+#define IOCPT_Q_F_INITED\tBIT(0)\n+#define IOCPT_Q_F_DEFERRED\tBIT(1)\n+#define IOCPT_Q_F_SG\t\tBIT(2)\n+\n+#define Q_NEXT_TO_POST(_q, _n)\t(((_q)->head_idx + (_n)) & ((_q)->size_mask))\n+#define Q_NEXT_TO_SRVC(_q, _n)\t(((_q)->tail_idx + (_n)) & ((_q)->size_mask))\n+\n+#define IOCPT_INFO_SZ(_q)\t((_q)->num_segs * sizeof(void *))\n+#define IOCPT_INFO_IDX(_q, _i)\t((_i) * (_q)->num_segs)\n+#define IOCPT_INFO_PTR(_q, _i)\t(&(_q)->info[IOCPT_INFO_IDX((_q), _i)])\n+\n+struct iocpt_queue {\n+\tuint16_t num_descs;\n+\tuint16_t num_segs;\n+\tuint16_t head_idx;\n+\tuint16_t tail_idx;\n+\tuint16_t size_mask;\n+\tuint8_t type;\n+\tuint8_t hw_type;\n+\tvoid *base;\n+\tvoid *sg_base;\n+\tstruct ionic_doorbell __iomem *db;\n+\tvoid **info;\n+\n+\tuint32_t index;\n+\tuint32_t hw_index;\n+\trte_iova_t base_pa;\n+\trte_iova_t sg_base_pa;\n+};\n+\n+struct iocpt_cq {\n+\tuint16_t tail_idx;\n+\tuint16_t num_descs;\n+\tuint16_t size_mask;\n+\tbool done_color;\n+\tvoid *base;\n+\trte_iova_t base_pa;\n+};\n+\n+#define IOCPT_COMMON_FIELDS\t\t\t\t\\\n+\tstruct iocpt_queue q;\t\t\t\t\\\n+\tstruct iocpt_cq cq;\t\t\t\t\\\n+\tstruct iocpt_dev *dev;\t\t\t\t\\\n+\tconst struct rte_memzone *base_z;\t\t\\\n+\tvoid *base;\t\t\t\t\t\\\n+\trte_iova_t base_pa\n+\n+struct iocpt_common_q {\n+\tIOCPT_COMMON_FIELDS;\n+};\n+\n+struct iocpt_admin_q {\n+\tIOCPT_COMMON_FIELDS;\n+\n+\tuint16_t flags;\n+};\n+\n+#define IOCPT_DEV_F_INITED\t\tBIT(0)\n+#define IOCPT_DEV_F_UP\t\t\tBIT(1)\n+#define IOCPT_DEV_F_FW_RESET\t\tBIT(2)\n+\n+/* Combined dev / LIF object */\n+struct iocpt_dev {\n+\tconst char *name;\n+\tchar fw_version[IOCPT_FWVERS_BUFLEN];\n+\tstruct iocpt_identity ident;\n+\n+\tvoid *bus_dev;\n+\tstruct rte_cryptodev *crypto_dev;\n+\n+\tunion iocpt_dev_info_regs __iomem *dev_info;\n+\tunion iocpt_dev_cmd_regs __iomem *dev_cmd;\n+\n+\tstruct ionic_doorbell __iomem *db_pages;\n+\tstruct ionic_intr __iomem *intr_ctrl;\n+\n+\tuint32_t max_qps;\n+\tuint32_t max_sessions;\n+\tuint16_t state;\n+\tuint8_t driver_id;\n+\tuint8_t socket_id;\n+\n+\trte_spinlock_t adminq_lock;\n+\trte_spinlock_t adminq_service_lock;\n+\n+\tstruct iocpt_admin_q *adminq;\n+\n+\tuint64_t features;\n+\tuint32_t hw_features;\n+\n+\tuint32_t info_sz;\n+\tstruct iocpt_lif_info *info;\n+\trte_iova_t info_pa;\n+\tconst struct rte_memzone *info_z;\n+\n+\tstruct iocpt_qtype_info qtype_info[IOCPT_QTYPE_MAX];\n+\tuint8_t qtype_ver[IOCPT_QTYPE_MAX];\n+\n+\tstruct rte_cryptodev_stats stats_base;\n+};\n+\n+/** iocpt_admin_ctx - Admin command context.\n+ * @pending_work:\tFlag that indicates a completion.\n+ * @cmd:\t\tAdmin command (64B) to be copied to the queue.\n+ * @comp:\t\tAdmin completion (16B) copied from the queue.\n+ */\n+struct iocpt_admin_ctx {\n+\tbool pending_work;\n+\tunion iocpt_adminq_cmd cmd;\n+\tunion iocpt_adminq_comp comp;\n+};\n+\n+int iocpt_dev_identify(struct iocpt_dev *dev);\n+int iocpt_dev_init(struct iocpt_dev *dev, rte_iova_t info_pa);\n+int iocpt_dev_adminq_init(struct iocpt_dev *dev);\n+void iocpt_dev_reset(struct iocpt_dev *dev);\n+\n+int iocpt_adminq_post_wait(struct iocpt_dev *dev, struct iocpt_admin_ctx *ctx);\n+\n+struct ionic_doorbell __iomem *iocpt_db_map(struct iocpt_dev *dev,\n+\tstruct iocpt_queue *q);\n+\n+typedef bool (*iocpt_cq_cb)(struct iocpt_cq *cq, uint16_t cq_desc_index,\n+\t\tvoid *cb_arg);\n+uint32_t iocpt_cq_service(struct iocpt_cq *cq, uint32_t work_to_do,\n+\tiocpt_cq_cb cb, void *cb_arg);\n+\n+static inline uint16_t\n+iocpt_q_space_avail(struct iocpt_queue *q)\n+{\n+\tuint16_t avail = q->tail_idx;\n+\n+\tif (q->head_idx >= avail)\n+\t\tavail += q->num_descs - q->head_idx - 1;\n+\telse\n+\t\tavail -= q->head_idx + 1;\n+\n+\treturn avail;\n+}\n+\n+static inline void\n+iocpt_q_flush(struct iocpt_queue *q)\n+{\n+\tuint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx;\n+\n+#if defined(RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA)\n+\t/* On some devices the standard 'dmb' barrier is insufficient */\n+\tasm volatile(\"dsb st\" : : : \"memory\");\n+\trte_write64_relaxed(rte_cpu_to_le_64(val), q->db);\n+#else\n+\trte_write64(rte_cpu_to_le_64(val), q->db);\n+#endif\n+}\n+\n+static inline bool\n+iocpt_is_embedded(void)\n+{\n+#if defined(RTE_LIBRTE_IONIC_PMD_EMBEDDED)\n+\treturn true;\n+#else\n+\treturn false;\n+#endif\n+}\n+\n+#endif /* _IONIC_CRYPTO_H_ */\ndiff --git a/drivers/crypto/ionic/ionic_crypto_cmds.c b/drivers/crypto/ionic/ionic_crypto_cmds.c\nnew file mode 100644\nindex 0000000000..44e6985eb1\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_cmds.c\n@@ -0,0 +1,651 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <stdbool.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+/* queuetype support level */\n+static const uint8_t iocpt_qtype_vers[IOCPT_QTYPE_MAX] = {\n+\t[IOCPT_QTYPE_ADMINQ] = 0, /* 0 = Base version */\n+\t[IOCPT_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */\n+\t[IOCPT_QTYPE_CRYPTOQ] = 0, /* 0 = Base version */\n+};\n+\n+static const char *\n+iocpt_error_to_str(enum iocpt_status_code code)\n+{\n+\tswitch (code) {\n+\tcase IOCPT_RC_SUCCESS:\n+\t\treturn \"IOCPT_RC_SUCCESS\";\n+\tcase IOCPT_RC_EVERSION:\n+\t\treturn \"IOCPT_RC_EVERSION\";\n+\tcase IOCPT_RC_EOPCODE:\n+\t\treturn \"IOCPT_RC_EOPCODE\";\n+\tcase IOCPT_RC_EIO:\n+\t\treturn \"IOCPT_RC_EIO\";\n+\tcase IOCPT_RC_EPERM:\n+\t\treturn \"IOCPT_RC_EPERM\";\n+\tcase IOCPT_RC_EQID:\n+\t\treturn \"IOCPT_RC_EQID\";\n+\tcase IOCPT_RC_EQTYPE:\n+\t\treturn \"IOCPT_RC_EQTYPE\";\n+\tcase IOCPT_RC_ENOENT:\n+\t\treturn \"IOCPT_RC_ENOENT\";\n+\tcase IOCPT_RC_EINTR:\n+\t\treturn \"IOCPT_RC_EINTR\";\n+\tcase IOCPT_RC_EAGAIN:\n+\t\treturn \"IOCPT_RC_EAGAIN\";\n+\tcase IOCPT_RC_ENOMEM:\n+\t\treturn \"IOCPT_RC_ENOMEM\";\n+\tcase IOCPT_RC_EFAULT:\n+\t\treturn \"IOCPT_RC_EFAULT\";\n+\tcase IOCPT_RC_EBUSY:\n+\t\treturn \"IOCPT_RC_EBUSY\";\n+\tcase IOCPT_RC_EEXIST:\n+\t\treturn \"IOCPT_RC_EEXIST\";\n+\tcase IOCPT_RC_EINVAL:\n+\t\treturn \"IOCPT_RC_EINVAL\";\n+\tcase IOCPT_RC_ENOSPC:\n+\t\treturn \"IOCPT_RC_ENOSPC\";\n+\tcase IOCPT_RC_ERANGE:\n+\t\treturn \"IOCPT_RC_ERANGE\";\n+\tcase IOCPT_RC_BAD_ADDR:\n+\t\treturn \"IOCPT_RC_BAD_ADDR\";\n+\tcase IOCPT_RC_DEV_CMD:\n+\t\treturn \"IOCPT_RC_DEV_CMD\";\n+\tcase IOCPT_RC_ERROR:\n+\t\treturn \"IOCPT_RC_ERROR\";\n+\tdefault:\n+\t\treturn \"IOCPT_RC_UNKNOWN\";\n+\t}\n+}\n+\n+static const char *\n+iocpt_opcode_to_str(enum iocpt_cmd_opcode opcode)\n+{\n+\tswitch (opcode) {\n+\tcase IOCPT_CMD_NOP:\n+\t\treturn \"IOCPT_CMD_NOP\";\n+\tcase IOCPT_CMD_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_IDENTIFY\";\n+\tcase IOCPT_CMD_RESET:\n+\t\treturn \"IOCPT_CMD_RESET\";\n+\tcase IOCPT_CMD_LIF_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_LIF_IDENTIFY\";\n+\tcase IOCPT_CMD_LIF_INIT:\n+\t\treturn \"IOCPT_CMD_LIF_INIT\";\n+\tcase IOCPT_CMD_LIF_RESET:\n+\t\treturn \"IOCPT_CMD_LIF_RESET\";\n+\tcase IOCPT_CMD_LIF_GETATTR:\n+\t\treturn \"IOCPT_CMD_LIF_GETATTR\";\n+\tcase IOCPT_CMD_LIF_SETATTR:\n+\t\treturn \"IOCPT_CMD_LIF_SETATTR\";\n+\tcase IOCPT_CMD_Q_IDENTIFY:\n+\t\treturn \"IOCPT_CMD_Q_IDENTIFY\";\n+\tcase IOCPT_CMD_Q_INIT:\n+\t\treturn \"IOCPT_CMD_Q_INIT\";\n+\tcase IOCPT_CMD_Q_CONTROL:\n+\t\treturn \"IOCPT_CMD_Q_CONTROL\";\n+\tcase IOCPT_CMD_SESS_CONTROL:\n+\t\treturn \"IOCPT_CMD_SESS_CONTROL\";\n+\tdefault:\n+\t\treturn \"DEVCMD_UNKNOWN\";\n+\t}\n+}\n+\n+/* Dev_cmd Interface */\n+\n+static void\n+iocpt_dev_cmd_go(struct iocpt_dev *dev, union iocpt_dev_cmd *cmd)\n+{\n+\tuint32_t cmd_size = RTE_DIM(cmd->words);\n+\tuint32_t i;\n+\n+\tIOCPT_PRINT(DEBUG, \"Sending %s (%d) via dev_cmd\",\n+\t\tiocpt_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);\n+\n+\tfor (i = 0; i < cmd_size; i++)\n+\t\tiowrite32(cmd->words[i], &dev->dev_cmd->cmd.words[i]);\n+\n+\tiowrite32(0, &dev->dev_cmd->done);\n+\tiowrite32(1, &dev->dev_cmd->doorbell);\n+}\n+\n+static int\n+iocpt_dev_cmd_wait(struct iocpt_dev *dev, unsigned long max_wait)\n+{\n+\tunsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US;\n+\tunsigned long max_wait_usec = max_wait * 1000000L;\n+\tunsigned long elapsed_usec = 0;\n+\tint done;\n+\n+\t/* Wait for dev cmd to complete.. but no more than max_wait sec */\n+\n+\tdo {\n+\t\tdone = ioread32(&dev->dev_cmd->done) & IONIC_DEV_CMD_DONE;\n+\t\tif (done != 0) {\n+\t\t\tIOCPT_PRINT(DEBUG, \"DEVCMD %d done took %lu usecs\",\n+\t\t\t\tioread8(&dev->dev_cmd->cmd.cmd.opcode),\n+\t\t\t\telapsed_usec);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trte_delay_us_block(step_usec);\n+\n+\t\telapsed_usec += step_usec;\n+\t} while (elapsed_usec < max_wait_usec);\n+\n+\tIOCPT_PRINT(ERR, \"DEVCMD %d timeout after %lu usecs\",\n+\t\tioread8(&dev->dev_cmd->cmd.cmd.opcode), elapsed_usec);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static void\n+iocpt_dev_cmd_comp(struct iocpt_dev *dev, void *mem)\n+{\n+\tunion iocpt_dev_cmd_comp *comp = mem;\n+\tuint32_t comp_size = RTE_DIM(comp->words);\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < comp_size; i++)\n+\t\tcomp->words[i] = ioread32(&dev->dev_cmd->comp.words[i]);\n+}\n+\n+\n+static int\n+iocpt_dev_cmd_wait_check(struct iocpt_dev *dev, unsigned long max_wait)\n+{\n+\tuint8_t status;\n+\tint err;\n+\n+\terr = iocpt_dev_cmd_wait(dev, max_wait);\n+\tif (err == 0) {\n+\t\tstatus = ioread8(&dev->dev_cmd->comp.comp.status);\n+\t\tif (status == IOCPT_RC_EAGAIN)\n+\t\t\terr = -EAGAIN;\n+\t\telse if (status != 0)\n+\t\t\terr = -EIO;\n+\t}\n+\n+\tIOCPT_PRINT(DEBUG, \"dev_cmd returned %d\", err);\n+\treturn err;\n+}\n+\n+/* Dev_cmds */\n+\n+static void\n+iocpt_dev_cmd_reset(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.reset.opcode = IOCPT_CMD_RESET,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_identify(struct iocpt_dev *dev, uint8_t ver)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_identify.opcode = IOCPT_CMD_LIF_IDENTIFY,\n+\t\t.lif_identify.type = IOCPT_LIF_TYPE_DEFAULT,\n+\t\t.lif_identify.ver = ver,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_init(struct iocpt_dev *dev, rte_iova_t info_pa)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_init.opcode = IOCPT_CMD_LIF_INIT,\n+\t\t.lif_init.type = IOCPT_LIF_TYPE_DEFAULT,\n+\t\t.lif_init.info_pa = info_pa,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_lif_reset(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.lif_reset.opcode = IOCPT_CMD_LIF_RESET,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_queue_identify(struct iocpt_dev *dev,\n+\t\tuint8_t qtype, uint8_t qver)\n+{\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.q_identify.opcode = IOCPT_CMD_Q_IDENTIFY,\n+\t\t.q_identify.type = qtype,\n+\t\t.q_identify.ver = qver,\n+\t};\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+static void\n+iocpt_dev_cmd_adminq_init(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_queue *q = &dev->adminq->q;\n+\tstruct iocpt_cq *cq = &dev->adminq->cq;\n+\n+\tunion iocpt_dev_cmd cmd = {\n+\t\t.q_init.opcode = IOCPT_CMD_Q_INIT,\n+\t\t.q_init.type = q->type,\n+\t\t.q_init.ver = dev->qtype_info[q->type].version,\n+\t\t.q_init.index = rte_cpu_to_le_32(q->index),\n+\t\t.q_init.flags = rte_cpu_to_le_16(IOCPT_QINIT_F_ENA),\n+\t\t.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n+\t\t.q_init.ring_size = rte_log2_u32(q->num_descs),\n+\t\t.q_init.ring_base = rte_cpu_to_le_64(q->base_pa),\n+\t\t.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n+\t};\n+\n+\tIOCPT_PRINT(DEBUG, \"adminq.q_init.ver %u\", cmd.q_init.ver);\n+\n+\tiocpt_dev_cmd_go(dev, &cmd);\n+}\n+\n+/* Dev_cmd consumers */\n+\n+static void\n+iocpt_queue_identify(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_q_identity *q_ident = &dev->ident.q;\n+\tuint32_t q_words = RTE_DIM(q_ident->words);\n+\tuint32_t cmd_words = RTE_DIM(dev->dev_cmd->data);\n+\tuint32_t i, nwords, qtype;\n+\tint err;\n+\n+\tfor (qtype = 0; qtype < RTE_DIM(iocpt_qtype_vers); qtype++) {\n+\t\tstruct iocpt_qtype_info *qti = &dev->qtype_info[qtype];\n+\n+\t\t/* Filter out the types this driver knows about */\n+\t\tswitch (qtype) {\n+\t\tcase IOCPT_QTYPE_ADMINQ:\n+\t\tcase IOCPT_QTYPE_NOTIFYQ:\n+\t\tcase IOCPT_QTYPE_CRYPTOQ:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tmemset(qti, 0, sizeof(*qti));\n+\n+\t\tif (iocpt_is_embedded()) {\n+\t\t\t/* When embedded, FW will always match the driver */\n+\t\t\tqti->version = iocpt_qtype_vers[qtype];\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* On the host, query the FW for info */\n+\t\tiocpt_dev_cmd_queue_identify(dev,\n+\t\t\tqtype, iocpt_qtype_vers[qtype]);\n+\t\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\t\tif (err == -EINVAL) {\n+\t\t\tIOCPT_PRINT(ERR, \"qtype %d not supported\", qtype);\n+\t\t\tcontinue;\n+\t\t} else if (err == -EIO) {\n+\t\t\tIOCPT_PRINT(ERR, \"q_ident failed, older FW\");\n+\t\t\treturn;\n+\t\t} else if (err != 0) {\n+\t\t\tIOCPT_PRINT(ERR, \"q_ident failed, qtype %d: %d\",\n+\t\t\t\tqtype, err);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tnwords = RTE_MIN(q_words, cmd_words);\n+\t\tfor (i = 0; i < nwords; i++)\n+\t\t\tq_ident->words[i] = ioread32(&dev->dev_cmd->data[i]);\n+\n+\t\tqti->version = q_ident->version;\n+\t\tqti->supported = q_ident->supported;\n+\t\tqti->features = rte_le_to_cpu_64(q_ident->features);\n+\t\tqti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz);\n+\t\tqti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz);\n+\t\tqti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz);\n+\t\tqti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);\n+\t\tqti->sg_desc_stride =\n+\t\t\trte_le_to_cpu_16(q_ident->sg_desc_stride);\n+\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].version = %d\",\n+\t\t\tqtype, qti->version);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].supported = %#x\",\n+\t\t\tqtype, qti->supported);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].features = %#jx\",\n+\t\t\tqtype, qti->features);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].desc_sz = %d\",\n+\t\t\tqtype, qti->desc_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].comp_sz = %d\",\n+\t\t\tqtype, qti->comp_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].sg_desc_sz = %d\",\n+\t\t\tqtype, qti->sg_desc_sz);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].max_sg_elems = %d\",\n+\t\t\tqtype, qti->max_sg_elems);\n+\t\tIOCPT_PRINT(DEBUG, \" qtype[%d].sg_desc_stride = %d\",\n+\t\t\tqtype, qti->sg_desc_stride);\n+\t}\n+}\n+\n+int\n+iocpt_dev_identify(struct iocpt_dev *dev)\n+{\n+\tunion iocpt_lif_identity *ident = &dev->ident.lif;\n+\tunion iocpt_lif_config *cfg = &ident->config;\n+\tuint64_t features;\n+\tuint32_t cmd_size = RTE_DIM(dev->dev_cmd->data);\n+\tuint32_t dev_size = RTE_DIM(ident->words);\n+\tuint32_t i, nwords;\n+\tint err;\n+\n+\tmemset(ident, 0, sizeof(*ident));\n+\n+\tiocpt_dev_cmd_lif_identify(dev, IOCPT_IDENTITY_VERSION_1);\n+\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tnwords = RTE_MIN(dev_size, cmd_size);\n+\tfor (i = 0; i < nwords; i++)\n+\t\tident->words[i] = ioread32(&dev->dev_cmd->data[i]);\n+\n+\tdev->max_qps =\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_CRYPTOQ]);\n+\tdev->max_sessions =\n+\t\trte_le_to_cpu_32(ident->max_nb_sessions);\n+\n+\tfeatures = rte_le_to_cpu_64(ident->features);\n+\tdev->features = RTE_CRYPTODEV_FF_HW_ACCELERATED;\n+\tif (features & IOCPT_HW_SYM)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO;\n+\tif (features & IOCPT_HW_ASYM)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO;\n+\tif (features & IOCPT_HW_CHAIN)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\n+\tif (features & IOCPT_HW_IP)\n+\t\tdev->features |= RTE_CRYPTODEV_FF_IN_PLACE_SGL;\n+\tif (features & IOCPT_HW_OOP) {\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;\n+\t\tdev->features |= RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT;\n+\t}\n+\n+\tIOCPT_PRINT(INFO, \"crypto.features %#jx\",\n+\t\trte_le_to_cpu_64(ident->features));\n+\tIOCPT_PRINT(INFO, \"crypto.features_active %#jx\",\n+\t\trte_le_to_cpu_64(cfg->features));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_ADMINQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_ADMINQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_NOTIFYQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_NOTIFYQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.queue_count[IOCPT_QTYPE_CRYPTOQ] %#x\",\n+\t\trte_le_to_cpu_32(cfg->queue_count[IOCPT_QTYPE_CRYPTOQ]));\n+\tIOCPT_PRINT(INFO, \"crypto.max_sessions %u\",\n+\t\trte_le_to_cpu_32(ident->max_nb_sessions));\n+\n+\tiocpt_queue_identify(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+iocpt_dev_init(struct iocpt_dev *dev, rte_iova_t info_pa)\n+{\n+\tuint32_t retries = 5;\n+\tint err;\n+\n+retry_lif_init:\n+\tiocpt_dev_cmd_lif_init(dev, info_pa);\n+\n+\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\tif (err == -EAGAIN && retries > 0) {\n+\t\tretries--;\n+\t\trte_delay_us_block(IONIC_DEVCMD_RETRY_WAIT_US);\n+\t\tgoto retry_lif_init;\n+\t}\n+\n+\treturn err;\n+}\n+\n+void\n+iocpt_dev_reset(struct iocpt_dev *dev)\n+{\n+\tiocpt_dev_cmd_lif_reset(dev);\n+\t(void)iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\n+\tiocpt_dev_cmd_reset(dev);\n+\t(void)iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+}\n+\n+int\n+iocpt_dev_adminq_init(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_queue *q = &dev->adminq->q;\n+\tstruct iocpt_q_init_comp comp;\n+\tuint32_t retries = 5;\n+\tint err;\n+\n+retry_adminq_init:\n+\tiocpt_dev_cmd_adminq_init(dev);\n+\n+\terr = iocpt_dev_cmd_wait_check(dev, IONIC_DEVCMD_TIMEOUT);\n+\tif (err == -EAGAIN && retries > 0) {\n+\t\tretries--;\n+\t\trte_delay_us_block(IONIC_DEVCMD_RETRY_WAIT_US);\n+\t\tgoto retry_adminq_init;\n+\t}\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tiocpt_dev_cmd_comp(dev, &comp);\n+\n+\tq->hw_type = comp.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(comp.hw_index);\n+\tq->db = iocpt_db_map(dev, q);\n+\n+\tIOCPT_PRINT(DEBUG, \"adminq->hw_type %d\", q->hw_type);\n+\tIOCPT_PRINT(DEBUG, \"adminq->hw_index %d\", q->hw_index);\n+\tIOCPT_PRINT(DEBUG, \"adminq->db %p\", q->db);\n+\n+\tdev->adminq->flags |= IOCPT_Q_F_INITED;\n+\n+\treturn 0;\n+}\n+\n+/* Admin_cmd interface */\n+\n+static bool\n+iocpt_adminq_service(struct iocpt_cq *cq, uint16_t cq_desc_index,\n+\t\tvoid *cb_arg __rte_unused)\n+{\n+\tstruct iocpt_admin_comp *cq_desc_base = cq->base;\n+\tstruct iocpt_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];\n+\tstruct iocpt_admin_q *adminq =\n+\t\tcontainer_of(cq, struct iocpt_admin_q, cq);\n+\tstruct iocpt_queue *q = &adminq->q;\n+\tstruct iocpt_admin_ctx *ctx;\n+\tuint16_t curr_q_tail_idx;\n+\tuint16_t stop_index;\n+\tvoid **info;\n+\n+\tif (!iocpt_color_match(cq_desc->color, cq->done_color))\n+\t\treturn false;\n+\n+\tstop_index = rte_le_to_cpu_16(cq_desc->comp_index);\n+\n+\tdo {\n+\t\tinfo = IOCPT_INFO_PTR(q, q->tail_idx);\n+\n+\t\tctx = info[0];\n+\t\tif (ctx != NULL) {\n+\t\t\tmemcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));\n+\t\t\tctx->pending_work = false; /* done */\n+\t\t}\n+\n+\t\tcurr_q_tail_idx = q->tail_idx;\n+\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n+\t} while (curr_q_tail_idx != stop_index);\n+\n+\treturn true;\n+}\n+\n+/** iocpt_adminq_post - Post an admin command.\n+ * @dev:\t\tHandle to dev.\n+ * @cmd_ctx:\t\tApi admin command context.\n+ *\n+ * Return: zero or negative error status.\n+ */\n+static int\n+iocpt_adminq_post(struct iocpt_dev *dev, struct iocpt_admin_ctx *ctx)\n+{\n+\tstruct iocpt_queue *q = &dev->adminq->q;\n+\tstruct iocpt_admin_cmd *q_desc_base = q->base;\n+\tstruct iocpt_admin_cmd *q_desc;\n+\tvoid **info;\n+\tint err = 0;\n+\n+\trte_spinlock_lock(&dev->adminq_lock);\n+\n+\tif (iocpt_q_space_avail(q) < 1) {\n+\t\terr = -ENOSPC;\n+\t\tgoto err_out;\n+\t}\n+\n+\tq_desc = &q_desc_base[q->head_idx];\n+\n+\tmemcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));\n+\n+\tinfo = IOCPT_INFO_PTR(q, q->head_idx);\n+\tinfo[0] = ctx;\n+\n+\tq->head_idx = Q_NEXT_TO_POST(q, 1);\n+\n+\t/* Ring doorbell */\n+\tiocpt_q_flush(q);\n+\n+err_out:\n+\trte_spinlock_unlock(&dev->adminq_lock);\n+\n+\treturn err;\n+}\n+\n+static int\n+iocpt_adminq_wait_for_completion(struct iocpt_dev *dev,\n+\t\tstruct iocpt_admin_ctx *ctx, unsigned long max_wait)\n+{\n+\tstruct iocpt_queue *q = &dev->adminq->q;\n+\tunsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US;\n+\tunsigned long step_deadline;\n+\tunsigned long max_wait_usec = max_wait * 1000000L;\n+\tunsigned long elapsed_usec = 0;\n+\tint budget = 8;\n+\tuint16_t idx;\n+\tvoid **info;\n+\n+\tstep_deadline = IONIC_ADMINQ_WDOG_MS * 1000 / step_usec;\n+\n+\twhile (ctx->pending_work && elapsed_usec < max_wait_usec) {\n+\t\t/*\n+\t\t * Locking here as adminq is served inline and could be\n+\t\t * called from multiple places\n+\t\t */\n+\t\trte_spinlock_lock(&dev->adminq_service_lock);\n+\n+\t\tiocpt_cq_service(&dev->adminq->cq, budget,\n+\t\t\tiocpt_adminq_service, NULL);\n+\n+\t\t/*\n+\t\t * Ring the doorbell again if work is pending after step_usec.\n+\t\t */\n+\t\tif (ctx->pending_work && !step_deadline) {\n+\t\t\tstep_deadline = IONIC_ADMINQ_WDOG_MS *\n+\t\t\t\t1000 / step_usec;\n+\n+\t\t\trte_spinlock_lock(&dev->adminq_lock);\n+\t\t\tidx = Q_NEXT_TO_POST(q, -1);\n+\t\t\tinfo = IOCPT_INFO_PTR(q, idx);\n+\t\t\tif (info[0] == ctx)\n+\t\t\t\tiocpt_q_flush(q);\n+\t\t\trte_spinlock_unlock(&dev->adminq_lock);\n+\t\t}\n+\n+\t\trte_spinlock_unlock(&dev->adminq_service_lock);\n+\n+\t\trte_delay_us_block(step_usec);\n+\t\telapsed_usec += step_usec;\n+\t\tstep_deadline--;\n+\t}\n+\n+\treturn (!ctx->pending_work);\n+}\n+\n+static int\n+iocpt_adminq_check_err(struct iocpt_admin_ctx *ctx, bool timeout)\n+{\n+\tconst char *name;\n+\tconst char *status;\n+\n+\tname = iocpt_opcode_to_str(ctx->cmd.cmd.opcode);\n+\n+\tif (ctx->comp.comp.status == IOCPT_RC_EAGAIN) {\n+\t\tIOCPT_PRINT(DEBUG, \"%s (%d) returned EAGAIN (%d)\",\n+\t\t\t name, ctx->cmd.cmd.opcode,\n+\t\t\t ctx->comp.comp.status);\n+\t\treturn -EAGAIN;\n+\t}\n+\tif (ctx->comp.comp.status != 0 || timeout) {\n+\t\tstatus = iocpt_error_to_str(ctx->comp.comp.status);\n+\t\tIOCPT_PRINT(ERR, \"%s (%d) failed: %s (%d)\",\n+\t\t\tname,\n+\t\t\tctx->cmd.cmd.opcode,\n+\t\t\ttimeout ? \"TIMEOUT\" : status,\n+\t\t\ttimeout ? -1 : ctx->comp.comp.status);\n+\t\treturn -EIO;\n+\t}\n+\n+\tif (ctx->cmd.cmd.opcode != IOCPT_CMD_SESS_CONTROL) {\n+\t\tIOCPT_PRINT(DEBUG, \"%s (%d) succeeded\",\n+\t\t\tname, ctx->cmd.cmd.opcode);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+iocpt_adminq_post_wait(struct iocpt_dev *dev, struct iocpt_admin_ctx *ctx)\n+{\n+\tbool done;\n+\tint err;\n+\n+\tif (ctx->cmd.cmd.opcode != IOCPT_CMD_SESS_CONTROL) {\n+\t\tIOCPT_PRINT(DEBUG, \"Sending %s (%d) via the admin queue\",\n+\t\t\tiocpt_opcode_to_str(ctx->cmd.cmd.opcode),\n+\t\t\tctx->cmd.cmd.opcode);\n+\t}\n+\n+\terr = iocpt_adminq_post(dev, ctx);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Failure posting %d to the admin queue (%d)\",\n+\t\t\tctx->cmd.cmd.opcode, err);\n+\t\treturn err;\n+\t}\n+\n+\tdone = iocpt_adminq_wait_for_completion(dev, ctx,\n+\t\tIONIC_DEVCMD_TIMEOUT);\n+\n+\treturn iocpt_adminq_check_err(ctx, !done /* timed out */);\n+}\ndiff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c\nnew file mode 100644\nindex 0000000000..7b26080bd1\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_main.c\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_malloc.h>\n+#include <rte_bitops.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+int iocpt_logtype;\n+\n+uint32_t\n+iocpt_cq_service(struct iocpt_cq *cq, uint32_t work_to_do,\n+\t\t iocpt_cq_cb cb, void *cb_arg)\n+{\n+\tuint32_t work_done = 0;\n+\n+\tif (work_to_do == 0)\n+\t\treturn 0;\n+\n+\twhile (cb(cq, cq->tail_idx, cb_arg)) {\n+\t\tcq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);\n+\t\tif (cq->tail_idx == 0)\n+\t\t\tcq->done_color = !cq->done_color;\n+\n+\t\tif (++work_done == work_to_do)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn work_done;\n+}\n+\n+struct ionic_doorbell *\n+iocpt_db_map(struct iocpt_dev *dev, struct iocpt_queue *q)\n+{\n+\treturn dev->db_pages + q->hw_type;\n+}\n+\n+RTE_LOG_REGISTER_DEFAULT(iocpt_logtype, NOTICE);\ndiff --git a/drivers/crypto/ionic/meson.build b/drivers/crypto/ionic/meson.build\nnew file mode 100644\nindex 0000000000..6eaef41196\n--- /dev/null\n+++ b/drivers/crypto/ionic/meson.build\n@@ -0,0 +1,12 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2021-2024 Advanced Micro Devices, Inc.\n+\n+deps += ['common_ionic']\n+\n+sources = files(\n+ 'ionic_crypto_cmds.c',\n+ 'ionic_crypto_main.c',\n+)\n+name = 'ionic_crypto'\n+\n+includes += include_directories('../../common/ionic')\n", "prefixes": [ "2/6" ] }