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{
    "id": 135490,
    "url": "https://patches.dpdk.org/api/patches/135490/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-16-ajit.khaparde@broadcom.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20231221180529.18687-16-ajit.khaparde@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20231221180529.18687-16-ajit.khaparde@broadcom.com",
    "date": "2023-12-21T18:05:26",
    "name": "[15/18] net/bnxt: add 400G get support for P7 devices",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "fdee07b53374263284c3f65672ab7d8bf745162f",
    "submitter": {
        "id": 501,
        "url": "https://patches.dpdk.org/api/people/501/?format=api",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-16-ajit.khaparde@broadcom.com/mbox/",
    "series": [
        {
            "id": 30650,
            "url": "https://patches.dpdk.org/api/series/30650/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30650",
            "date": "2023-12-21T18:05:11",
            "name": "bnxt patchset",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/30650/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/135490/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/135490/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>",
        "Subject": "[PATCH 15/18] net/bnxt: add 400G get support for P7 devices",
        "Date": "Thu, 21 Dec 2023 10:05:26 -0800",
        "Message-Id": "<20231221180529.18687-16-ajit.khaparde@broadcom.com>",
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    },
    "content": "From: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\n\nP7 devices report speeds over speeds2 hsi fields. Adding required\nsupport to capture the capability from phy_qcap and save the\nspeeds2 fields into driver priv structure.\nIn fixed mode update the link_speed from force_link_speeds2 field.\nUpdates to logging to provide more info regarding numbers of lanes\nand the link signal mode.\n\nSome code refactoring done for PHY auto detect and displaying\nXCVR information.\n\nSigned-off-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h                |  15 +\n drivers/net/bnxt/bnxt_ethdev.c         |  57 ++-\n drivers/net/bnxt/bnxt_hwrm.c           | 493 ++++++++++++++++++++++++-\n drivers/net/bnxt/bnxt_hwrm.h           |   1 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h |  10 +-\n 5 files changed, 568 insertions(+), 8 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex eb3142cf09..2d871933e9 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -327,6 +327,16 @@ struct bnxt_link_info {\n \tuint16_t\t\tsupport_pam4_auto_speeds;\n \tuint8_t\t\t\treq_signal_mode;\n \tuint8_t\t\t\tmodule_status;\n+\t/* P7 speeds2 fields */\n+\tbool                    support_speeds_v2;\n+\tuint16_t                supported_speeds2_force_mode;\n+\tuint16_t                supported_speeds2_auto_mode;\n+\tuint16_t                support_speeds2;\n+\tuint16_t                force_link_speeds2;\n+\tuint16_t                auto_link_speeds2;\n+\tuint16_t                cfg_auto_link_speeds2_mask;\n+\tuint8_t                 active_lanes;\n+\tuint8_t\t\t\toption_flags;\n };\n \n #define BNXT_COS_QUEUE_COUNT\t8\n@@ -1165,6 +1175,11 @@ extern int bnxt_logtype_driver;\n #define PMD_DRV_LOG(level, fmt, args...) \\\n \t  PMD_DRV_LOG_RAW(level, fmt, ## args)\n \n+#define BNXT_LINK_SPEEDS_V2_OPTIONS(f) \\\n+\t((f) & HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED)\n+#define BNXT_LINK_SPEEDS_V2_VF(bp) (BNXT_VF((bp)) && ((bp)->link_info->option_flags))\n+#define BNXT_LINK_SPEEDS_V2(bp) (((bp)->link_info) && (((bp)->link_info->support_speeds_v2) || \\\n+\t\t\t\t\t\t       BNXT_LINK_SPEEDS_V2_VF((bp))))\n extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;\n int32_t bnxt_ulp_port_init(struct bnxt *bp);\n void bnxt_ulp_port_deinit(struct bnxt *bp);\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 7aed6d3ab6..625e5f1f9a 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -697,7 +697,10 @@ static inline bool bnxt_force_link_config(struct bnxt *bp)\n \n static int bnxt_update_phy_setting(struct bnxt *bp)\n {\n+\tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n+\tstruct rte_eth_link *link = &bp->eth_dev->data->dev_link;\n \tstruct rte_eth_link new;\n+\tuint32_t curr_speed_bit;\n \tint rc;\n \n \trc = bnxt_get_hwrm_link_config(bp, &new);\n@@ -706,13 +709,17 @@ static int bnxt_update_phy_setting(struct bnxt *bp)\n \t\treturn rc;\n \t}\n \n+\t/* convert to speedbit flag */\n+\tcurr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, 1);\n+\n \t/*\n \t * Device is not obliged link down in certain scenarios, even\n \t * when forced. When FW does not allow any user other than BMC\n \t * to shutdown the port, bnxt_get_hwrm_link_config() call always\n \t * returns link up. Force phy update always in that case.\n \t */\n-\tif (!new.link_status || bnxt_force_link_config(bp)) {\n+\tif (!new.link_status || bnxt_force_link_config(bp) ||\n+\t    (BNXT_LINK_SPEEDS_V2(bp) && dev_conf->link_speeds != curr_speed_bit)) {\n \t\trc = bnxt_set_hwrm_link_config(bp, true);\n \t\tif (rc) {\n \t\t\tPMD_DRV_LOG(ERR, \"Failed to update PHY settings\\n\");\n@@ -933,6 +940,50 @@ static int bnxt_shutdown_nic(struct bnxt *bp)\n  * Device configuration and status function\n  */\n \n+static uint32_t bnxt_get_speed_capabilities_v2(struct bnxt *bp)\n+{\n+\tuint32_t link_speed = 0;\n+\tuint32_t speed_capa = 0;\n+\n+\tif (bp->link_info == NULL)\n+\t\treturn 0;\n+\n+\tlink_speed = bp->link_info->support_speeds2;\n+\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_1G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_10G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_25G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_40G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_50G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_50G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_200G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_400G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_100G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_200G;\n+\tif (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_400G;\n+\n+\tif (bp->link_info->auto_mode ==\n+\t    HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)\n+\t\tspeed_capa |= RTE_ETH_LINK_SPEED_FIXED;\n+\n+\treturn speed_capa;\n+}\n+\n uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)\n {\n \tuint32_t pam4_link_speed = 0;\n@@ -942,6 +993,10 @@ uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)\n \tif (bp->link_info == NULL)\n \t\treturn 0;\n \n+\t/* P7 uses speeds_v2 */\n+\tif (BNXT_LINK_SPEEDS_V2(bp))\n+\t\treturn bnxt_get_speed_capabilities_v2(bp);\n+\n \tlink_speed = bp->link_info->support_speeds;\n \n \t/* If PAM4 is configured, use PAM4 supported speed */\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 0165a534af..98cb130fb2 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -68,6 +68,282 @@ const char *bnxt_backing_store_types[] = {\n \t\"Invalid type\"\n };\n \n+const char *media_type[] = { \"Unknown\", \"Twisted Pair\",\n+\t\"Direct Attached Copper\", \"Fiber\"\n+};\n+\n+#define MAX_MEDIA_TYPE (sizeof(media_type) / sizeof(const char *))\n+\n+const char *link_status_str[] = { \"Down. No link or cable detected.\",\n+\t\"Down. No link, but a cable has been detected.\", \"Up.\",\n+};\n+\n+#define MAX_LINK_STR (sizeof(link_status_str) / sizeof(const char *))\n+\n+const char *fec_mode[] = {\n+\t\"No active FEC\",\n+\t\"FEC CLAUSE 74 (Fire Code).\",\n+\t\"FEC CLAUSE 91 RS(528,514).\",\n+\t\"FEC RS544_1XN\",\n+\t\"FEC RS(544,528)\",\n+\t\"FEC RS272_1XN\",\n+\t\"FEC RS(272,257)\"\n+};\n+\n+#define MAX_FEC_MODE (sizeof(fec_mode) / sizeof(const char *))\n+\n+const char *signal_mode[] = {\n+\t\"NRZ\", \"PAM4\", \"PAM4_112\"\n+};\n+\n+#define MAX_SIG_MODE (sizeof(signal_mode) / sizeof(const char *))\n+\n+/* multi-purpose multi-key table container.\n+ * Add a unique entry for a new PHY attribs as per HW CAS.\n+ * Query it using a helper functions.\n+ */\n+struct link_speeds2_tbl {\n+\tuint16_t force_val;\n+\tuint16_t auto_val;\n+\tuint32_t rte_speed;\n+\tuint32_t rte_speed_num;\n+\tuint16_t hwrm_speed;\n+\tuint16_t sig_mode;\n+\tconst char *desc;\n+} link_speeds2_tbl[] = {\n+\t{\n+\t\t10,\n+\t\t0,\n+\t\tRTE_ETH_LINK_SPEED_1G,\n+\t\tRTE_ETH_SPEED_NUM_1G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"1Gb NRZ\",\n+\t}, {\n+\t\t100,\n+\t\t1,\n+\t\tRTE_ETH_LINK_SPEED_10G,\n+\t\tRTE_ETH_SPEED_NUM_10G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"10Gb NRZ\",\n+\t}, {\n+\t\t250,\n+\t\t2,\n+\t\tRTE_ETH_LINK_SPEED_25G,\n+\t\tRTE_ETH_SPEED_NUM_25G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"25Gb NRZ\",\n+\t}, {\n+\t\t400,\n+\t\t3,\n+\t\tRTE_ETH_LINK_SPEED_40G,\n+\t\tRTE_ETH_SPEED_NUM_40G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"40Gb NRZ\",\n+\t}, {\n+\t\t500,\n+\t\t4,\n+\t\tRTE_ETH_LINK_SPEED_50G,\n+\t\tRTE_ETH_SPEED_NUM_50G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"50Gb NRZ\",\n+\t}, {\n+\t\t1000,\n+\t\t5,\n+\t\tRTE_ETH_LINK_SPEED_100G,\n+\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB,\n+\t\tBNXT_SIG_MODE_NRZ,\n+\t\t\"100Gb NRZ\",\n+\t}, {\n+\t\t501,\n+\t\t6,\n+\t\tRTE_ETH_LINK_SPEED_50G,\n+\t\tRTE_ETH_SPEED_NUM_50G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56,\n+\t\tBNXT_SIG_MODE_PAM4,\n+\t\t\"50Gb (PAM4-56: 50G per lane)\",\n+\t}, {\n+\t\t1001,\n+\t\t7,\n+\t\tRTE_ETH_LINK_SPEED_100G,\n+\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56,\n+\t\tBNXT_SIG_MODE_PAM4,\n+\t\t\"100Gb (PAM4-56: 50G per lane)\",\n+\t}, {\n+\t\t2001,\n+\t\t8,\n+\t\tRTE_ETH_LINK_SPEED_200G,\n+\t\tRTE_ETH_SPEED_NUM_200G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56,\n+\t\tBNXT_SIG_MODE_PAM4,\n+\t\t\"200Gb (PAM4-56: 50G per lane)\",\n+\t}, {\n+\t\t4001,\n+\t\t9,\n+\t\tRTE_ETH_LINK_SPEED_400G,\n+\t\tRTE_ETH_SPEED_NUM_400G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56,\n+\t\tBNXT_SIG_MODE_PAM4,\n+\t\t\"400Gb (PAM4-56: 50G per lane)\",\n+\t}, {\n+\t\t1002,\n+\t\t10,\n+\t\tRTE_ETH_LINK_SPEED_100G,\n+\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112,\n+\t\tBNXT_SIG_MODE_PAM4_112,\n+\t\t\"100Gb (PAM4-112: 100G per lane)\",\n+\t}, {\n+\t\t2002,\n+\t\t11,\n+\t\tRTE_ETH_LINK_SPEED_200G,\n+\t\tRTE_ETH_SPEED_NUM_200G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112,\n+\t\tBNXT_SIG_MODE_PAM4_112,\n+\t\t\"200Gb (PAM4-112: 100G per lane)\",\n+\t}, {\n+\t\t4002,\n+\t\t12,\n+\t\tRTE_ETH_LINK_SPEED_400G,\n+\t\tRTE_ETH_SPEED_NUM_400G,\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112,\n+\t\tBNXT_SIG_MODE_PAM4_112,\n+\t\t\"400Gb (PAM4-112: 100G per lane)\",\n+\t}, {\n+\t\t0,\n+\t\t13,\n+\t\tRTE_ETH_LINK_SPEED_AUTONEG, /* None matches, AN is default 0 */\n+\t\tRTE_ETH_SPEED_NUM_NONE,\t/* None matches, No speed */\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB, /* Placeholder for wrong HWRM */\n+\t\tBNXT_SIG_MODE_NRZ, /* default sig */\n+\t\t\"Unknown\",\n+\t},\n+};\n+\n+#define BNXT_SPEEDS2_TBL_SZ (sizeof(link_speeds2_tbl) / sizeof(*link_speeds2_tbl))\n+\n+/* In hwrm_phy_qcfg reports trained up speeds in link_speed(offset:0x8[31:16]) */\n+struct link_speeds_tbl {\n+\tuint16_t hwrm_speed;\n+\tuint32_t rte_speed_num;\n+\tconst char *desc;\n+} link_speeds_tbl[] = {\n+\t{\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB,\n+\t\tRTE_ETH_SPEED_NUM_100M, \"100 MB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB,\n+\t\tRTE_ETH_SPEED_NUM_1G, \"1 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB,\n+\t\tRTE_ETH_SPEED_NUM_2_5G, \"25 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB,\n+\t\tRTE_ETH_SPEED_NUM_10G, \"10 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB,\n+\t\tRTE_ETH_SPEED_NUM_20G, \"20 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB,\n+\t\tRTE_ETH_SPEED_NUM_40G, \"40 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB,\n+\t\tRTE_ETH_SPEED_NUM_50G, \"50 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB,\n+\t\tRTE_ETH_SPEED_NUM_100G, \"100 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB,\n+\t\tRTE_ETH_SPEED_NUM_200G, \"200 GB\",\n+\t}, {\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB,\n+\t\tRTE_ETH_SPEED_NUM_400G, \"400 GB\",\n+\t}, {\n+\t\t0, RTE_ETH_SPEED_NUM_NONE, \"None\",\n+\t},\n+};\n+\n+#define BNXT_SPEEDS_TBL_SZ (sizeof(link_speeds_tbl) / sizeof(*link_speeds_tbl))\n+\n+static const char *bnxt_get_xcvr_type(uint32_t xcvr_identifier_type_tx_lpi_timer)\n+{\n+\tuint32_t xcvr_type = HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK &\n+\t\txcvr_identifier_type_tx_lpi_timer;\n+\n+\t/* Addressing only known CMIS types */\n+\tswitch (xcvr_type) {\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP:\n+\t\treturn \"SFP\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP:\n+\t\treturn \"QSFP\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS:\n+\t\treturn \"QSFP+\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28:\n+\t\treturn \"QSFP28\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD:\n+\t\treturn \"QSFP112\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112:\n+\t\treturn \"QSFP-DD\";\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN:\n+\t\treturn \"Unknown\";\n+\tdefault:\n+\t\t/* All other/new CMIS variants belong here */\n+\t\treturn \"QSFP-xx new CMIS variant\";\n+\t}\n+}\n+\n+/* Utility function to lookup speeds2 table and\n+ * return a rte to hwrm speed matching row to the client\n+ */\n+static\n+struct link_speeds2_tbl *bnxt_get_rte_hwrm_speeds2_entry(uint32_t speed)\n+{\n+\tint i, max;\n+\n+\tmax = BNXT_SPEEDS2_TBL_SZ - 1;\n+\tspeed &= ~RTE_ETH_LINK_SPEED_FIXED;\n+\tfor (i = 0; i < max; i++) {\n+\t\tif (speed == link_speeds2_tbl[i].rte_speed)\n+\t\t\tbreak;\n+\t}\n+\treturn (struct link_speeds2_tbl *)&link_speeds2_tbl[i];\n+}\n+\n+/* Utility function to lookup speeds2 table and\n+ * return a hwrm to rte speed matching row to the client\n+ */\n+static struct link_speeds2_tbl *bnxt_get_hwrm_to_rte_speeds2_entry(uint16_t speed)\n+{\n+\tint i, max;\n+\n+\tmax = BNXT_SPEEDS2_TBL_SZ - 1;\n+\tfor (i = 0; i < max; i++) {\n+\t\tif (speed == link_speeds2_tbl[i].hwrm_speed)\n+\t\t\tbreak;\n+\t}\n+\treturn (struct link_speeds2_tbl *)&link_speeds2_tbl[i];\n+}\n+\n+/* Helper function to lookup auto link_speed table */\n+static struct link_speeds_tbl *bnxt_get_hwrm_to_rte_speeds_entry(uint16_t speed)\n+{\n+\tint i, max;\n+\n+\tmax = BNXT_SPEEDS_TBL_SZ - 1;\n+\n+\tfor (i = 0; i < max ; i++) {\n+\t\tif (speed == link_speeds_tbl[i].hwrm_speed)\n+\t\t\tbreak;\n+\t}\n+\treturn (struct link_speeds_tbl *)&link_speeds_tbl[i];\n+}\n+\n static int page_getenum(size_t size)\n {\n \tif (size <= 1 << 4)\n@@ -1564,15 +1840,64 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,\n \tlink_info->phy_ver[2] = resp->phy_bld;\n \tlink_info->link_signal_mode =\n \t\tresp->active_fec_signal_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK;\n+\tlink_info->option_flags = resp->option_flags;\n \tlink_info->force_pam4_link_speed =\n \t\t\trte_le_to_cpu_16(resp->force_pam4_link_speed);\n \tlink_info->support_pam4_speeds =\n \t\t\trte_le_to_cpu_16(resp->support_pam4_speeds);\n \tlink_info->auto_pam4_link_speed_mask =\n \t\t\trte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);\n+\t/* P7 uses speeds2 fields */\n+\tif (BNXT_LINK_SPEEDS_V2(bp) && BNXT_LINK_SPEEDS_V2_OPTIONS(link_info->option_flags)) {\n+\t\tlink_info->support_speeds2 = rte_le_to_cpu_16(resp->support_speeds2);\n+\t\tlink_info->force_link_speeds2 = rte_le_to_cpu_16(resp->force_link_speeds2);\n+\t\tlink_info->auto_link_speeds2 = rte_le_to_cpu_16(resp->auto_link_speeds2);\n+\t\tlink_info->active_lanes = resp->active_lanes;\n+\t\tif (!link_info->auto_mode)\n+\t\t\tlink_info->link_speed = link_info->force_link_speeds2;\n+\t}\n \tlink_info->module_status = resp->module_status;\n \tHWRM_UNLOCK();\n \n+\t/* Display the captured P7 phy details */\n+\tif (BNXT_LINK_SPEEDS_V2(bp)) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Phytype:%d, Media_type:%d, Status: %d, Link Signal:%d\\n\"\n+\t\t\t    \"Active Fec: %d Support_speeds2:%x, Force_link_speedsv2:%x\\n\"\n+\t\t\t    \"Auto_link_speedsv2:%x, Active_lanes:%d\\n\",\n+\t\t\t    link_info->phy_type,\n+\t\t\t    link_info->media_type,\n+\t\t\t    link_info->phy_link_status,\n+\t\t\t    link_info->link_signal_mode,\n+\t\t\t    (resp->active_fec_signal_mode &\n+\t\t\t\tHWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK) >> 4,\n+\t\t\t    link_info->support_speeds2, link_info->force_link_speeds2,\n+\t\t\t    link_info->auto_link_speeds2,\n+\t\t\t    link_info->active_lanes);\n+\n+\t\tconst char *desc;\n+\n+\t\tif (link_info->auto_mode)\n+\t\t\tdesc = ((struct link_speeds_tbl *)\n+\t\t\t\tbnxt_get_hwrm_to_rte_speeds_entry(link_info->link_speed))->desc;\n+\t\telse\n+\t\t\tdesc = ((struct link_speeds2_tbl *)\n+\t\t\t\tbnxt_get_hwrm_to_rte_speeds2_entry(link_info->link_speed))->desc;\n+\n+\t\tPMD_DRV_LOG(INFO, \"Link Speed: %s %s, Status: %s Signal-mode: %s\\n\"\n+\t\t\t    \"Media type: %s, Xcvr type: %s, Active FEC: %s Lanes: %d\\n\",\n+\t\t\t    desc,\n+\t\t\t    !(link_info->auto_mode) ? \"Forced\" : \"AutoNegotiated\",\n+\t\t\t    link_status_str[link_info->phy_link_status % MAX_LINK_STR],\n+\t\t\t    signal_mode[link_info->link_signal_mode % MAX_SIG_MODE],\n+\t\t\t    media_type[link_info->media_type % MAX_MEDIA_TYPE],\n+\t\t\t    bnxt_get_xcvr_type(rte_le_to_cpu_32\n+\t\t\t\t\t       (resp->xcvr_identifier_type_tx_lpi_timer)),\n+\t\t\t    fec_mode[((resp->active_fec_signal_mode &\n+\t\t\t\t       HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK) >> 4) %\n+\t\t\t    MAX_FEC_MODE], link_info->active_lanes);\n+\t\treturn rc;\n+\t}\n+\n \tPMD_DRV_LOG(DEBUG, \"Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\\n\",\n \t\t    link_info->link_speed, link_info->auto_mode,\n \t\t    link_info->auto_link_speed, link_info->auto_link_speed_mask,\n@@ -1608,6 +1933,15 @@ int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)\n \tif (resp->supported_pam4_speeds_auto_mode)\n \t\tlink_info->support_pam4_auto_speeds =\n \t\t\trte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);\n+\t/* P7 chips now report all speeds here */\n+\tif (resp->flags2 & HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED)\n+\t\tlink_info->support_speeds_v2 = true;\n+\tif (link_info->support_speeds_v2) {\n+\t\tlink_info->supported_speeds2_force_mode =\n+\t\t\trte_le_to_cpu_16(resp->supported_speeds2_force_mode);\n+\t\tlink_info->supported_speeds2_auto_mode =\n+\t\t\trte_le_to_cpu_16(resp->supported_speeds2_auto_mode);\n+\t}\n \n \tHWRM_UNLOCK();\n \n@@ -3265,7 +3599,14 @@ static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)\n \treturn !conf_link;\n }\n \n-static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,\n+static uint16_t bnxt_parse_eth_link_speed_v2(uint32_t conf_link_speed)\n+{\n+\t/* get bitmap value based on speed */\n+\treturn ((struct link_speeds2_tbl *)\n+\t\tbnxt_get_rte_hwrm_speeds2_entry(conf_link_speed))->force_val;\n+}\n+\n+static uint16_t bnxt_parse_eth_link_speed(struct bnxt *bp, uint32_t conf_link_speed,\n \t\t\t\t\t  struct bnxt_link_info *link_info)\n {\n \tuint16_t support_pam4_speeds = link_info->support_pam4_speeds;\n@@ -3275,6 +3616,10 @@ static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,\n \tif (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)\n \t\treturn RTE_ETH_LINK_SPEED_AUTONEG;\n \n+\t/* Handle P7 chips saperately. It got enhanced phy attribs to choose from */\n+\tif (BNXT_LINK_SPEEDS_V2(bp))\n+\t\treturn bnxt_parse_eth_link_speed_v2(conf_link_speed);\n+\n \tswitch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {\n \tcase RTE_ETH_LINK_SPEED_100M:\n \tcase RTE_ETH_LINK_SPEED_100M_HD:\n@@ -3346,6 +3691,9 @@ static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,\n \t\tRTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \\\n \t\tRTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \\\n \t\tRTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)\n+#define BNXT_SUPPORTED_SPEEDS2 ((BNXT_SUPPORTED_SPEEDS | RTE_ETH_LINK_SPEED_400G) & \\\n+\t\t~(RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \\\n+\t\t  RTE_ETH_LINK_SPEED_2_5G | RTE_ETH_LINK_SPEED_20G))\n \n static int bnxt_validate_link_speed(struct bnxt *bp)\n {\n@@ -3385,11 +3733,25 @@ static int bnxt_validate_link_speed(struct bnxt *bp)\n \treturn 0;\n }\n \n+static uint16_t\n+bnxt_parse_eth_link_speed_mask_v2(struct bnxt *bp, uint32_t link_speed)\n+{\n+\tuint16_t ret = 0;\n+\n+\tif (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)\n+\t\treturn bp->link_info->supported_speeds2_auto_mode;\n+\n+\treturn ret;\n+}\n+\n static uint16_t\n bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)\n {\n \tuint16_t ret = 0;\n \n+\tif (BNXT_LINK_SPEEDS_V2(bp))\n+\t\treturn bnxt_parse_eth_link_speed_mask_v2(bp, link_speed);\n+\n \tif (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {\n \t\tif (bp->link_info->support_speeds)\n \t\t\treturn bp->link_info->support_speeds;\n@@ -3421,10 +3783,21 @@ bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)\n \treturn ret;\n }\n \n-static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)\n+static uint32_t bnxt_parse_hw_link_speed_v2(uint16_t hw_link_speed)\n+{\n+\treturn ((struct link_speeds2_tbl *)\n+\t\tbnxt_get_hwrm_to_rte_speeds2_entry(hw_link_speed))->rte_speed_num;\n+}\n+\n+static uint32_t bnxt_parse_hw_link_speed(struct bnxt *bp, uint16_t hw_link_speed)\n {\n \tuint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;\n \n+\t/* query fixed speed2 table if not autoneg */\n+\tif (BNXT_LINK_SPEEDS_V2(bp) && !bp->link_info->auto_mode)\n+\t\treturn bnxt_parse_hw_link_speed_v2(hw_link_speed);\n+\n+\t/* for P7 and earlier nics link_speed carries AN'd speed */\n \tswitch (hw_link_speed) {\n \tcase HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:\n \t\teth_link_speed = RTE_ETH_SPEED_NUM_100M;\n@@ -3456,6 +3829,9 @@ static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)\n \tcase HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:\n \t\teth_link_speed = RTE_ETH_SPEED_NUM_200G;\n \t\tbreak;\n+\tcase HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB:\n+\t\teth_link_speed = RTE_ETH_SPEED_NUM_400G;\n+\t\tbreak;\n \tcase HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:\n \tdefault:\n \t\tPMD_DRV_LOG(ERR, \"HWRM link speed %d not defined\\n\",\n@@ -3502,8 +3878,7 @@ int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)\n \t}\n \n \tif (link_info->link_speed)\n-\t\tlink->link_speed =\n-\t\t\tbnxt_parse_hw_link_speed(link_info->link_speed);\n+\t\tlink->link_speed = bnxt_parse_hw_link_speed(bp, link_info->link_speed);\n \telse\n \t\tlink->link_speed = RTE_ETH_SPEED_NUM_NONE;\n \tlink->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);\n@@ -3515,6 +3890,111 @@ int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)\n \treturn rc;\n }\n \n+static int bnxt_hwrm_port_phy_cfg_v2(struct bnxt *bp, struct bnxt_link_info *conf)\n+{\n+\tstruct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tstruct hwrm_port_phy_cfg_input req = {0};\n+\tuint32_t enables = 0;\n+\tint rc = 0;\n+\n+\tHWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);\n+\n+\tif (!conf->link_up) {\n+\t\treq.flags =\n+\t\trte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);\n+\t\tPMD_DRV_LOG(ERR, \"Force Link Down\\n\");\n+\t\tgoto link_down;\n+\t}\n+\n+\t/* Setting Fixed Speed. But AutoNeg is ON, So disable it */\n+\tif (bp->link_info->auto_mode && conf->link_speed) {\n+\t\treq.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;\n+\t\tPMD_DRV_LOG(DEBUG, \"Disabling AutoNeg\\n\");\n+\t}\n+\treq.flags = rte_cpu_to_le_32(conf->phy_flags);\n+\tif (!conf->link_speed) {\n+\t\t/* No speeds specified. Enable AutoNeg - all speeds */\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK;\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;\n+\t\treq.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;\n+\t\treq.auto_link_speeds2_mask =\n+\t\t\trte_cpu_to_le_16(bp->link_info->supported_speeds2_auto_mode);\n+\t} else {\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2;\n+\t\treq.force_link_speeds2 = rte_cpu_to_le_16(conf->link_speed);\n+\t}\n+\n+\t/* Fill rest of the req message */\n+\treq.auto_duplex = conf->duplex;\n+\tif (req.auto_mode != HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK)\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;\n+\treq.auto_pause = conf->auto_pause;\n+\treq.force_pause = conf->force_pause;\n+\tif (req.auto_pause)\n+\t\treq.force_pause = 0;\n+\t/* Set force_pause if there is no auto or if there is a force */\n+\tif (req.auto_pause && !req.force_pause)\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;\n+\telse\n+\t\tenables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;\n+\treq.enables = rte_cpu_to_le_32(enables);\n+\n+link_down:\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n+\n+\tHWRM_CHECK_RESULT();\n+\tHWRM_UNLOCK();\n+\treturn rc;\n+}\n+\n+static int bnxt_set_hwrm_link_config_v2(struct bnxt *bp, bool link_up)\n+{\n+\tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n+\tstruct bnxt_link_info link_req;\n+\tuint16_t speed, autoneg;\n+\tint rc = 0;\n+\n+\tmemset(&link_req, 0, sizeof(link_req));\n+\tlink_req.link_up = link_up;\n+\tif (!link_up)\n+\t\tgoto port_phy_cfg;\n+\n+\tautoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);\n+\tspeed = bnxt_parse_eth_link_speed(bp, dev_conf->link_speeds,\n+\t\t\t\t\t  bp->link_info);\n+\tlink_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;\n+\tif (autoneg == 1) {\n+\t\tlink_req.phy_flags |=\n+\t\t\tHWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;\n+\t\tlink_req.cfg_auto_link_speeds2_mask =\n+\t\t\tbnxt_parse_eth_link_speed_mask(bp, dev_conf->link_speeds);\n+\t} else {\n+\t\tif (bp->link_info->phy_type ==\n+\t\t    HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||\n+\t\t    bp->link_info->phy_type ==\n+\t\t    HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||\n+\t\t    bp->link_info->media_type ==\n+\t\t    HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {\n+\t\t\tPMD_DRV_LOG(ERR, \"10GBase-T devices must autoneg\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tlink_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;\n+\t\t/* If user wants a particular speed try that first. */\n+\t\tlink_req.link_speed = speed;\n+\t}\n+\tlink_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);\n+\tlink_req.auto_pause = bp->link_info->auto_pause;\n+\tlink_req.force_pause = bp->link_info->force_pause;\n+\n+port_phy_cfg:\n+\trc = bnxt_hwrm_port_phy_cfg_v2(bp, &link_req);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(ERR, \"Set link config failed with rc %d\\n\", rc);\n+\n+\treturn rc;\n+}\n+\n int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)\n {\n \tint rc = 0;\n@@ -3529,6 +4009,9 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)\n \tif (rc)\n \t\tgoto error;\n \n+\tif (BNXT_LINK_SPEEDS_V2(bp))\n+\t\treturn bnxt_set_hwrm_link_config_v2(bp, link_up);\n+\n \tmemset(&link_req, 0, sizeof(link_req));\n \tlink_req.link_up = link_up;\n \tif (!link_up)\n@@ -3554,7 +4037,7 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)\n \t\tPMD_DRV_LOG(DEBUG, \"Disabling autoneg for 200G\\n\");\n \t}\n \n-\tspeed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,\n+\tspeed = bnxt_parse_eth_link_speed(bp, dev_conf->link_speeds,\n \t\t\t\t\t  bp->link_info);\n \tlink_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;\n \t/* Autoneg can be done only when the FW allows. */\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex 6116253787..179d5dc1f0 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -145,6 +145,7 @@ struct bnxt_pf_resource_info {\n \n #define BNXT_SIG_MODE_NRZ\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ\n #define BNXT_SIG_MODE_PAM4\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4\n+#define BNXT_SIG_MODE_PAM4_112\tHWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112\n \n #define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp)\t\t\\\n \t(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 65f3f0576b..b012a84d36 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -27273,11 +27273,17 @@ struct hwrm_port_phy_qcfg_output {\n \t/* QSFP+ */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \\\n \t\t(UINT32_C(0xd) << 24)\n-\t/* QSFP28 */\n+\t/* QSFP28/QSFP56 or later */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \\\n \t\t(UINT32_C(0x11) << 24)\n+\t/* QSFP-DD */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD \\\n+\t\t(UINT32_C(0x18) << 24)\n+\t/* QSFP112 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 \\\n+\t\t(UINT32_C(0x1e) << 24)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112\n \t/*\n \t * This value represents the current configuration of\n \t * Forward Error Correction (FEC) on the port.\n",
    "prefixes": [
        "15/18"
    ]
}