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{
    "id": 134900,
    "url": "https://patches.dpdk.org/api/patches/134900/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231207063514.2001192-2-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20231207063514.2001192-2-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20231207063514.2001192-2-wenzhuo.lu@intel.com",
    "date": "2023-12-07T06:35:13",
    "name": "[1/2] common/idpf: enable AVX2 for single queue Rx",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "dfc7dbe0c9c2abdf17509666186c74f3b99970ff",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231207063514.2001192-2-wenzhuo.lu@intel.com/mbox/",
    "series": [
        {
            "id": 30468,
            "url": "https://patches.dpdk.org/api/series/30468/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30468",
            "date": "2023-12-07T06:35:12",
            "name": "enable AVX2 for IDPF single queue",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/30468/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/134900/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/134900/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "from dpdk-wenzhuo-icelake.sh.intel.com ([10.67.111.210])\n by orsmga002.jf.intel.com with ESMTP; 06 Dec 2023 22:12:21 -0800"
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            "E=McAfee;i=\"6600,9927,10916\"; a=\"458507907\"",
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            "E=Sophos;i=\"6.04,256,1695711600\"; d=\"scan'208\";a=\"771599760\""
        ],
        "X-ExtLoop1": "1",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "Subject": "[PATCH 1/2] common/idpf: enable AVX2 for single queue Rx",
        "Date": "Thu,  7 Dec 2023 06:35:13 +0000",
        "Message-Id": "<20231207063514.2001192-2-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20231207063514.2001192-1-wenzhuo.lu@intel.com>",
        "References": "<20231207063514.2001192-1-wenzhuo.lu@intel.com>",
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        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "In case some CPUs don't support AVX512. Enable AVX2 for them to\nget better per-core performance.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/common/idpf/idpf_common_device.h    |   1 +\n drivers/common/idpf/idpf_common_rxtx.h      |   4 +\n drivers/common/idpf/idpf_common_rxtx_avx2.c | 609 ++++++++++++++++++++\n drivers/common/idpf/meson.build             |  16 +\n drivers/common/idpf/version.map             |   1 +\n drivers/net/idpf/idpf_rxtx.c                |  12 +\n 6 files changed, 643 insertions(+)\n create mode 100644 drivers/common/idpf/idpf_common_rxtx_avx2.c",
    "diff": "diff --git a/drivers/common/idpf/idpf_common_device.h b/drivers/common/idpf/idpf_common_device.h\nindex f767ea7cec..afe3d48798 100644\n--- a/drivers/common/idpf/idpf_common_device.h\n+++ b/drivers/common/idpf/idpf_common_device.h\n@@ -114,6 +114,7 @@ struct idpf_vport {\n \n \tbool rx_vec_allowed;\n \tbool tx_vec_allowed;\n+\tbool rx_use_avx2;\n \tbool rx_use_avx512;\n \tbool tx_use_avx512;\n \ndiff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h\nindex b49b1ed737..4d64063718 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.h\n+++ b/drivers/common/idpf/idpf_common_rxtx.h\n@@ -302,5 +302,9 @@ uint16_t idpf_dp_splitq_xmit_pkts_avx512(void *tx_queue, struct rte_mbuf **tx_pk\n __rte_internal\n uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t  uint16_t nb_pkts);\n+__rte_internal\n+uint16_t idpf_dp_singleq_recv_pkts_avx2(void *rx_queue,\n+\t\t\t\t\tstruct rte_mbuf **rx_pkts,\n+\t\t\t\t\tuint16_t nb_pkts);\n \n #endif /* _IDPF_COMMON_RXTX_H_ */\ndiff --git a/drivers/common/idpf/idpf_common_rxtx_avx2.c b/drivers/common/idpf/idpf_common_rxtx_avx2.c\nnew file mode 100644\nindex 0000000000..0403cf118f\n--- /dev/null\n+++ b/drivers/common/idpf/idpf_common_rxtx_avx2.c\n@@ -0,0 +1,609 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#include <rte_vect.h>\n+\n+#include \"idpf_common_rxtx.h\"\n+#include \"idpf_common_device.h\"\n+\n+#ifndef __INTEL_COMPILER\n+#pragma GCC diagnostic ignored \"-Wcast-qual\"\n+#endif\n+\n+static __rte_always_inline void\n+idpf_singleq_rx_rearm(struct idpf_rx_queue *rxq)\n+{\n+\tint i;\n+\tuint16_t rx_id;\n+\tvolatile union virtchnl2_rx_desc *rxdp = rxq->rx_ring;\n+\tstruct rte_mbuf **rxep = &rxq->sw_ring[rxq->rxrearm_start];\n+\n+\trxdp += rxq->rxrearm_start;\n+\n+\t/* Pull 'n' more MBUFs into the software ring */\n+\tif (rte_mempool_get_bulk(rxq->mp,\n+\t\t\t\t (void *)rxep,\n+\t\t\t\t IDPF_RXQ_REARM_THRESH) < 0) {\n+\t\tif (rxq->rxrearm_nb + IDPF_RXQ_REARM_THRESH >=\n+\t\t    rxq->nb_rx_desc) {\n+\t\t\t__m128i dma_addr0;\n+\n+\t\t\tdma_addr0 = _mm_setzero_si128();\n+\t\t\tfor (i = 0; i < IDPF_VPMD_DESCS_PER_LOOP; i++) {\n+\t\t\t\trxep[i] = &rxq->fake_mbuf;\n+\t\t\t\t_mm_store_si128((__m128i *)&rxdp[i].read,\n+\t\t\t\t\t\tdma_addr0);\n+\t\t\t}\n+\t\t}\n+\t\t__atomic_fetch_add(&rxq->rx_stats.mbuf_alloc_failed,\n+\t\t\t\t   IDPF_RXQ_REARM_THRESH, __ATOMIC_RELAXED);\n+\n+\t\treturn;\n+\t}\n+\n+\tstruct rte_mbuf *mb0, *mb1;\n+\t__m128i dma_addr0, dma_addr1;\n+\t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n+\t\t\tRTE_PKTMBUF_HEADROOM);\n+\t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n+\tfor (i = 0; i < IDPF_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n+\t\t__m128i vaddr0, vaddr1;\n+\n+\t\tmb0 = rxep[0];\n+\t\tmb1 = rxep[1];\n+\n+\t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\n+\t\t/* convert pa to dma_addr hdr/data */\n+\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n+\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n+\n+\t\t/* add headroom to pa values */\n+\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\n+\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\n+\n+\t\t/* flush desc with pa dma_addr */\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\n+\t}\n+\n+\trxq->rxrearm_start += IDPF_RXQ_REARM_THRESH;\n+\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n+\t\trxq->rxrearm_start = 0;\n+\n+\trxq->rxrearm_nb -= IDPF_RXQ_REARM_THRESH;\n+\n+\trx_id = (uint16_t)((rxq->rxrearm_start == 0) ?\n+\t\t\t     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n+\n+\t/* Update the tail pointer on the NIC */\n+\tIDPF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n+}\n+\n+static inline __m256i\n+idpf_flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)\n+{\n+#define FDID_MIS_MAGIC 0xFFFFFFFF\n+\tRTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR != (1 << 2));\n+\tRTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));\n+\tconst __m256i pkt_fdir_bit = _mm256_set1_epi32(RTE_MBUF_F_RX_FDIR |\n+\t\t\tRTE_MBUF_F_RX_FDIR_ID);\n+\t/* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */\n+\tconst __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);\n+\t__m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,\n+\t\t\tfdir_mis_mask);\n+\t/* this XOR op results to bit-reverse the fdir_mask */\n+\tfdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);\n+\tconst __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);\n+\n+\treturn fdir_flags;\n+}\n+\n+static inline uint16_t\n+_idpf_singleq_recv_raw_pkts_vec_avx2(struct idpf_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n+\t\t\t\t     uint16_t nb_pkts, uint8_t *split_packet)\n+{\n+#define IDPF_DESCS_PER_LOOP_AVX 8\n+\n+\tconst uint32_t *ptype_tbl = rxq->adapter->ptype_tbl;\n+\tconst __m256i mbuf_init = _mm256_set_epi64x(0, 0,\n+\t\t\t0, rxq->mbuf_initializer);\n+\tstruct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];\n+\tvolatile union virtchnl2_rx_desc *rxdp = rxq->rx_ring;\n+\tconst int avx_aligned = ((rxq->rx_tail & 1) == 0);\n+\n+\trxdp += rxq->rx_tail;\n+\n+\trte_prefetch0(rxdp);\n+\n+\t/* nb_pkts has to be floor-aligned to IDPF_DESCS_PER_LOOP_AVX */\n+\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IDPF_DESCS_PER_LOOP_AVX);\n+\n+\t/* See if we need to rearm the RX queue - gives the prefetch a bit\n+\t * of time to act\n+\t */\n+\tif (rxq->rxrearm_nb > IDPF_RXQ_REARM_THRESH)\n+\t\tidpf_singleq_rx_rearm(rxq);\n+\n+\t/* Before we start moving massive data around, check to see if\n+\t * there is actually a packet available\n+\t */\n+\tif (!(rxdp->flex_nic_wb.status_error0 &\n+\t\t\trte_cpu_to_le_32(1 << VIRTCHNL2_RX_FLEX_DESC_STATUS0_DD_S)))\n+\t\treturn 0;\n+\n+\t/* 8 packets DD mask, LSB in each 32-bit value */\n+\tconst __m256i dd_check = _mm256_set1_epi32(1);\n+\n+\t/* 8 packets EOP mask, second-LSB in each 32-bit value */\n+\tconst __m256i eop_check = _mm256_slli_epi32(dd_check,\n+\t\t\tVIRTCHNL2_RX_FLEX_DESC_STATUS0_EOF_S);\n+\n+\t/* mask to shuffle from desc. to mbuf (2 descriptors)*/\n+\tconst __m256i shuf_msk =\n+\t\t_mm256_set_epi8\n+\t\t\t(/* first descriptor */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n+\t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF,\t/*pkt_type set as unknown */\n+\t\t\t /* second descriptor */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n+\t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n+\t\t\t 5, 4,\t\t/* octet 4~5, 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF\t/*pkt_type set as unknown */\n+\t\t\t);\n+\t/**\n+\t * compile-time check the above crc and shuffle layout is correct.\n+\t * NOTE: the first field (lowest address) is given last in set_epi\n+\t * calls above.\n+\t */\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n+\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n+\n+\t/* Status/Error flag masks */\n+\t/**\n+\t * mask everything except Checksum Reports, RSS indication\n+\t * and VLAN indication.\n+\t * bit6:4 for IP/L4 checksum errors.\n+\t * bit12 is for RSS indication.\n+\t * bit13 is for VLAN indication.\n+\t */\n+\tconst __m256i flags_mask =\n+\t\t _mm256_set1_epi32((0xF << 4) | (1 << 12) | (1 << 13));\n+\t/**\n+\t * data to be shuffled by the result of the flags mask shifted by 4\n+\t * bits.  This gives use the l3_l4 flags.\n+\t */\n+\tconst __m256i l3_l4_flags_shuf =\n+\t\t_mm256_set_epi8((RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 |\n+\t\t RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |\n+\t\t  RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD  |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD  |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t/**\n+\t\t * second 128-bits\n+\t\t * shift right 20 bits to use the low two bits to indicate\n+\t\t * outer checksum status\n+\t\t * shift right 1 bit to make sure it not exceed 255\n+\t\t */\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD  |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD  |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_BAD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,\n+\t\t(RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD >> 20 | RTE_MBUF_F_RX_L4_CKSUM_GOOD |\n+\t\t RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1);\n+\tconst __m256i cksum_mask =\n+\t\t _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_MASK |\n+\t\t\t\t   RTE_MBUF_F_RX_L4_CKSUM_MASK |\n+\t\t\t\t   RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |\n+\t\t\t\t   RTE_MBUF_F_RX_OUTER_L4_CKSUM_MASK);\n+\t/**\n+\t * data to be shuffled by result of flag mask, shifted down 12.\n+\t * If RSS(bit12)/VLAN(bit13) are set,\n+\t * shuffle moves appropriate flags in place.\n+\t */\n+\tconst __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tRTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,\n+\t\t\tRTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,\n+\t\t\tRTE_MBUF_F_RX_RSS_HASH, 0,\n+\t\t\t/* end up 128-bits */\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tRTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,\n+\t\t\tRTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,\n+\t\t\tRTE_MBUF_F_RX_RSS_HASH, 0);\n+\n+\tRTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */\n+\n+\tuint16_t i, received;\n+\n+\tfor (i = 0, received = 0; i < nb_pkts;\n+\t     i += IDPF_DESCS_PER_LOOP_AVX,\n+\t     rxdp += IDPF_DESCS_PER_LOOP_AVX) {\n+\t\t/* step 1, copy over 8 mbuf pointers to rx_pkts array */\n+\t\t_mm256_storeu_si256((void *)&rx_pkts[i],\n+\t\t\t\t    _mm256_loadu_si256((void *)&sw_ring[i]));\n+#ifdef RTE_ARCH_X86_64\n+\t\t_mm256_storeu_si256\n+\t\t\t((void *)&rx_pkts[i + 4],\n+\t\t\t _mm256_loadu_si256((void *)&sw_ring[i + 4]));\n+#endif\n+\n+\t\t__m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;\n+\n+\t\tconst __m128i raw_desc7 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 7));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc6 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 6));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc5 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 5));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc4 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 4));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc3 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 3));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc2 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 2));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc1 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 1));\n+\t\trte_compiler_barrier();\n+\t\tconst __m128i raw_desc0 =\n+\t\t\t_mm_load_si128((void *)(rxdp + 0));\n+\n+\t\traw_desc6_7 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc6),\n+\t\t\t\t raw_desc7, 1);\n+\t\traw_desc4_5 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc4),\n+\t\t\t\t raw_desc5, 1);\n+\t\traw_desc2_3 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc2),\n+\t\t\t\t raw_desc3, 1);\n+\t\traw_desc0_1 =\n+\t\t\t_mm256_inserti128_si256\n+\t\t\t\t(_mm256_castsi128_si256(raw_desc0),\n+\t\t\t\t raw_desc1, 1);\n+\n+\t\tif (split_packet) {\n+\t\t\tint j;\n+\n+\t\t\tfor (j = 0; j < IDPF_DESCS_PER_LOOP_AVX; j++)\n+\t\t\t\trte_mbuf_prefetch_part2(rx_pkts[i + j]);\n+\t\t}\n+\n+\t\t/**\n+\t\t * convert descriptors 4-7 into mbufs, re-arrange fields.\n+\t\t * Then write into the mbuf.\n+\t\t */\n+\t\t__m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);\n+\t\t__m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);\n+\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m256i ptype_mask =\n+\t\t\t_mm256_set1_epi16(VIRTCHNL2_RX_FLEX_DESC_PTYPE_M);\n+\t\tconst __m256i ptypes6_7 =\n+\t\t\t_mm256_and_si256(raw_desc6_7, ptype_mask);\n+\t\tconst __m256i ptypes4_5 =\n+\t\t\t_mm256_and_si256(raw_desc4_5, ptype_mask);\n+\t\tconst uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);\n+\t\tconst uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);\n+\t\tconst uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);\n+\t\tconst uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);\n+\n+\t\tmb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype7], 4);\n+\t\tmb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype6], 0);\n+\t\tmb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype5], 4);\n+\t\tmb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype4], 0);\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,\n+\t\t\t\traw_desc4_5);\n+\n+\t\t/**\n+\t\t * convert descriptors 0-3 into mbufs, re-arrange fields.\n+\t\t * Then write into the mbuf.\n+\t\t */\n+\t\t__m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);\n+\t\t__m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);\n+\n+\t\t/**\n+\t\t * to get packet types, ptype is located in bit16-25\n+\t\t * of each 128bits\n+\t\t */\n+\t\tconst __m256i ptypes2_3 =\n+\t\t\t_mm256_and_si256(raw_desc2_3, ptype_mask);\n+\t\tconst __m256i ptypes0_1 =\n+\t\t\t_mm256_and_si256(raw_desc0_1, ptype_mask);\n+\t\tconst uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);\n+\t\tconst uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);\n+\t\tconst uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);\n+\t\tconst uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);\n+\n+\t\tmb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype3], 4);\n+\t\tmb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype2], 0);\n+\t\tmb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype1], 4);\n+\t\tmb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype0], 0);\n+\t\t/* merge the status bits into one register */\n+\t\tconst __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,\n+\t\t\t\t\t\t\t\traw_desc0_1);\n+\n+\t\t/**\n+\t\t * take the two sets of status bits and merge to one\n+\t\t * After merge, the packets status flags are in the\n+\t\t * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]\n+\t\t */\n+\t\t__m256i status0_7 = _mm256_unpacklo_epi64(status4_7,\n+\t\t\t\t\t\t\t  status0_3);\n+\n+\t\t/* now do flag manipulation */\n+\n+\t\t/* get only flag/error bits we want */\n+\t\tconst __m256i flag_bits =\n+\t\t\t_mm256_and_si256(status0_7, flags_mask);\n+\t\t/**\n+\t\t * l3_l4_error flags, shuffle, then shift to correct adjustment\n+\t\t * of flags in flags_shuf, and finally mask out extra bits\n+\t\t */\n+\t\t__m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,\n+\t\t\t\t_mm256_srli_epi32(flag_bits, 4));\n+\t\tl3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);\n+\n+\t\t__m256i l4_outer_mask = _mm256_set1_epi32(0x6);\n+\t\t__m256i l4_outer_flags =\n+\t\t\t\t_mm256_and_si256(l3_l4_flags, l4_outer_mask);\n+\t\tl4_outer_flags = _mm256_slli_epi32(l4_outer_flags, 20);\n+\n+\t\t__m256i l3_l4_mask = _mm256_set1_epi32(~0x6);\n+\t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, l3_l4_mask);\n+\t\tl3_l4_flags = _mm256_or_si256(l3_l4_flags, l4_outer_flags);\n+\t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);\n+\t\t/* set rss and vlan flags */\n+\t\tconst __m256i rss_vlan_flag_bits =\n+\t\t\t_mm256_srli_epi32(flag_bits, 12);\n+\t\tconst __m256i rss_vlan_flags =\n+\t\t\t_mm256_shuffle_epi8(rss_vlan_flags_shuf,\n+\t\t\t\t\t    rss_vlan_flag_bits);\n+\n+\t\t/* merge flags */\n+\t\t__m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t\t\trss_vlan_flags);\n+\n+\t\t/**\n+\t\t * At this point, we have the 8 sets of flags in the low 16-bits\n+\t\t * of each 32-bit value in vlan0.\n+\t\t * We want to extract these, and merge them with the mbuf init\n+\t\t * data so we can do a single write to the mbuf to set the flags\n+\t\t * and all the other initialization fields. Extracting the\n+\t\t * appropriate flags means that we have to do a shift and blend\n+\t\t * for each mbuf before we do the write. However, we can also\n+\t\t * add in the previously computed rx_descriptor fields to\n+\t\t * make a single 256-bit write per mbuf\n+\t\t */\n+\t\t/* check the structure matches expectations */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n+\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n+\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n+\t\t\t\t\t\t    rearm_data),\n+\t\t\t\t\t   16));\n+\t\t/* build up data and do writes */\n+\t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n+\t\t\trearm6, rearm7;\n+\t\trearm6 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_slli_si256(mbuf_flags, 8),\n+\t\t\t\t\t    0x04);\n+\t\trearm4 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_slli_si256(mbuf_flags, 4),\n+\t\t\t\t\t    0x04);\n+\t\trearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);\n+\t\trearm0 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_srli_si256(mbuf_flags, 4),\n+\t\t\t\t\t    0x04);\n+\t\t/* permute to add in the rx_descriptor e.g. rss fields */\n+\t\trearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);\n+\t\trearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);\n+\t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n+\t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n+\t\t/* write to mbuf */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t\t\t    rearm6);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t\t\t    rearm4);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t\t\t    rearm2);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t\t\t    rearm0);\n+\n+\t\t/* repeat for the odd mbufs */\n+\t\tconst __m256i odd_flags =\n+\t\t\t_mm256_castsi128_si256\n+\t\t\t\t(_mm256_extracti128_si256(mbuf_flags, 1));\n+\t\trearm7 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_slli_si256(odd_flags, 8),\n+\t\t\t\t\t    0x04);\n+\t\trearm5 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_slli_si256(odd_flags, 4),\n+\t\t\t\t\t    0x04);\n+\t\trearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);\n+\t\trearm1 = _mm256_blend_epi32(mbuf_init,\n+\t\t\t\t\t    _mm256_srli_si256(odd_flags, 4),\n+\t\t\t\t\t    0x04);\n+\t\t/* since odd mbufs are already in hi 128-bits use blend */\n+\t\trearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);\n+\t\trearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);\n+\t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n+\t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n+\t\t/* again write to mbufs */\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t\t\t    rearm7);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t\t\t    rearm5);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t\t\t    rearm3);\n+\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t\t\t    rearm1);\n+\n+\t\t/* extract and record EOP bit */\n+\t\tif (split_packet) {\n+\t\t\tconst __m128i eop_mask =\n+\t\t\t\t_mm_set1_epi16(1 << VIRTCHNL2_RX_FLEX_DESC_STATUS0_EOF_S);\n+\t\t\tconst __m256i eop_bits256 = _mm256_and_si256(status0_7,\n+\t\t\t\t\t\t\t\t     eop_check);\n+\t\t\t/* pack status bits into a single 128-bit register */\n+\t\t\tconst __m128i eop_bits =\n+\t\t\t\t_mm_packus_epi32\n+\t\t\t\t\t(_mm256_castsi256_si128(eop_bits256),\n+\t\t\t\t\t _mm256_extractf128_si256(eop_bits256,\n+\t\t\t\t\t\t\t\t  1));\n+\t\t\t/**\n+\t\t\t * flip bits, and mask out the EOP bit, which is now\n+\t\t\t * a split-packet bit i.e. !EOP, rather than EOP one.\n+\t\t\t */\n+\t\t\t__m128i split_bits = _mm_andnot_si128(eop_bits,\n+\t\t\t\t\teop_mask);\n+\t\t\t/**\n+\t\t\t * eop bits are out of order, so we need to shuffle them\n+\t\t\t * back into order again. In doing so, only use low 8\n+\t\t\t * bits, which acts like another pack instruction\n+\t\t\t * The original order is (hi->lo): 1,3,5,7,0,2,4,6\n+\t\t\t * [Since we use epi8, the 16-bit positions are\n+\t\t\t * multiplied by 2 in the eop_shuffle value.]\n+\t\t\t */\n+\t\t\t__m128i eop_shuffle =\n+\t\t\t\t_mm_set_epi8(/* zero hi 64b */\n+\t\t\t\t\t     0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t     0xFF, 0xFF, 0xFF, 0xFF,\n+\t\t\t\t\t     /* move values to lo 64b */\n+\t\t\t\t\t     8, 0, 10, 2,\n+\t\t\t\t\t     12, 4, 14, 6);\n+\t\t\tsplit_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);\n+\t\t\t*(uint64_t *)split_packet =\n+\t\t\t\t_mm_cvtsi128_si64(split_bits);\n+\t\t\tsplit_packet += IDPF_DESCS_PER_LOOP_AVX;\n+\t\t}\n+\n+\t\t/* perform dd_check */\n+\t\tstatus0_7 = _mm256_and_si256(status0_7, dd_check);\n+\t\tstatus0_7 = _mm256_packs_epi32(status0_7,\n+\t\t\t\t\t       _mm256_setzero_si256());\n+\n+\t\tuint64_t burst = __builtin_popcountll\n+\t\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t\t(_mm256_extracti128_si256\n+\t\t\t\t\t\t\t(status0_7, 1)));\n+\t\tburst += __builtin_popcountll\n+\t\t\t\t(_mm_cvtsi128_si64\n+\t\t\t\t\t(_mm256_castsi256_si128(status0_7)));\n+\t\treceived += burst;\n+\t\tif (burst != IDPF_DESCS_PER_LOOP_AVX)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* update tail pointers */\n+\trxq->rx_tail += received;\n+\trxq->rx_tail &= (rxq->nb_rx_desc - 1);\n+\tif ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */\n+\t\trxq->rx_tail--;\n+\t\treceived--;\n+\t}\n+\trxq->rxrearm_nb += received;\n+\treturn received;\n+}\n+\n+/**\n+ * Notice:\n+ * - nb_pkts < IDPF_DESCS_PER_LOOP, just return no packet\n+ */\n+uint16_t\n+idpf_dp_singleq_recv_pkts_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t       uint16_t nb_pkts)\n+{\n+\treturn _idpf_singleq_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);\n+}\ndiff --git a/drivers/common/idpf/meson.build b/drivers/common/idpf/meson.build\nindex 80c8906f80..6ab1c8175d 100644\n--- a/drivers/common/idpf/meson.build\n+++ b/drivers/common/idpf/meson.build\n@@ -16,6 +16,22 @@ sources = files(\n )\n \n if arch_subdir == 'x86'\n+    # compile AVX2 version if either:\n+    # a. we have AVX supported in minimum instruction set baseline\n+    # b. it's not minimum instruction set, but supported by compiler\n+    if cc.get_define('__AVX2__', args: machine_args) != ''\n+        cflags += ['-DCC_AVX2_SUPPORT']\n+        sources += files('idpf_common_rxtx_avx2.c')\n+    elif cc.has_argument('-mavx2')\n+        cflags += ['-DCC_AVX2_SUPPORT']\n+        idpf_avx2_lib = static_library('idpf_avx2_lib',\n+                'idpf_common_rxtx_avx2.c',\n+                dependencies: [static_rte_ethdev, static_rte_kvargs, static_rte_hash],\n+                include_directories: includes,\n+                c_args: [cflags, '-mavx2'])\n+        objs += idpf_avx2_lib.extract_objects('idpf_common_rxtx_avx2.c')\n+    endif\n+\n     idpf_avx512_cpu_support = (\n         cc.get_define('__AVX512F__', args: machine_args) != '' and\n         cc.get_define('__AVX512BW__', args: machine_args) != '' and\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex 0729f6b912..4510aae6b3 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -14,6 +14,7 @@ INTERNAL {\n \tidpf_dp_splitq_recv_pkts_avx512;\n \tidpf_dp_splitq_xmit_pkts;\n \tidpf_dp_splitq_xmit_pkts_avx512;\n+\tidpf_dp_singleq_recv_pkts_avx2;\n \n \tidpf_qc_rx_thresh_check;\n \tidpf_qc_rx_queue_release;\ndiff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c\nindex 64f2235580..b155c9ccd1 100644\n--- a/drivers/net/idpf/idpf_rxtx.c\n+++ b/drivers/net/idpf/idpf_rxtx.c\n@@ -772,6 +772,11 @@ idpf_set_rx_function(struct rte_eth_dev *dev)\n \t    rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n \t\tvport->rx_vec_allowed = true;\n \n+\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n+\t\t    rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)\n+\t\t\tvport->rx_use_avx2 = true;\n+\n \t\tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)\n #ifdef CC_AVX512_SUPPORT\n \t\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n@@ -823,6 +828,13 @@ idpf_set_rx_function(struct rte_eth_dev *dev)\n \t\t\t\treturn;\n \t\t\t}\n #endif /* CC_AVX512_SUPPORT */\n+\t\t\tif (vport->rx_use_avx2) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t    \"Using Single AVX2 Vector Rx (port %d).\",\n+\t\t\t\t\t    dev->data->port_id);\n+\t\t\t\tdev->rx_pkt_burst = idpf_dp_singleq_recv_pkts_avx2;\n+\t\t\t\treturn;\n+\t\t\t}\n \t\t}\n \n \t\tif (dev->data->scattered_rx) {\n",
    "prefixes": [
        "1/2"
    ]
}