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GET /api/patches/1348/?format=api
{ "id": 1348, "url": "https://patches.dpdk.org/api/patches/1348/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416399968-348-3-git-send-email-sergio.gonzalez.monroy@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416399968-348-3-git-send-email-sergio.gonzalez.monroy@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416399968-348-3-git-send-email-sergio.gonzalez.monroy@intel.com", "date": "2014-11-19T12:26:07", "name": "[dpdk-dev,2/3] Add RTE_ prefix to CACHE_LINE_MASK macro", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "10ec6484785b5c4e50b368a24cecccce04498a6d", "submitter": { "id": 73, "url": "https://patches.dpdk.org/api/people/73/?format=api", "name": "Sergio Gonzalez Monroy", "email": "sergio.gonzalez.monroy@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416399968-348-3-git-send-email-sergio.gonzalez.monroy@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1348/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1348/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id AA4B37F7D;\n\tWed, 19 Nov 2014 13:15:59 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 25BAD7F00\n\tfor <dev@dpdk.org>; Wed, 19 Nov 2014 13:15:48 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP; 19 Nov 2014 04:23:59 -0800", "from irvmail001.ir.intel.com ([163.33.26.43])\n\tby orsmga002.jf.intel.com with ESMTP; 19 Nov 2014 04:26:09 -0800", "from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com\n\t[10.237.217.46])\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n\tsAJCQ8TS008251 for <dev@dpdk.org>; Wed, 19 Nov 2014 12:26:09 GMT", "from sivswdev02.ir.intel.com (localhost [127.0.0.1])\n\tby sivswdev02.ir.intel.com with ESMTP id sAJCQ8Ux000400\n\tfor <dev@dpdk.org>; Wed, 19 Nov 2014 12:26:08 GMT", "(from smonroy@localhost)\n\tby sivswdev02.ir.intel.com with id sAJCQ8n2000396\n\tfor dev@dpdk.org; Wed, 19 Nov 2014 12:26:08 GMT" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.07,416,1413270000\"; d=\"scan'208\";a=\"639653699\"", "From": "Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>", "To": "dev@dpdk.org", "Date": "Wed, 19 Nov 2014 12:26:07 +0000", "Message-Id": "<1416399968-348-3-git-send-email-sergio.gonzalez.monroy@intel.com>", "X-Mailer": "git-send-email 1.8.5.4", "In-Reply-To": "<1416399968-348-1-git-send-email-sergio.gonzalez.monroy@intel.com>", "References": "<1416399968-348-1-git-send-email-sergio.gonzalez.monroy@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/3] Add RTE_ prefix to CACHE_LINE_MASK macro", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding RTE_ for consistency with other renamed macros and to avoid\npotential conflicts.\n\nSigned-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>\n---\n app/test/test_memzone.c | 32 +++++++++++++++---------------\n lib/librte_acl/rte_acl_osdep_alone.h | 2 +-\n lib/librte_distributor/rte_distributor.c | 2 +-\n lib/librte_eal/common/eal_common_memzone.c | 14 ++++++-------\n lib/librte_eal/common/include/rte_memory.h | 2 +-\n lib/librte_mempool/rte_mempool.c | 18 ++++++++---------\n lib/librte_ring/rte_ring.c | 10 +++++-----\n lib/librte_sched/rte_bitmap.h | 2 +-\n 8 files changed, 41 insertions(+), 41 deletions(-)", "diff": "diff --git a/app/test/test_memzone.c b/app/test/test_memzone.c\nindex b665fce..eeaac1f 100644\n--- a/app/test/test_memzone.c\n+++ b/app/test/test_memzone.c\n@@ -283,7 +283,7 @@ test_memzone_reserve_max(void)\n \t\t/* align everything */\n \t\tlast_addr = RTE_PTR_ALIGN_CEIL(ms[memseg_idx].addr, RTE_CACHE_LINE_SIZE);\n \t\tlen = ms[memseg_idx].len - RTE_PTR_DIFF(last_addr, ms[memseg_idx].addr);\n-\t\tlen &= ~((size_t) CACHE_LINE_MASK);\n+\t\tlen &= ~((size_t) RTE_CACHE_LINE_MASK);\n \n \t\t/* cycle through all memzones */\n \t\tfor (memzone_idx = 0; memzone_idx < RTE_MAX_MEMZONE; memzone_idx++) {\n@@ -376,7 +376,7 @@ test_memzone_reserve_max_aligned(void)\n \t\t/* align everything */\n \t\tlast_addr = RTE_PTR_ALIGN_CEIL(ms[memseg_idx].addr, RTE_CACHE_LINE_SIZE);\n \t\tlen = ms[memseg_idx].len - RTE_PTR_DIFF(last_addr, ms[memseg_idx].addr);\n-\t\tlen &= ~((size_t) CACHE_LINE_MASK);\n+\t\tlen &= ~((size_t) RTE_CACHE_LINE_MASK);\n \n \t\t/* cycle through all memzones */\n \t\tfor (memzone_idx = 0; memzone_idx < RTE_MAX_MEMZONE; memzone_idx++) {\n@@ -474,11 +474,11 @@ test_memzone_aligned(void)\n \t\tprintf(\"Unable to reserve 64-byte aligned memzone!\\n\");\n \t\treturn -1;\n \t}\n-\tif ((memzone_aligned_32->phys_addr & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_32->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n-\tif (((uintptr_t) memzone_aligned_32->addr & CACHE_LINE_MASK) != 0)\n+\tif (((uintptr_t) memzone_aligned_32->addr & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n-\tif ((memzone_aligned_32->len & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_32->len & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n \n \tif (memzone_aligned_128 == NULL) {\n@@ -489,7 +489,7 @@ test_memzone_aligned(void)\n \t\treturn -1;\n \tif (((uintptr_t) memzone_aligned_128->addr & 127) != 0)\n \t\treturn -1;\n-\tif ((memzone_aligned_128->len & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_128->len & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n \n \tif (memzone_aligned_256 == NULL) {\n@@ -500,7 +500,7 @@ test_memzone_aligned(void)\n \t\treturn -1;\n \tif (((uintptr_t) memzone_aligned_256->addr & 255) != 0)\n \t\treturn -1;\n-\tif ((memzone_aligned_256->len & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_256->len & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n \n \tif (memzone_aligned_512 == NULL) {\n@@ -511,7 +511,7 @@ test_memzone_aligned(void)\n \t\treturn -1;\n \tif (((uintptr_t) memzone_aligned_512->addr & 511) != 0)\n \t\treturn -1;\n-\tif ((memzone_aligned_512->len & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_512->len & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n \n \tif (memzone_aligned_1024 == NULL) {\n@@ -522,7 +522,7 @@ test_memzone_aligned(void)\n \t\treturn -1;\n \tif (((uintptr_t) memzone_aligned_1024->addr & 1023) != 0)\n \t\treturn -1;\n-\tif ((memzone_aligned_1024->len & CACHE_LINE_MASK) != 0)\n+\tif ((memzone_aligned_1024->len & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n \n \t/* check that zones don't overlap */\n@@ -588,7 +588,7 @@ check_memzone_bounded(const char *name, uint32_t len, uint32_t align,\n \t\treturn (-1);\n \t}\n \n-\tif ((mz->len & CACHE_LINE_MASK) != 0 || mz->len < len ||\n+\tif ((mz->len & RTE_CACHE_LINE_MASK) != 0 || mz->len < len ||\n \t\t\tmz->len < RTE_CACHE_LINE_SIZE) {\n \t\tprintf(\"%s(%s): invalid length\\n\",\n \t\t\t__func__, mz->name);\n@@ -952,17 +952,17 @@ test_memzone(void)\n \t/* check cache-line alignments */\n \tprintf(\"check alignments and lengths\\n\");\n \n-\tif ((memzone1->phys_addr & CACHE_LINE_MASK) != 0)\n+\tif ((memzone1->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n-\tif ((memzone2->phys_addr & CACHE_LINE_MASK) != 0)\n+\tif ((memzone2->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n-\tif (memzone3 != NULL && (memzone3->phys_addr & CACHE_LINE_MASK) != 0)\n+\tif (memzone3 != NULL && (memzone3->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n \t\treturn -1;\n-\tif ((memzone1->len & CACHE_LINE_MASK) != 0 || memzone1->len == 0)\n+\tif ((memzone1->len & RTE_CACHE_LINE_MASK) != 0 || memzone1->len == 0)\n \t\treturn -1;\n-\tif ((memzone2->len & CACHE_LINE_MASK) != 0 || memzone2->len == 0)\n+\tif ((memzone2->len & RTE_CACHE_LINE_MASK) != 0 || memzone2->len == 0)\n \t\treturn -1;\n-\tif (memzone3 != NULL && ((memzone3->len & CACHE_LINE_MASK) != 0 ||\n+\tif (memzone3 != NULL && ((memzone3->len & RTE_CACHE_LINE_MASK) != 0 ||\n \t\t\tmemzone3->len == 0))\n \t\treturn -1;\n \tif (memzone4->len != 1024)\ndiff --git a/lib/librte_acl/rte_acl_osdep_alone.h b/lib/librte_acl/rte_acl_osdep_alone.h\nindex 73d1701..a84b6f9 100644\n--- a/lib/librte_acl/rte_acl_osdep_alone.h\n+++ b/lib/librte_acl/rte_acl_osdep_alone.h\n@@ -181,7 +181,7 @@ rte_rdtsc(void)\n */\n #define\tSOCKET_ID_ANY\t-1 /**< Any NUMA socket. */\n #define\tRTE_CACHE_LINE_SIZE\t64 /**< Cache line size. */\n-#define\tCACHE_LINE_MASK\t(RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */\n+#define\tRTE_CACHE_LINE_MASK\t(RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */\n \n /**\n * Force alignment to cache line.\ndiff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c\nindex 0b4178c..aa2f740 100644\n--- a/lib/librte_distributor/rte_distributor.c\n+++ b/lib/librte_distributor/rte_distributor.c\n@@ -450,7 +450,7 @@ rte_distributor_create(const char *name,\n \tconst struct rte_memzone *mz;\n \n \t/* compilation-time checks */\n-\tRTE_BUILD_BUG_ON((sizeof(*d) & CACHE_LINE_MASK) != 0);\n+\tRTE_BUILD_BUG_ON((sizeof(*d) & RTE_CACHE_LINE_MASK) != 0);\n \tRTE_BUILD_BUG_ON((RTE_DISTRIB_MAX_WORKERS & 7) != 0);\n \tRTE_BUILD_BUG_ON(RTE_DISTRIB_MAX_WORKERS >\n \t\t\t\tsizeof(d->in_flight_bitmask) * CHAR_BIT);\ndiff --git a/lib/librte_eal/common/eal_common_memzone.c b/lib/librte_eal/common/eal_common_memzone.c\nindex 18e4f38..7af5a75 100644\n--- a/lib/librte_eal/common/eal_common_memzone.c\n+++ b/lib/librte_eal/common/eal_common_memzone.c\n@@ -169,13 +169,13 @@ memzone_reserve_aligned_thread_unsafe(const char *name, size_t len,\n \n \n \t/* align length on cache boundary. Check for overflow before doing so */\n-\tif (len > SIZE_MAX - CACHE_LINE_MASK) {\n+\tif (len > SIZE_MAX - RTE_CACHE_LINE_MASK) {\n \t\trte_errno = EINVAL; /* requested size too big */\n \t\treturn NULL;\n \t}\n \n-\tlen += CACHE_LINE_MASK;\n-\tlen &= ~((size_t) CACHE_LINE_MASK);\n+\tlen += RTE_CACHE_LINE_MASK;\n+\tlen &= ~((size_t) RTE_CACHE_LINE_MASK);\n \n \t/* save minimal requested length */\n \trequested_len = RTE_MAX((size_t)RTE_CACHE_LINE_SIZE, len);\n@@ -421,8 +421,8 @@ memseg_sanitize(struct rte_memseg *memseg)\n \tunsigned virt_align;\n \tunsigned off;\n \n-\tphys_align = memseg->phys_addr & CACHE_LINE_MASK;\n-\tvirt_align = (unsigned long)memseg->addr & CACHE_LINE_MASK;\n+\tphys_align = memseg->phys_addr & RTE_CACHE_LINE_MASK;\n+\tvirt_align = (unsigned long)memseg->addr & RTE_CACHE_LINE_MASK;\n \n \t/*\n \t * sanity check: phys_addr and addr must have the same\n@@ -438,13 +438,13 @@ memseg_sanitize(struct rte_memseg *memseg)\n \t}\n \n \t/* align start address */\n-\toff = (RTE_CACHE_LINE_SIZE - phys_align) & CACHE_LINE_MASK;\n+\toff = (RTE_CACHE_LINE_SIZE - phys_align) & RTE_CACHE_LINE_MASK;\n \tmemseg->phys_addr += off;\n \tmemseg->addr = (char *)memseg->addr + off;\n \tmemseg->len -= off;\n \n \t/* align end address */\n-\tmemseg->len &= ~((uint64_t)CACHE_LINE_MASK);\n+\tmemseg->len &= ~((uint64_t)RTE_CACHE_LINE_MASK);\n \n \treturn 0;\n }\ndiff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h\nindex 0502793..ab20c4b 100644\n--- a/lib/librte_eal/common/include/rte_memory.h\n+++ b/lib/librte_eal/common/include/rte_memory.h\n@@ -62,7 +62,7 @@ enum rte_page_sizes {\n #ifndef RTE_CACHE_LINE_SIZE\n #define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */\n #endif\n-#define CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */\n+#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */\n \n #define CACHE_LINE_ROUNDUP(size) \\\n \t(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))\ndiff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c\nindex bb09dae..8f10be8 100644\n--- a/lib/librte_mempool/rte_mempool.c\n+++ b/lib/librte_mempool/rte_mempool.c\n@@ -114,7 +114,7 @@ static unsigned optimize_object_size(unsigned obj_size)\n \t\tnrank = 1;\n \n \t/* process new object size */\n-\tnew_obj_size = (obj_size + CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE;\n+\tnew_obj_size = (obj_size + RTE_CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE;\n \twhile (get_gcd(new_obj_size, nrank * nchan) != 1)\n \t\tnew_obj_size++;\n \treturn new_obj_size * RTE_CACHE_LINE_SIZE;\n@@ -270,8 +270,8 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,\n \t\tsz->total_size = sz->header_size + sz->elt_size +\n \t\t\tsz->trailer_size;\n \t\tsz->trailer_size += ((RTE_CACHE_LINE_SIZE -\n-\t\t\t\t (sz->total_size & CACHE_LINE_MASK)) &\n-\t\t\t\t CACHE_LINE_MASK);\n+\t\t\t\t (sz->total_size & RTE_CACHE_LINE_MASK)) &\n+\t\t\t\t RTE_CACHE_LINE_MASK);\n \t}\n \n \t/*\n@@ -418,18 +418,18 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n \n \t/* compilation-time checks */\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool_cache) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_mempool, local_cache) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #endif\n #ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool_debug_stats) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_mempool, stats) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #endif\n \n \t/* check that we have an initialised tail queue */\n@@ -489,7 +489,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n \t * cache-aligned\n \t */\n \tprivate_data_size = (private_data_size +\n-\t\t\t CACHE_LINE_MASK) & (~CACHE_LINE_MASK);\n+\t\t\t RTE_CACHE_LINE_MASK) & (~RTE_CACHE_LINE_MASK);\n \n \tif (! rte_eal_has_hugepages()) {\n \t\t/*\ndiff --git a/lib/librte_ring/rte_ring.c b/lib/librte_ring/rte_ring.c\nindex e007b0f..f5899c4 100644\n--- a/lib/librte_ring/rte_ring.c\n+++ b/lib/librte_ring/rte_ring.c\n@@ -120,18 +120,18 @@ rte_ring_init(struct rte_ring *r, const char *name, unsigned count,\n {\n \t/* compilation-time checks */\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_ring) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #ifdef RTE_RING_SPLIT_PROD_CONS\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, cons) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #endif\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, prod) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #ifdef RTE_LIBRTE_RING_DEBUG\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_ring_debug_stats) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, stats) &\n-\t\t\t CACHE_LINE_MASK) != 0);\n+\t\t\t RTE_CACHE_LINE_MASK) != 0);\n #endif\n \n \t/* init the ring structure */\ndiff --git a/lib/librte_sched/rte_bitmap.h b/lib/librte_sched/rte_bitmap.h\nindex 43d1d43..95f3c0d 100644\n--- a/lib/librte_sched/rte_bitmap.h\n+++ b/lib/librte_sched/rte_bitmap.h\n@@ -249,7 +249,7 @@ rte_bitmap_init(uint32_t n_bits, uint8_t *mem, uint32_t mem_size)\n \t\treturn NULL;\n \t}\n \n-\tif ((mem == NULL) || (((uintptr_t) mem) & CACHE_LINE_MASK)) {\n+\tif ((mem == NULL) || (((uintptr_t) mem) & RTE_CACHE_LINE_MASK)) {\n \t\treturn NULL;\n \t}\n \n", "prefixes": [ "dpdk-dev", "2/3" ] }