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GET /api/patches/133282/?format=api
{ "id": 133282, "url": "https://patches.dpdk.org/api/patches/133282/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231025094806.962190-1-thomas@monjalon.net/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231025094806.962190-1-thomas@monjalon.net>", "list_archive_url": "https://inbox.dpdk.org/dev/20231025094806.962190-1-thomas@monjalon.net", "date": "2023-10-25T09:48:05", "name": "net/mlx5: add global API prefix to public constants", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "05f6963adcd2f69d38a403afe69df808f1f125c8", "submitter": { "id": 685, "url": "https://patches.dpdk.org/api/people/685/?format=api", "name": "Thomas Monjalon", "email": "thomas@monjalon.net" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231025094806.962190-1-thomas@monjalon.net/mbox/", "series": [ { "id": 29976, "url": "https://patches.dpdk.org/api/series/29976/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29976", "date": "2023-10-25T09:48:05", "name": "net/mlx5: add global API prefix to public constants", "version": 1, "mbox": "https://patches.dpdk.org/series/29976/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/133282/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/133282/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 548C7431FA;\n\tWed, 25 Oct 2023 11:48:58 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3A0ED402E8;\n\tWed, 25 Oct 2023 11:48:58 +0200 (CEST)", "from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com\n [64.147.123.19]) by mails.dpdk.org (Postfix) with ESMTP id 4819E402C5\n for <dev@dpdk.org>; Wed, 25 Oct 2023 11:48:57 +0200 (CEST)", "from compute2.internal (compute2.nyi.internal [10.202.2.46])\n by mailout.west.internal (Postfix) with ESMTP id F1A90320097C;\n Wed, 25 Oct 2023 05:48:54 -0400 (EDT)", "from mailfrontend2 ([10.202.2.163])\n by compute2.internal (MEProxy); Wed, 25 Oct 2023 05:48:55 -0400", "by mail.messagingengine.com (Postfix) with ESMTPA; Wed,\n 25 Oct 2023 05:48:53 -0400 (EDT)" ], "DKIM-Signature": [ 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bh=XOFM+XVsZixCZ\n l33HLkmQIKAQLxdiz59HFmwHkCXYWQ=; b=gAJ2fTZB1WOEs8auwpxak+4L3u7bL\n 2Lc4VPZSRE/DXc/ZWQNzCMzOumMeQzy/S14FdNeIZ7gcdbx4q02I6ZsoPTeZ9xcD\n xjrOBuOsxWM0bpm2/iz6+xhTjk/mRRv1X/+1X4ADlFyQ3gK1b/Yf5g7krw4/InDX\n 9yGyoh4dsTIgeL4vKdTYE1pyg5oOiOvCoz8J/n5ZsuCtsX7ZysdFnvi01UaHtsz8\n D9/dASCl7w4nEyyw8w1NhLyxQ+WbHLcgFxk9qaOJwvu9KqObgFhXfAx7RX6dA0a8\n IbAeQqKIW/qrhbYei/pHOZsvYf1eKp2rqmLZhTxxffPaD5dyfZj4jGVxg==" ], "X-ME-Sender": "<xms:huQ4ZY5FMQ8PVJmQtNvxIiwzWVEVFQTN0YDg_M_1kGCv2F04tQLCJA>\n <xme:huQ4ZZ5NVkeFE0SqeRZ150AtmQ2w9GAVJxLZZUb3nxIGb5ZaKp5fDoehaW60Q3p4d\n hH7pz7s5pQH8hqowQ>", "X-ME-Received": "\n <xmr:huQ4ZXdYg3LANHVbX63jL-O8XxJuGU0rUKtRQjZsL8s-arKTmeyndKYBVqN98tAQ1D9iEqs_eVXDlTZX2YvUjoFntke7XZY>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgedvkedrledtgddvtdcutefuodetggdotefrodftvf\n curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu\n uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc\n fjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefvhhhomhgrshcu\n ofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecuggftrf\n grthhtvghrnhepveevfeevieeihfetudekgeekleeigeffueekveduteeuffeiudevteei\n udekfeelnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh\n epthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth", "X-ME-Proxy": "<xmx:huQ4ZdIA_8cfl4ueprkSvTg_a0F3pySnQGZAhG4yd4Bz67L9CEWswg>\n <xmx:huQ4ZcLJK1y3Ji8oVdid5HnvoS0ocrebojENdJ-BZiyPLu-UYFNpwA>\n <xmx:huQ4ZezPp1FMvN36IpEhTfHJlIoCN812k08uGDYz8KK1omZ1MXljMg>\n <xmx:huQ4ZREOD90l90Eb-JArmlqIBuWArOiSpONzNeq5-20Jcm8tdRLkHQ>", "Feedback-ID": "i47234305:Fastmail", "From": "Thomas Monjalon <thomas@monjalon.net>", "To": "dev@dpdk.org", "Cc": "rongweil@nvidia.com, Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH] net/mlx5: add global API prefix to public constants", "Date": "Wed, 25 Oct 2023 11:48:05 +0200", "Message-ID": "<20231025094806.962190-1-thomas@monjalon.net>", "X-Mailer": "git-send-email 2.42.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The file rte_pmd_mlx5.h is a public API,\nso its components must be prefixed with RTE_PMD_.\n\nSigned-off-by: Thomas Monjalon <thomas@monjalon.net>\n---\n drivers/net/mlx5/mlx5.h | 6 +++---\n drivers/net/mlx5/mlx5_defs.h | 2 +-\n drivers/net/mlx5/mlx5_ethdev.c | 4 ++--\n drivers/net/mlx5/mlx5_flow.c | 28 ++++++++++++++--------------\n drivers/net/mlx5/mlx5_flow.h | 2 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 8 ++++----\n drivers/net/mlx5/mlx5_flow_hw.c | 4 ++--\n drivers/net/mlx5/mlx5_rx.c | 2 +-\n drivers/net/mlx5/mlx5_rx.h | 4 ++--\n drivers/net/mlx5/mlx5_rxq.c | 10 +++++-----\n drivers/net/mlx5/mlx5_testpmd.c | 4 ++--\n drivers/net/mlx5/rte_pmd_mlx5.h | 30 +++++++++++++++---------------\n 12 files changed, 52 insertions(+), 52 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0b709a1bda..9966c2c082 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1684,8 +1684,8 @@ struct mlx5_dv_flow_info {\n \tstruct rte_flow_attr attr;\n };\n \n-struct mlx5_flow_engine_mode_info {\n-\tenum mlx5_flow_engine_mode mode;\n+struct rte_pmd_mlx5_flow_engine_mode_info {\n+\tenum rte_pmd_mlx5_flow_engine_mode mode;\n \tuint32_t mode_flag;\n \t/* The list is maintained in insertion order. */\n \tLIST_HEAD(hot_up_info, mlx5_dv_flow_info) hot_upgrade;\n@@ -1834,7 +1834,7 @@ struct mlx5_priv {\n \tuint32_t nb_queue; /* HW steering queue number. */\n \tstruct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */\n \tuint32_t hws_mark_refcnt; /* HWS mark action reference counter. */\n-\tstruct mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */\n \tstruct mlx5_flow_hw_attr *hw_attr; /* HW Steering port configuration. */\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t/* Item template list. */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 2af8c731ef..dc5216cb24 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -181,7 +181,7 @@\n #define MLX5_MAX_INDIRECT_ACTIONS 3\n \n /* Maximum number of external Rx queues supported by rte_flow */\n-#define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1)\n+#define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1)\n \n /*\n * Linux definition of static_assert is found in /usr/include/assert.h.\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 4a85415ff3..3339da054e 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -129,11 +129,11 @@ mlx5_dev_configure(struct rte_eth_dev *dev)\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\tif (priv->ext_rxqs && rxqs_n >= MLX5_EXTERNAL_RX_QUEUE_ID_MIN) {\n+\tif (priv->ext_rxqs && rxqs_n >= RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN) {\n \t\tDRV_LOG(ERR, \"port %u cannot handle this many Rx queues (%u), \"\n \t\t\t\"the maximal number of internal Rx queues is %u\",\n \t\t\tdev->data->port_id, rxqs_n,\n-\t\t\tMLX5_EXTERNAL_RX_QUEUE_ID_MIN - 1);\n+\t\t\tRTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN - 1);\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 8ad85e6027..ca4702efd9 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -170,7 +170,7 @@ mlx5_need_cache_flow(const struct mlx5_priv *priv,\n {\n \treturn priv->isolated && priv->sh->config.dv_flow_en == 1 &&\n \t\t(attr ? !attr->group : true) &&\n-\t\tpriv->mode_info.mode == MLX5_FLOW_ENGINE_MODE_STANDBY &&\n+\t\tpriv->mode_info.mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY &&\n \t\t(!priv->sh->config.dv_esw_en || !priv->sh->config.fdb_def_rule);\n }\n \n@@ -7632,7 +7632,7 @@ mlx5_flow_cache_flow_info(struct rte_eth_dev *dev,\n \t\t\t uint32_t flow_idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n \tstruct mlx5_dv_flow_info *flow_info, *tmp_info;\n \tstruct rte_flow_error error;\n \tint len, ret;\n@@ -7706,7 +7706,7 @@ static int\n mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n \tstruct mlx5_dv_flow_info *flow_info;\n \tstruct rte_flow_attr attr;\n \tstruct rte_flow_error error;\n@@ -7769,7 +7769,7 @@ mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio)\n * Set the mode of the flow engine of a process to active or standby during live migration.\n *\n * @param[in] mode\n- * MLX5 flow engine mode, @see `enum mlx5_flow_engine_mode`.\n+ * MLX5 flow engine mode, @see `enum rte_pmd_mlx5_flow_engine_mode`.\n * @param[in] flags\n * Flow engine mode specific flags.\n *\n@@ -7777,20 +7777,20 @@ mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio)\n * Negative value on error, positive on success.\n */\n int\n-rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flags)\n+rte_pmd_mlx5_flow_engine_set_mode(enum rte_pmd_mlx5_flow_engine_mode mode, uint32_t flags)\n {\n \tstruct mlx5_priv *priv;\n-\tstruct mlx5_flow_engine_mode_info *mode_info;\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info *mode_info;\n \tstruct mlx5_dv_flow_info *flow_info, *tmp_info;\n \tuint16_t port, port_id;\n \tuint16_t toggle_num = 0;\n \tstruct rte_eth_dev *dev;\n-\tenum mlx5_flow_engine_mode orig_mode;\n+\tenum rte_pmd_mlx5_flow_engine_mode orig_mode;\n \tuint32_t orig_flags;\n \tbool need_toggle = false;\n \n \t/* Check if flags combinations are supported. */\n-\tif (flags && flags != MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS) {\n+\tif (flags && flags != RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS) {\n \t\tDRV_LOG(ERR, \"Doesn't support such flags %u\", flags);\n \t\treturn -1;\n \t}\n@@ -7813,7 +7813,7 @@ rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flag\n \t\t\tcontinue;\n \t\t}\n \t\t/* Active -> standby. */\n-\t\tif (mode == MLX5_FLOW_ENGINE_MODE_STANDBY) {\n+\t\tif (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY) {\n \t\t\tif (!LIST_EMPTY(&mode_info->hot_upgrade)) {\n \t\t\t\tDRV_LOG(ERR, \"Cached rule existed\");\n \t\t\t\torig_mode = mode_info->mode;\n@@ -7824,7 +7824,7 @@ rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flag\n \t\t\tmode_info->mode = mode;\n \t\t\ttoggle_num++;\n \t\t/* Standby -> active. */\n-\t\t} else if (mode == MLX5_FLOW_ENGINE_MODE_ACTIVE) {\n+\t\t} else if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) {\n \t\t\tif (LIST_EMPTY(&mode_info->hot_upgrade)) {\n \t\t\t\tDRV_LOG(INFO, \"No cached rule existed\");\n \t\t\t} else {\n@@ -7838,7 +7838,7 @@ rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flag\n \t\t\ttoggle_num++;\n \t\t}\n \t}\n-\tif (mode == MLX5_FLOW_ENGINE_MODE_ACTIVE) {\n+\tif (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) {\n \t\t/* Clear cache flow rules. */\n \t\tMLX5_ETH_FOREACH_DEV(port, NULL) {\n \t\t\tpriv = rte_eth_devices[port].data->dev_private;\n@@ -7913,7 +7913,7 @@ mlx5_flow_create(struct rte_eth_dev *dev,\n \tif (unlikely(mlx5_need_cache_flow(priv, attr))) {\n \t\tif (attr->transfer ||\n \t\t (attr->ingress &&\n-\t\t !(priv->mode_info.mode_flag & MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS)))\n+\t\t !(priv->mode_info.mode_flag & RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS)))\n \t\t\tnew_attr->priority += 1;\n \t}\n \tflow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, attr, items, actions, true, error);\n@@ -7982,7 +7982,7 @@ mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tuint32_t num_flushed = 0, fidx = 1;\n \tstruct rte_flow *flow;\n-\tstruct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n \tstruct mlx5_dv_flow_info *flow_info;\n \n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n@@ -8475,7 +8475,7 @@ mlx5_flow_destroy(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error __rte_unused)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n+\tstruct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info;\n \tstruct mlx5_dv_flow_info *flow_info;\n \n \tif (priv->sh->config.dv_flow_en == 2)\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 903ff66d72..e9fe294e79 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1656,7 +1656,7 @@ flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id)\n \tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n \t\treturn mlx5_flow_hw_aso_tag;\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n-\t\tif (id == MLX5_LINEAR_HASH_TAG_INDEX)\n+\t\tif (id == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)\n \t\t\treturn REG_C_3;\n \t\tMLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);\n \t\treturn mlx5_flow_hw_avl_tags[id];\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 3dc2fe5c71..ddaf1a3508 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1916,7 +1916,7 @@ mlx5_flow_field_id_to_modify_info\n \t\t\tuint8_t tag_index = flow_tag_index_get(data);\n \t\t\tint reg;\n \n-\t\t\toff_be = (tag_index == MLX5_LINEAR_HASH_TAG_INDEX) ?\n+\t\t\toff_be = (tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) ?\n \t\t\t\t 16 - (data->offset + width) + 16 : data->offset;\n \t\t\tif (priv->sh->config.dv_flow_en == 2)\n \t\t\t\treg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG,\n@@ -19650,18 +19650,18 @@ flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tint ret = 0;\n \n-\tif ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {\n+\tif ((domains & RTE_PMD_MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {\n \t\tret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,\n \t\t\t\t\t\tflags);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n \t}\n-\tif ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {\n+\tif ((domains & RTE_PMD_MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {\n \t\tret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n \t}\n-\tif ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {\n+\tif ((domains & RTE_PMD_MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {\n \t\tret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);\n \t\tif (ret != 0)\n \t\t\treturn ret;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 6fcf654e4a..8fd76b541b 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -1035,7 +1035,7 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,\n \n \t\t\tvalue = *(const unaligned_uint32_t *)item.spec;\n \t\t\tif (conf->dst.field == RTE_FLOW_FIELD_TAG &&\n-\t\t\t tag_index == MLX5_LINEAR_HASH_TAG_INDEX)\n+\t\t\t tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)\n \t\t\t\tvalue = rte_cpu_to_be_32(value << 16);\n \t\t\telse\n \t\t\t\tvalue = rte_cpu_to_be_32(value);\n@@ -2154,7 +2154,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \n \t\tvalue_p = (unaligned_uint32_t *)values;\n \t\tif (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG &&\n-\t\t tag_index == MLX5_LINEAR_HASH_TAG_INDEX)\n+\t\t tag_index == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX)\n \t\t\t*value_p = rte_cpu_to_be_32(*value_p << 16);\n \t\telse\n \t\t\t*value_p = rte_cpu_to_be_32(*value_p);\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 392784050f..5bf1a679b2 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -1560,7 +1560,7 @@ int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate,\n \tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tbool lwm_triggered =\n-\t !!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n+\t !!(flags & RTE_BIT32(RTE_PMD_MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n \n \tif (!lwm_triggered) {\n \t\tpriv->sh->host_shaper_rate = rate;\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex baeb4797aa..2fce908499 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -663,9 +663,9 @@ mlx5_is_external_rxq(struct rte_eth_dev *dev, uint16_t queue_idx)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_external_rxq *rxq;\n \n-\tif (!priv->ext_rxqs || queue_idx < MLX5_EXTERNAL_RX_QUEUE_ID_MIN)\n+\tif (!priv->ext_rxqs || queue_idx < RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN)\n \t\treturn false;\n-\trxq = &priv->ext_rxqs[queue_idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n+\trxq = &priv->ext_rxqs[queue_idx - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n \treturn !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED);\n }\n \ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 8ef7860e16..88b2dc54b3 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2176,7 +2176,7 @@ mlx5_ext_rxq_get(struct rte_eth_dev *dev, uint16_t idx)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n \tMLX5_ASSERT(mlx5_is_external_rxq(dev, idx));\n-\treturn &priv->ext_rxqs[idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n+\treturn &priv->ext_rxqs[idx - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n }\n \n /**\n@@ -2341,7 +2341,7 @@ mlx5_ext_rxq_verify(struct rte_eth_dev *dev)\n \tif (priv->ext_rxqs == NULL)\n \t\treturn 0;\n \n-\tfor (i = MLX5_EXTERNAL_RX_QUEUE_ID_MIN; i <= UINT16_MAX ; ++i) {\n+\tfor (i = RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN; i <= UINT16_MAX ; ++i) {\n \t\trxq = mlx5_ext_rxq_get(dev, i);\n \t\tif (rxq->refcnt < 2)\n \t\t\tcontinue;\n@@ -3210,9 +3210,9 @@ mlx5_external_rx_queue_get_validate(uint16_t port_id, uint16_t dpdk_idx)\n \tstruct rte_eth_dev *dev;\n \tstruct mlx5_priv *priv;\n \n-\tif (dpdk_idx < MLX5_EXTERNAL_RX_QUEUE_ID_MIN) {\n+\tif (dpdk_idx < RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN) {\n \t\tDRV_LOG(ERR, \"Queue index %u should be in range: [%u, %u].\",\n-\t\t\tdpdk_idx, MLX5_EXTERNAL_RX_QUEUE_ID_MIN, UINT16_MAX);\n+\t\t\tdpdk_idx, RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN, UINT16_MAX);\n \t\trte_errno = EINVAL;\n \t\treturn NULL;\n \t}\n@@ -3243,7 +3243,7 @@ mlx5_external_rx_queue_get_validate(uint16_t port_id, uint16_t dpdk_idx)\n \t * DevX, external RxQs array is allocated.\n \t */\n \tMLX5_ASSERT(priv->ext_rxqs != NULL);\n-\treturn &priv->ext_rxqs[dpdk_idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n+\treturn &priv->ext_rxqs[dpdk_idx - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN];\n }\n \n int\ndiff --git a/drivers/net/mlx5/mlx5_testpmd.c b/drivers/net/mlx5/mlx5_testpmd.c\nindex 879ea2826e..b108f0e9dd 100644\n--- a/drivers/net/mlx5/mlx5_testpmd.c\n+++ b/drivers/net/mlx5/mlx5_testpmd.c\n@@ -112,10 +112,10 @@ mlx5_test_set_port_host_shaper(uint16_t port_id, uint16_t avail_thresh_triggered\n \thost_shaper_avail_thresh_triggered[port_id] = avail_thresh_triggered ? 1 : 0;\n \tif (!avail_thresh_triggered) {\n \t\tret = rte_pmd_mlx5_host_shaper_config(port_id, 0,\n-\t\tRTE_BIT32(MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n+\t\tRTE_BIT32(RTE_PMD_MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n \t} else {\n \t\tret = rte_pmd_mlx5_host_shaper_config(port_id, 1,\n-\t\tRTE_BIT32(MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n+\t\tRTE_BIT32(RTE_PMD_MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n \t}\n \tif (ret)\n \t\treturn ret;\ndiff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h\nindex b1a92b3dd0..654dd3cff3 100644\n--- a/drivers/net/mlx5/rte_pmd_mlx5.h\n+++ b/drivers/net/mlx5/rte_pmd_mlx5.h\n@@ -38,9 +38,9 @@ extern \"C\" {\n __rte_experimental\n int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n);\n \n-#define MLX5_DOMAIN_BIT_NIC_RX\t(1 << 0) /**< NIC RX domain bit mask. */\n-#define MLX5_DOMAIN_BIT_NIC_TX\t(1 << 1) /**< NIC TX domain bit mask. */\n-#define MLX5_DOMAIN_BIT_FDB\t(1 << 2) /**< FDB (TX + RX) domain bit mask. */\n+#define RTE_PMD_MLX5_DOMAIN_BIT_NIC_RX\t(1 << 0) /**< NIC RX domain bit mask. */\n+#define RTE_PMD_MLX5_DOMAIN_BIT_NIC_TX\t(1 << 1) /**< NIC TX domain bit mask. */\n+#define RTE_PMD_MLX5_DOMAIN_BIT_FDB\t(1 << 2) /**< FDB (TX + RX) domain bit mask. */\n \n /**\n * Synchronize the flows to make them take effort on hardware.\n@@ -52,7 +52,7 @@ int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n);\n * @param[in] domains\n * Refer to \"/usr/include/infiniband/mlx5dv.h\".\n * Bitmask of domains in which the synchronization will be done.\n- * MLX5_DOMAIN_BIT* macros are used to specify the domains.\n+ * RTE_PMD_MLX5_DOMAIN_BIT_* macros are used to specify the domains.\n * An ADD or OR operation could be used to synchronize flows in more than\n * one domain per call.\n *\n@@ -66,12 +66,12 @@ int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains);\n /**\n * External Rx queue rte_flow index minimal value.\n */\n-#define MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)\n+#define RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)\n \n /**\n * Tag level to set the linear hash index.\n */\n-#define MLX5_LINEAR_HASH_TAG_INDEX 255\n+#define RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX 255\n \n /**\n * Update mapping between rte_flow queue index (16 bits) and HW queue index (32\n@@ -123,7 +123,7 @@ int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,\n * Unset this flag to update the rate of the host port shaper directly in\n * the API call; use rate 0 to disable the current shaper.\n */\n-#define MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED 0\n+#define RTE_PMD_MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED 0\n \n /**\n * Configure a HW shaper to limit Tx rate for a host port.\n@@ -135,7 +135,7 @@ int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,\n * @param[in] rate\n * Unit is 100Mbps, setting the rate to 0 disables the shaper.\n * @param[in] flags\n- * Host shaper flags.\n+ * Host shaper flags (see RTE_PMD_MLX5_HOST_SHAPER_FLAG_*).\n * @return\n * 0 : operation success.\n * Otherwise:\n@@ -164,16 +164,16 @@ __rte_experimental\n int rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num);\n \n /* MLX5 flow engine mode definition for live migration. */\n-enum mlx5_flow_engine_mode {\n-\tMLX5_FLOW_ENGINE_MODE_ACTIVE, /* active means high priority, effective in HW. */\n-\tMLX5_FLOW_ENGINE_MODE_STANDBY, /* standby mode with lower priority flow rules. */\n+enum rte_pmd_mlx5_flow_engine_mode {\n+\tRTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE, /* active means high priority, effective in HW. */\n+\tRTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY, /* standby mode with lower priority flow rules. */\n };\n \n /**\n * When set on the flow engine of a standby process, ingress flow rules will be effective\n * in active and standby processes, so the ingress traffic may be duplicated.\n */\n-#define MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS RTE_BIT32(0)\n+#define RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS RTE_BIT32(0)\n \n /**\n * @warning\n@@ -217,9 +217,9 @@ enum mlx5_flow_engine_mode {\n * old: shutdown\n *\n * @param mode\n- * The desired mode `mlx5_flow_engine_mode`.\n+ * The desired mode (see rte_pmd_mlx5_flow_engine_mode).\n * @param flags\n- * Mode specific flags.\n+ * Mode specific flags (see RTE_PMD_MLX5_FLOW_ENGINE_FLAG_*).\n * @return\n * Positive value on success, -rte_errno value on error:\n * - (> 0) Number of switched devices.\n@@ -227,7 +227,7 @@ enum mlx5_flow_engine_mode {\n * - (-EPERM) if operation failed and can't recover.\n */\n __rte_experimental\n-int rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flags);\n+int rte_pmd_mlx5_flow_engine_set_mode(enum rte_pmd_mlx5_flow_engine_mode mode, uint32_t flags);\n \n #ifdef __cplusplus\n }\n", "prefixes": [] }