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GET /api/patches/132380/?format=api
{ "id": 132380, "url": "https://patches.dpdk.org/api/patches/132380/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231007023339.1546659-11-chaoyong.he@corigine.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231007023339.1546659-11-chaoyong.he@corigine.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231007023339.1546659-11-chaoyong.he@corigine.com", "date": "2023-10-07T02:33:38", "name": "[10/11] net/nfp: adjust logic to make it more readable", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "59219ff8a311809658f2a826b4cd8118a2c11787", "submitter": { "id": 2554, "url": "https://patches.dpdk.org/api/people/2554/?format=api", "name": "Chaoyong He", "email": "chaoyong.he@corigine.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231007023339.1546659-11-chaoyong.he@corigine.com/mbox/", "series": [ { "id": 29758, "url": "https://patches.dpdk.org/api/series/29758/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29758", "date": "2023-10-07T02:33:28", "name": "Unify the PMD coding style", "version": 1, "mbox": "https://patches.dpdk.org/series/29758/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/132380/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/132380/checks/", "tags": {}, "related": [], "headers": { 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"Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=corigine.com;", "From": "Chaoyong He <chaoyong.he@corigine.com>", "To": "dev@dpdk.org", "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>", "Subject": "[PATCH 10/11] net/nfp: adjust logic to make it more readable", "Date": "Sat, 7 Oct 2023 10:33:38 +0800", "Message-Id": "<20231007023339.1546659-11-chaoyong.he@corigine.com>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20231007023339.1546659-1-chaoyong.he@corigine.com>", "References": "<20231007023339.1546659-1-chaoyong.he@corigine.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR03CA0212.namprd03.prod.outlook.com\n (2603:10b6:a03:39f::7) To SJ0PR13MB5545.namprd13.prod.outlook.com\n (2603:10b6:a03:424::5)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", 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"X-OriginatorOrg": "corigine.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 757f9eae-4c1f-4ae2-d899-08dbc6dde744", "X-MS-Exchange-CrossTenant-AuthSource": "SJ0PR13MB5545.namprd13.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Oct 2023 02:34:17.5803 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fe128f2c-073b-4c20-818e-7246a585940c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n tOH7eiNVYQc/GtMwcbDIGx3bnssrS4/FuFeYkUGpaxrzCEz7JoCRzpM8QtEXJLXJ6jWKg9XdegJeDQ75uMzWcdS1e8FRcuHa+oW1kY709NA=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR13MB3936", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adjust some logic to make it easier to understand.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Long Wu <long.wu@corigine.com>\nReviewed-by: Peng Zhang <peng.zhang@corigine.com>\n---\n drivers/net/nfp/nfp_common.c | 83 +++++++++++++++++---------------\n drivers/net/nfp/nfp_cpp_bridge.c | 5 +-\n drivers/net/nfp/nfp_ctrl.h | 2 -\n drivers/net/nfp/nfp_ethdev.c | 23 ++++-----\n drivers/net/nfp/nfp_ethdev_vf.c | 15 +++---\n drivers/net/nfp/nfp_rxtx.c | 2 +-\n 6 files changed, 61 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/nfp/nfp_common.c b/drivers/net/nfp/nfp_common.c\nindex 3409ee8cb8..f6cd506dd6 100644\n--- a/drivers/net/nfp/nfp_common.c\n+++ b/drivers/net/nfp/nfp_common.c\n@@ -467,19 +467,19 @@ nfp_net_enable_queues(struct rte_eth_dev *dev)\n {\n \tuint16_t i;\n \tstruct nfp_net_hw *hw;\n-\tuint64_t enabled_queues = 0;\n+\tuint64_t enabled_queues;\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \t/* Enabling the required TX queues in the device */\n+\tenabled_queues = 0;\n \tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n \tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n \n-\tenabled_queues = 0;\n-\n \t/* Enabling the required RX queues in the device */\n+\tenabled_queues = 0;\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n \t\tenabled_queues |= (1 << i);\n \n@@ -619,33 +619,33 @@ uint32_t\n nfp_check_offloads(struct rte_eth_dev *dev)\n {\n \tuint32_t ctrl = 0;\n+\tuint64_t rx_offload;\n+\tuint64_t tx_offload;\n \tstruct nfp_net_hw *hw;\n \tstruct rte_eth_conf *dev_conf;\n-\tstruct rte_eth_rxmode *rxmode;\n-\tstruct rte_eth_txmode *txmode;\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tdev_conf = &dev->data->dev_conf;\n-\trxmode = &dev_conf->rxmode;\n-\ttxmode = &dev_conf->txmode;\n+\trx_offload = dev_conf->rxmode.offloads;\n+\ttx_offload = dev_conf->txmode.offloads;\n \n-\tif ((rxmode->offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) != 0) {\n+\tif ((rx_offload & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) != 0) {\n \t\tif ((hw->cap & NFP_NET_CFG_CTRL_RXCSUM) != 0)\n \t\t\tctrl |= NFP_NET_CFG_CTRL_RXCSUM;\n \t}\n \n-\tif ((rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) != 0)\n+\tif ((rx_offload & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) != 0)\n \t\tnfp_net_enbable_rxvlan_cap(hw, &ctrl);\n \n-\tif ((rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) != 0) {\n+\tif ((rx_offload & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) != 0) {\n \t\tif ((hw->cap & NFP_NET_CFG_CTRL_RXQINQ) != 0)\n \t\t\tctrl |= NFP_NET_CFG_CTRL_RXQINQ;\n \t}\n \n \thw->mtu = dev->data->mtu;\n \n-\tif ((txmode->offloads & RTE_ETH_TX_OFFLOAD_VLAN_INSERT) != 0) {\n+\tif ((tx_offload & RTE_ETH_TX_OFFLOAD_VLAN_INSERT) != 0) {\n \t\tif ((hw->cap & NFP_NET_CFG_CTRL_TXVLAN_V2) != 0)\n \t\t\tctrl |= NFP_NET_CFG_CTRL_TXVLAN_V2;\n \t\telse if ((hw->cap & NFP_NET_CFG_CTRL_TXVLAN) != 0)\n@@ -661,14 +661,14 @@ nfp_check_offloads(struct rte_eth_dev *dev)\n \t\tctrl |= NFP_NET_CFG_CTRL_L2MC;\n \n \t/* TX checksum offload */\n-\tif ((txmode->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) != 0 ||\n-\t\t\t(txmode->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) != 0 ||\n-\t\t\t(txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) != 0)\n+\tif ((tx_offload & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) != 0 ||\n+\t\t\t(tx_offload & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) != 0 ||\n+\t\t\t(tx_offload & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) != 0)\n \t\tctrl |= NFP_NET_CFG_CTRL_TXCSUM;\n \n \t/* LSO offload */\n-\tif ((txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO) != 0 ||\n-\t\t\t(txmode->offloads & RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO) != 0) {\n+\tif ((tx_offload & RTE_ETH_TX_OFFLOAD_TCP_TSO) != 0 ||\n+\t\t\t(tx_offload & RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO) != 0) {\n \t\tif ((hw->cap & NFP_NET_CFG_CTRL_LSO) != 0)\n \t\t\tctrl |= NFP_NET_CFG_CTRL_LSO;\n \t\telse\n@@ -676,7 +676,7 @@ nfp_check_offloads(struct rte_eth_dev *dev)\n \t}\n \n \t/* RX gather */\n-\tif ((txmode->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) != 0)\n+\tif ((tx_offload & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) != 0)\n \t\tctrl |= NFP_NET_CFG_CTRL_GATHER;\n \n \treturn ctrl;\n@@ -766,11 +766,10 @@ nfp_net_link_update(struct rte_eth_dev *dev,\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\t/* Read link status */\n-\tnn_link_status = nn_cfg_readw(hw, NFP_NET_CFG_STS);\n-\n \tmemset(&link, 0, sizeof(struct rte_eth_link));\n \n+\t/* Read link status */\n+\tnn_link_status = nn_cfg_readw(hw, NFP_NET_CFG_STS);\n \tif ((nn_link_status & NFP_NET_CFG_STS_LINK) != 0)\n \t\tlink.link_status = RTE_ETH_LINK_UP;\n \n@@ -828,6 +827,9 @@ nfp_net_stats_get(struct rte_eth_dev *dev,\n \tstruct nfp_net_hw *hw;\n \tstruct rte_eth_stats nfp_dev_stats;\n \n+\tif (stats == NULL)\n+\t\treturn -EINVAL;\n+\n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tmemset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));\n@@ -892,11 +894,8 @@ nfp_net_stats_get(struct rte_eth_dev *dev,\n \t\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);\n \tnfp_dev_stats.imissed -= hw->eth_stats_base.imissed;\n \n-\tif (stats != NULL) {\n-\t\tmemcpy(stats, &nfp_dev_stats, sizeof(*stats));\n-\t\treturn 0;\n-\t}\n-\treturn -EINVAL;\n+\tmemcpy(stats, &nfp_dev_stats, sizeof(*stats));\n+\treturn 0;\n }\n \n /*\n@@ -1379,13 +1378,14 @@ nfp_rx_queue_intr_enable(struct rte_eth_dev *dev,\n \tstruct nfp_net_hw *hw;\n \tstruct rte_pci_device *pci_dev;\n \n-\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tpci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tif (rte_intr_type_get(pci_dev->intr_handle) != RTE_INTR_HANDLE_UIO)\n \t\tbase = 1;\n \n \t/* Make sure all updates are written before un-masking */\n \trte_wmb();\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),\n \t\t\tNFP_NET_CFG_ICR_UNMASKED);\n \treturn 0;\n@@ -1399,14 +1399,16 @@ nfp_rx_queue_intr_disable(struct rte_eth_dev *dev,\n \tstruct nfp_net_hw *hw;\n \tstruct rte_pci_device *pci_dev;\n \n-\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tpci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tif (rte_intr_type_get(pci_dev->intr_handle) != RTE_INTR_HANDLE_UIO)\n \t\tbase = 1;\n \n \t/* Make sure all updates are written before un-masking */\n \trte_wmb();\n-\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), NFP_NET_CFG_ICR_RXTX);\n+\n \treturn 0;\n }\n \n@@ -1445,13 +1447,13 @@ nfp_net_irq_unmask(struct rte_eth_dev *dev)\n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tpci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \n+\t/* Make sure all updates are written before un-masking */\n+\trte_wmb();\n+\n \tif ((hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) != 0) {\n \t\t/* If MSI-X auto-masking is used, clear the entry */\n-\t\trte_wmb();\n \t\trte_intr_ack(pci_dev->intr_handle);\n \t} else {\n-\t\t/* Make sure all updates are written before un-masking */\n-\t\trte_wmb();\n \t\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),\n \t\t\t\tNFP_NET_CFG_ICR_UNMASKED);\n \t}\n@@ -1548,19 +1550,18 @@ nfp_net_vlan_offload_set(struct rte_eth_dev *dev,\n \tint ret;\n \tuint32_t update;\n \tuint32_t new_ctrl;\n+\tuint64_t rx_offload;\n \tstruct nfp_net_hw *hw;\n \tuint32_t rxvlan_ctrl = 0;\n-\tstruct rte_eth_conf *dev_conf;\n \n \thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tdev_conf = &dev->data->dev_conf;\n+\trx_offload = dev->data->dev_conf.rxmode.offloads;\n \tnew_ctrl = hw->ctrl;\n \n-\tnfp_net_enbable_rxvlan_cap(hw, &rxvlan_ctrl);\n-\n \t/* VLAN stripping setting */\n \tif ((mask & RTE_ETH_VLAN_STRIP_MASK) != 0) {\n-\t\tif ((dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) != 0)\n+\t\tnfp_net_enbable_rxvlan_cap(hw, &rxvlan_ctrl);\n+\t\tif ((rx_offload & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) != 0)\n \t\t\tnew_ctrl |= rxvlan_ctrl;\n \t\telse\n \t\t\tnew_ctrl &= ~rxvlan_ctrl;\n@@ -1568,7 +1569,7 @@ nfp_net_vlan_offload_set(struct rte_eth_dev *dev,\n \n \t/* QinQ stripping setting */\n \tif ((mask & RTE_ETH_QINQ_STRIP_MASK) != 0) {\n-\t\tif ((dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) != 0)\n+\t\tif ((rx_offload & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) != 0)\n \t\t\tnew_ctrl |= NFP_NET_CFG_CTRL_RXQINQ;\n \t\telse\n \t\t\tnew_ctrl &= ~NFP_NET_CFG_CTRL_RXQINQ;\n@@ -1580,10 +1581,12 @@ nfp_net_vlan_offload_set(struct rte_eth_dev *dev,\n \tupdate = NFP_NET_CFG_UPDATE_GEN;\n \n \tret = nfp_net_reconfig(hw, new_ctrl, update);\n-\tif (ret == 0)\n-\t\thw->ctrl = new_ctrl;\n+\tif (ret != 0)\n+\t\treturn ret;\n \n-\treturn ret;\n+\thw->ctrl = new_ctrl;\n+\n+\treturn 0;\n }\n \n static int\ndiff --git a/drivers/net/nfp/nfp_cpp_bridge.c b/drivers/net/nfp/nfp_cpp_bridge.c\nindex 080070f58b..f37de7060a 100644\n--- a/drivers/net/nfp/nfp_cpp_bridge.c\n+++ b/drivers/net/nfp/nfp_cpp_bridge.c\n@@ -22,9 +22,6 @@\n #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)\n \n /* Prototypes */\n-static int nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp);\n-static int nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp);\n-static int nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp);\n static int nfp_cpp_bridge_service_func(void *args);\n \n int\n@@ -438,7 +435,7 @@ nfp_cpp_bridge_service_func(void *args)\n \t\t\treturn -EIO;\n \t\t}\n \n-\t\twhile (1) {\n+\t\tfor (;;) {\n \t\t\tret = recv(datafd, &op, 4, 0);\n \t\t\tif (ret <= 0) {\n \t\t\t\tPMD_CPP_LOG(DEBUG, \"%s: socket close\", __func__);\ndiff --git a/drivers/net/nfp/nfp_ctrl.h b/drivers/net/nfp/nfp_ctrl.h\nindex 71fe125420..1012b37b1f 100644\n--- a/drivers/net/nfp/nfp_ctrl.h\n+++ b/drivers/net/nfp/nfp_ctrl.h\n@@ -442,8 +442,6 @@ struct nfp_net_fw_ver {\n #define NFP_MAC_STATS_TX_PAUSE_FRAMES_CLASS6 (NFP_MAC_STATS_BASE + 0x1f0)\n #define NFP_MAC_STATS_TX_PAUSE_FRAMES_CLASS7 (NFP_MAC_STATS_BASE + 0x1f8)\n \n-#define NFP_PF_CSR_SLICE_SIZE (32 * 1024)\n-\n /*\n * General use mailbox area (0x1800 - 0x19ff)\n * 4B used for update command and 4B return code followed by\ndiff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c\nindex 0493548c81..362fd2b601 100644\n--- a/drivers/net/nfp/nfp_ethdev.c\n+++ b/drivers/net/nfp/nfp_ethdev.c\n@@ -80,7 +80,7 @@ nfp_net_start(struct rte_eth_dev *dev)\n \t\t\t * Better not to share LSC with RX interrupts.\n \t\t\t * Unregistering LSC interrupt handler\n \t\t\t */\n-\t\t\trte_intr_callback_unregister(pci_dev->intr_handle,\n+\t\t\trte_intr_callback_unregister(intr_handle,\n \t\t\t\t\tnfp_net_dev_interrupt_handler, (void *)dev);\n \n \t\t\tif (dev->data->nb_rx_queues > 1) {\n@@ -525,7 +525,7 @@ nfp_net_init(struct rte_eth_dev *eth_dev)\n \t\t\treturn -ENODEV;\n \n \t\t/* Use port offset in pf ctrl_bar for this ports control bar */\n-\t\thw->ctrl_bar = pf_dev->ctrl_bar + (port * NFP_PF_CSR_SLICE_SIZE);\n+\t\thw->ctrl_bar = pf_dev->ctrl_bar + (port * NFP_NET_CFG_BAR_SZ);\n \t\thw->mac_stats = app_fw_nic->ports[0]->mac_stats_bar + (port * NFP_MAC_STATS_SIZE);\n \t}\n \n@@ -743,8 +743,7 @@ nfp_init_app_fw_nic(struct nfp_pf_dev *pf_dev,\n \t\tconst struct nfp_dev_info *dev_info)\n {\n \tuint8_t i;\n-\tint ret;\n-\tint err = 0;\n+\tint ret = 0;\n \tuint32_t total_vnics;\n \tstruct nfp_net_hw *hw;\n \tunsigned int numa_node;\n@@ -765,8 +764,8 @@ nfp_init_app_fw_nic(struct nfp_pf_dev *pf_dev,\n \tpf_dev->app_fw_priv = app_fw_nic;\n \n \t/* Read the number of vNIC's created for the PF */\n-\ttotal_vnics = nfp_rtsym_read_le(pf_dev->sym_tbl, \"nfd_cfg_pf0_num_ports\", &err);\n-\tif (err != 0 || total_vnics == 0 || total_vnics > 8) {\n+\ttotal_vnics = nfp_rtsym_read_le(pf_dev->sym_tbl, \"nfd_cfg_pf0_num_ports\", &ret);\n+\tif (ret != 0 || total_vnics == 0 || total_vnics > 8) {\n \t\tPMD_INIT_LOG(ERR, \"nfd_cfg_pf0_num_ports symbol with wrong value\");\n \t\tret = -ENODEV;\n \t\tgoto app_cleanup;\n@@ -874,8 +873,7 @@ nfp_init_app_fw_nic(struct nfp_pf_dev *pf_dev,\n static int\n nfp_pf_init(struct rte_pci_device *pci_dev)\n {\n-\tint ret;\n-\tint err = 0;\n+\tint ret = 0;\n \tuint64_t addr;\n \tuint32_t cpp_id;\n \tstruct nfp_cpp *cpp;\n@@ -943,8 +941,8 @@ nfp_pf_init(struct rte_pci_device *pci_dev)\n \t}\n \n \t/* Read the app ID of the firmware loaded */\n-\tapp_fw_id = nfp_rtsym_read_le(sym_tbl, \"_pf0_net_app_id\", &err);\n-\tif (err != 0) {\n+\tapp_fw_id = nfp_rtsym_read_le(sym_tbl, \"_pf0_net_app_id\", &ret);\n+\tif (ret != 0) {\n \t\tPMD_INIT_LOG(ERR, \"Couldn't read app_fw_id from fw\");\n \t\tret = -EIO;\n \t\tgoto sym_tbl_cleanup;\n@@ -1080,7 +1078,6 @@ nfp_secondary_init_app_fw_nic(struct rte_pci_device *pci_dev,\n static int\n nfp_pf_secondary_init(struct rte_pci_device *pci_dev)\n {\n-\tint err = 0;\n \tint ret = 0;\n \tstruct nfp_cpp *cpp;\n \tenum nfp_app_fw_id app_fw_id;\n@@ -1124,8 +1121,8 @@ nfp_pf_secondary_init(struct rte_pci_device *pci_dev)\n \t}\n \n \t/* Read the app ID of the firmware loaded */\n-\tapp_fw_id = nfp_rtsym_read_le(sym_tbl, \"_pf0_net_app_id\", &err);\n-\tif (err != 0) {\n+\tapp_fw_id = nfp_rtsym_read_le(sym_tbl, \"_pf0_net_app_id\", &ret);\n+\tif (ret != 0) {\n \t\tPMD_INIT_LOG(ERR, \"Couldn't read app_fw_id from fw\");\n \t\tgoto sym_tbl_cleanup;\n \t}\ndiff --git a/drivers/net/nfp/nfp_ethdev_vf.c b/drivers/net/nfp/nfp_ethdev_vf.c\nindex af0689832a..b6ebbc1ea5 100644\n--- a/drivers/net/nfp/nfp_ethdev_vf.c\n+++ b/drivers/net/nfp/nfp_ethdev_vf.c\n@@ -39,8 +39,6 @@ nfp_netvf_start(struct rte_eth_dev *dev)\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n \n-\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\n \t/* Disabling queues just in case... */\n \tnfp_net_disable_queues(dev);\n \n@@ -54,7 +52,7 @@ nfp_netvf_start(struct rte_eth_dev *dev)\n \t\t\t * Better not to share LSC with RX interrupts.\n \t\t\t * Unregistering LSC interrupt handler\n \t\t\t */\n-\t\t\trte_intr_callback_unregister(pci_dev->intr_handle,\n+\t\t\trte_intr_callback_unregister(intr_handle,\n \t\t\t\t\tnfp_net_dev_interrupt_handler, (void *)dev);\n \n \t\t\tif (dev->data->nb_rx_queues > 1) {\n@@ -77,6 +75,7 @@ nfp_netvf_start(struct rte_eth_dev *dev)\n \tnew_ctrl = nfp_check_offloads(dev);\n \n \t/* Writing configuration parameters in the device */\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tnfp_net_params_setup(hw);\n \n \tdev_conf = &dev->data->dev_conf;\n@@ -244,15 +243,15 @@ static int\n nfp_netvf_init(struct rte_eth_dev *eth_dev)\n {\n \tint err;\n+\tuint16_t port;\n \tuint32_t start_q;\n-\tuint16_t port = 0;\n \tstruct nfp_net_hw *hw;\n \tuint64_t tx_bar_off = 0;\n \tuint64_t rx_bar_off = 0;\n \tstruct rte_pci_device *pci_dev;\n \tconst struct nfp_dev_info *dev_info;\n-\tstruct rte_ether_addr *tmp_ether_addr;\n \n+\tport = eth_dev->data->port_id;\n \tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n \n \tdev_info = nfp_dev_info_get(pci_dev->id.device_id);\n@@ -325,9 +324,7 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \tnfp_netvf_read_mac(hw);\n-\n-\ttmp_ether_addr = &hw->mac_addr;\n-\tif (rte_is_valid_assigned_ether_addr(tmp_ether_addr) == 0) {\n+\tif (rte_is_valid_assigned_ether_addr(&hw->mac_addr) == 0) {\n \t\tPMD_INIT_LOG(INFO, \"Using random mac address for port %hu\", port);\n \t\t/* Using random mac addresses for VFs */\n \t\trte_eth_random_addr(&hw->mac_addr.addr_bytes[0]);\n@@ -344,7 +341,7 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)\n \n \tPMD_INIT_LOG(INFO, \"port %hu VendorID=%#x DeviceID=%#x \"\n \t\t\t\"mac=\" RTE_ETHER_ADDR_PRT_FMT,\n-\t\t\teth_dev->data->port_id, pci_dev->id.vendor_id,\n+\t\t\tport, pci_dev->id.vendor_id,\n \t\t\tpci_dev->id.device_id,\n \t\t\tRTE_ETHER_ADDR_BYTES(&hw->mac_addr));\n \ndiff --git a/drivers/net/nfp/nfp_rxtx.c b/drivers/net/nfp/nfp_rxtx.c\nindex 4632837c0e..e11f617f9a 100644\n--- a/drivers/net/nfp/nfp_rxtx.c\n+++ b/drivers/net/nfp/nfp_rxtx.c\n@@ -284,7 +284,7 @@ nfp_net_parse_chained_meta(uint8_t *meta_base,\n \t\t\tmeta->vlan[meta->vlan_layer].tci =\n \t\t\t\t\tvlan_info & NFP_NET_META_VLAN_MASK;\n \t\t\tmeta->vlan[meta->vlan_layer].tpid = NFP_NET_META_TPID(vlan_info);\n-\t\t\t++meta->vlan_layer;\n+\t\t\tmeta->vlan_layer++;\n \t\t\tbreak;\n \t\tcase NFP_NET_META_IPSEC:\n \t\t\tmeta->sa_idx = rte_be_to_cpu_32(*(rte_be32_t *)meta_offset);\n", "prefixes": [ "10/11" ] }