Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/13218/?format=api
{ "id": 13218, "url": "https://patches.dpdk.org/api/patches/13218/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1465250923-78695-9-git-send-email-stephen.hurd@broadcom.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1465250923-78695-9-git-send-email-stephen.hurd@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1465250923-78695-9-git-send-email-stephen.hurd@broadcom.com", "date": "2016-06-06T22:08:13", "name": "[dpdk-dev,v4,09/39] bnxt: add L2 filter alloc/init/free", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eac9cf3b1fe0bc01cfd00606ce61a9fc67d6609c", "submitter": { "id": 438, "url": "https://patches.dpdk.org/api/people/438/?format=api", "name": "Stephen Hurd", "email": "stephen.hurd@broadcom.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1465250923-78695-9-git-send-email-stephen.hurd@broadcom.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/13218/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/13218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id BF82F6A16;\n\tTue, 7 Jun 2016 00:09:40 +0200 (CEST)", "from mail-gw2-out.broadcom.com (mail-gw2-out.broadcom.com\n\t[216.31.210.63]) by dpdk.org (Postfix) with ESMTP id 8B3505AB8\n\tfor <dev@dpdk.org>; Tue, 7 Jun 2016 00:09:29 +0200 (CEST)", "from mail-irv-18.broadcom.com ([10.15.198.37])\n\tby mail-gw2-out.broadcom.com with ESMTP; 06 Jun 2016 15:28:25 -0700", "from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com\n\t[10.11.16.101])\n\tby mail-irv-18.broadcom.com (Postfix) with ESMTP id 0C54182026;\n\tMon, 6 Jun 2016 15:09:29 -0700 (PDT)", "from DPDK-C1.broadcom.com (dhcp-10-13-115-104.irv.broadcom.com\n\t[10.13.115.104])\n\tby mail-irva-12.broadcom.com (Postfix) with ESMTP id CDA0512762F;\n\tMon, 6 Jun 2016 15:09:26 -0700 (PDT)" ], "X-IronPort-AV": "E=Sophos;i=\"5.26,429,1459839600\"; d=\"scan'208\";a=\"97008497\"", "From": "Stephen Hurd <stephen.hurd@broadcom.com>", "To": "dev@dpdk.org,\n\tajit.khaparde@broadcom.com,\n\tbruce.richardson@intel.com", "Date": "Mon, 6 Jun 2016 15:08:13 -0700", "Message-Id": "<1465250923-78695-9-git-send-email-stephen.hurd@broadcom.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com>", "References": "<1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com>", "Subject": "[dpdk-dev] [PATCH v4 09/39] bnxt: add L2 filter alloc/init/free", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ajit Khaparde <ajit.khaparde@broadcom.com>\n\nAdd the L2 filter structure and the alloc/init/free functions for\ndealing with them.\n\nA filter is used to identify traffic that contains a matching set of\nparameters like unicast or broadcast MAC address or a VLAN tag amongst\nother things which then allows the ASIC to direct the incoming traffic\nto an appropriate VNIC or Rx ring.\n\nv4:\nAddress review comments and fix issues pointed out by checkpatch.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: David Christensen <david.christensen@broadcom.com>\nSigned-off-by: Stephen Hurd <stephen.hurd@broadcom.com>\n---\n drivers/net/bnxt/Makefile | 1 +\n drivers/net/bnxt/bnxt.h | 3 +\n drivers/net/bnxt/bnxt_filter.c | 175 +++++++++++++\n drivers/net/bnxt/bnxt_filter.h | 74 ++++++\n drivers/net/bnxt/bnxt_hwrm.c | 21 ++\n drivers/net/bnxt/bnxt_hwrm.h | 3 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 456 +++++++++++++++++++++++++++++++++\n 7 files changed, 733 insertions(+)\n create mode 100644 drivers/net/bnxt/bnxt_filter.c\n create mode 100644 drivers/net/bnxt/bnxt_filter.h", "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex afd1690..b7834b1 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -50,6 +50,7 @@ EXPORT_MAP := rte_pmd_bnxt_version.map\n #\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_cpr.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_ethdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_filter.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_hwrm.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_ring.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c\ndiff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex bdd355f..49aa38b 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -145,6 +145,9 @@ struct bnxt {\n \tstruct bnxt_vnic_info\t*vnic_info;\n \tSTAILQ_HEAD(, bnxt_vnic_info)\tfree_vnic_list;\n \n+\tstruct bnxt_filter_info\t*filter_info;\n+\tSTAILQ_HEAD(, bnxt_filter_info)\tfree_filter_list;\n+\n \t/* VNIC pointer for flow filter (VMDq) pools */\n #define MAX_FF_POOLS\tETH_64_POOLS\n \tSTAILQ_HEAD(, bnxt_vnic_info)\tff_pool[MAX_FF_POOLS];\ndiff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c\nnew file mode 100644\nindex 0000000..f03a1dc\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_filter.c\n@@ -0,0 +1,175 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <sys/queue.h>\n+\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+\n+#include \"bnxt.h\"\n+#include \"bnxt_filter.h\"\n+#include \"bnxt_hwrm.h\"\n+#include \"bnxt_vnic.h\"\n+#include \"hsi_struct_def_dpdk.h\"\n+\n+/*\n+ * Filter Functions\n+ */\n+\n+struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp)\n+{\n+\tstruct bnxt_filter_info *filter;\n+\n+\t/* Find the 1st unused filter from the free_filter_list pool*/\n+\tfilter = STAILQ_FIRST(&bp->free_filter_list);\n+\tif (!filter) {\n+\t\tRTE_LOG(ERR, PMD, \"No more free filter resources\\n\");\n+\t\treturn NULL;\n+\t}\n+\tSTAILQ_REMOVE_HEAD(&bp->free_filter_list, next);\n+\n+\t/* Default to L2 MAC Addr filter */\n+\tfilter->flags = HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;\n+\tfilter->enables = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |\n+\t\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;\n+\tmemcpy(filter->l2_addr, bp->eth_dev->data->mac_addrs->addr_bytes,\n+\t ETHER_ADDR_LEN);\n+\tmemset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);\n+\treturn filter;\n+}\n+\n+void bnxt_init_filters(struct bnxt *bp)\n+{\n+\tstruct bnxt_filter_info *filter;\n+\tint i, max_filters;\n+\n+\tif (BNXT_PF(bp)) {\n+\t\tstruct bnxt_pf_info *pf = &bp->pf;\n+\n+\t\tmax_filters = pf->max_l2_ctx;\n+\t} else {\n+\t\tstruct bnxt_vf_info *vf = &bp->vf;\n+\n+\t\tmax_filters = vf->max_l2_ctx;\n+\t}\n+\tSTAILQ_INIT(&bp->free_filter_list);\n+\tfor (i = 0; i < max_filters; i++) {\n+\t\tfilter = &bp->filter_info[i];\n+\t\tfilter->fw_l2_filter_id = -1;\n+\t\tSTAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);\n+\t}\n+}\n+\n+void bnxt_free_all_filters(struct bnxt *bp)\n+{\n+\tstruct bnxt_vnic_info *vnic;\n+\tstruct bnxt_filter_info *filter, *temp_filter;\n+\tint i;\n+\n+\tfor (i = 0; i < MAX_FF_POOLS; i++) {\n+\t\tSTAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {\n+\t\t\tfilter = STAILQ_FIRST(&vnic->filter);\n+\t\t\twhile (filter) {\n+\t\t\t\ttemp_filter = STAILQ_NEXT(filter, next);\n+\t\t\t\tSTAILQ_REMOVE(&vnic->filter, filter,\n+\t\t\t\t\t bnxt_filter_info, next);\n+\t\t\t\tSTAILQ_INSERT_TAIL(&bp->free_filter_list,\n+\t\t\t\t\t\t filter, next);\n+\t\t\t\tfilter = temp_filter;\n+\t\t\t}\n+\t\t\tSTAILQ_INIT(&vnic->filter);\n+\t\t}\n+\t}\n+}\n+\n+void bnxt_free_filter_mem(struct bnxt *bp)\n+{\n+\tstruct bnxt_filter_info *filter;\n+\tuint16_t max_filters, i;\n+\tint rc = 0;\n+\n+\t/* Ensure that all filters are freed */\n+\tif (BNXT_PF(bp)) {\n+\t\tstruct bnxt_pf_info *pf = &bp->pf;\n+\n+\t\tmax_filters = pf->max_l2_ctx;\n+\t} else {\n+\t\tstruct bnxt_vf_info *vf = &bp->vf;\n+\n+\t\tmax_filters = vf->max_l2_ctx;\n+\t}\n+\tfor (i = 0; i < max_filters; i++) {\n+\t\tfilter = &bp->filter_info[i];\n+\t\tif (filter->fw_l2_filter_id != ((uint64_t)-1)) {\n+\t\t\tRTE_LOG(ERR, PMD, \"HWRM filter is not freed??\\n\");\n+\t\t\t/* Call HWRM to try to free filter again */\n+\t\t\trc = bnxt_hwrm_clear_filter(bp, filter);\n+\t\t\tif (rc)\n+\t\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t \"HWRM filter cannot be freed rc = %d\\n\",\n+\t\t\t\t\trc);\n+\t\t}\n+\t\tfilter->fw_l2_filter_id = -1;\n+\t}\n+\tSTAILQ_INIT(&bp->free_filter_list);\n+\n+\trte_free(bp->filter_info);\n+\tbp->filter_info = NULL;\n+}\n+\n+int bnxt_alloc_filter_mem(struct bnxt *bp)\n+{\n+\tstruct bnxt_filter_info *filter_mem;\n+\tuint16_t max_filters;\n+\n+\tif (BNXT_PF(bp)) {\n+\t\tstruct bnxt_pf_info *pf = &bp->pf;\n+\n+\t\tmax_filters = pf->max_l2_ctx;\n+\t} else {\n+\t\tstruct bnxt_vf_info *vf = &bp->vf;\n+\n+\t\tmax_filters = vf->max_l2_ctx;\n+\t}\n+\t/* Allocate memory for VNIC pool and filter pool */\n+\tfilter_mem = rte_zmalloc(\"bnxt_filter_info\",\n+\t\t\t\t max_filters * sizeof(struct bnxt_filter_info),\n+\t\t\t\t 0);\n+\tif (filter_mem == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"Failed to alloc memory for %d filters\",\n+\t\t\tmax_filters);\n+\t\treturn -ENOMEM;\n+\t}\n+\tbp->filter_info = filter_mem;\n+\treturn 0;\n+}\ndiff --git a/drivers/net/bnxt/bnxt_filter.h b/drivers/net/bnxt/bnxt_filter.h\nnew file mode 100644\nindex 0000000..06fe134\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_filter.h\n@@ -0,0 +1,74 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _BNXT_FILTER_H_\n+#define _BNXT_FILTER_H_\n+\n+#include <rte_ether.h>\n+\n+struct bnxt;\n+struct bnxt_filter_info {\n+\tSTAILQ_ENTRY(bnxt_filter_info)\tnext;\n+\tuint64_t\t\tfw_l2_filter_id;\n+#define INVALID_MAC_INDEX\t((uint16_t)-1)\n+\tuint16_t\t\tmac_index;\n+\n+\t/* Filter Characteristics */\n+\tuint32_t\t\tflags;\n+\tuint32_t\t\tenables;\n+\tuint8_t\t\t\tl2_addr[ETHER_ADDR_LEN];\n+\tuint8_t\t\t\tl2_addr_mask[ETHER_ADDR_LEN];\n+\tuint16_t\t\tl2_ovlan;\n+\tuint16_t\t\tl2_ovlan_mask;\n+\tuint16_t\t\tl2_ivlan;\n+\tuint16_t\t\tl2_ivlan_mask;\n+\tuint8_t\t\t\tt_l2_addr[ETHER_ADDR_LEN];\n+\tuint8_t\t\t\tt_l2_addr_mask[ETHER_ADDR_LEN];\n+\tuint16_t\t\tt_l2_ovlan;\n+\tuint16_t\t\tt_l2_ovlan_mask;\n+\tuint16_t\t\tt_l2_ivlan;\n+\tuint16_t\t\tt_l2_ivlan_mask;\n+\tuint8_t\t\t\ttunnel_type;\n+\tuint16_t\t\tmirror_vnic_id;\n+\tuint32_t\t\tvni;\n+\tuint8_t\t\t\tpri_hint;\n+\tuint64_t\t\tl2_filter_id_hint;\n+};\n+\n+struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);\n+void bnxt_init_filters(struct bnxt *bp);\n+void bnxt_free_all_filters(struct bnxt *bp);\n+void bnxt_free_filter_mem(struct bnxt *bp);\n+int bnxt_alloc_filter_mem(struct bnxt *bp);\n+\n+#endif\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex f591ead..5d9a991 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -39,6 +39,7 @@\n #include <rte_version.h>\n \n #include \"bnxt.h\"\n+#include \"bnxt_filter.h\"\n #include \"bnxt_hwrm.h\"\n #include \"hsi_struct_def_dpdk.h\"\n \n@@ -135,6 +136,26 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)\n \t\t} \\\n \t}\n \n+int bnxt_hwrm_clear_filter(struct bnxt *bp,\n+\t\t\t struct bnxt_filter_info *filter)\n+{\n+\tint rc = 0;\n+\tstruct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };\n+\tstruct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;\n+\n+\tHWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);\n+\n+\treq.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);\n+\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req));\n+\n+\tHWRM_CHECK_RESULT;\n+\n+\tfilter->fw_l2_filter_id = -1;\n+\n+\treturn 0;\n+}\n+\n int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)\n {\n \tint rc;\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex b792313..c48ba3f 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -41,6 +41,9 @@\n \n #define HWRM_SEQ_ID_INVALID -1U\n \n+int bnxt_hwrm_clear_filter(struct bnxt *bp,\n+\t\t\t struct bnxt_filter_info *filter);\n+\n int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd);\n \n int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 9efb68b..ca42a87 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -253,6 +253,462 @@ struct output {\n \tuint16_t resp_len;\n } __attribute__((packed));\n \n+/* hwrm_cfa_l2_filter_alloc */\n+/*\n+ * A filter is used to identify traffic that contains a matching set of\n+ * parameters like unicast or broadcast MAC address or a VLAN tag amongst\n+ * other things which then allows the ASIC to direct the incoming traffic\n+ * to an appropriate VNIC or Rx ring.\n+ */\n+\n+/* Input (96 bytes) */\n+struct hwrm_cfa_l2_filter_alloc_input {\n+\t/*\n+\t * This value indicates what type of request this is. The format for the\n+\t * rest of the command is determined by this field.\n+\t */\n+\tuint16_t req_type;\n+\n+\t/*\n+\t * This value indicates the what completion ring the request will be\n+\t * optionally completed on. If the value is -1, then no CR completion\n+\t * will be generated. Any other value must be a valid CR ring_id value\n+\t * for this function.\n+\t */\n+\tuint16_t cmpl_ring;\n+\n+\t/* This value indicates the command sequence number. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\n+\t/*\n+\t * This is the host address where the response will be written when the\n+\t * request is complete. This area must be 16B aligned and must be\n+\t * cleared to zero before the request is made.\n+\t */\n+\tuint64_t resp_addr;\n+\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource. This\n+\t * enumeration is used for resources that are similar for both TX and RX\n+\t * paths of the chip.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \\\n+\t\t\t\t\t\t\tUINT32_C(0x1)\n+\t\t/* tx path */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \\\n+\t\t\t\t\t\t\t(UINT32_C(0x0) << 0)\n+\t\t/* rx path */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 0)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \\\n+\t\t\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX\n+\t/*\n+\t * Setting of this flag indicates the applicability to the loopback\n+\t * path.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n+\t\t\t\t\t\t\tUINT32_C(0x2)\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n+\t\t\t\t\t\t\tUINT32_C(0x4)\n+\t/*\n+\t * If this flag is set, all t_l2_* fields are invalid and they should\n+\t * not be specified. If this flag is set, then l2_* fields refer to\n+\t * fields of outermost L2 header.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \\\n+\t\t\t\t\t\t\tUINT32_C(0x8)\n+\tuint32_t flags;\n+\n+\t/* This bit must be '1' for the l2_addr field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n+\t\t\t\t\t\t\tUINT32_C(0x1)\n+\t/* This bit must be '1' for the l2_addr_mask field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x2)\n+\t/* This bit must be '1' for the l2_ovlan field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \\\n+\t\t\t\t\t\t\tUINT32_C(0x4)\n+\t/* This bit must be '1' for the l2_ovlan_mask field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x8)\n+\t/* This bit must be '1' for the l2_ivlan field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n+\t\t\t\t\t\t\tUINT32_C(0x10)\n+\t/* This bit must be '1' for the l2_ivlan_mask field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x20)\n+\t/* This bit must be '1' for the t_l2_addr field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \\\n+\t\t\t\t\t\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the t_l2_addr_mask field to be configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x80)\n+\t/* This bit must be '1' for the t_l2_ovlan field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \\\n+\t\t\t\t\t\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ovlan_mask field to be configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x200)\n+\t/* This bit must be '1' for the t_l2_ivlan field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \\\n+\t\t\t\t\t\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ivlan_mask field to be configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \\\n+\t\t\t\t\t\t\tUINT32_C(0x800)\n+\t/* This bit must be '1' for the src_type field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \\\n+\t\t\t\t\t\t\tUINT32_C(0x1000)\n+\t/* This bit must be '1' for the src_id field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \\\n+\t\t\t\t\t\t\tUINT32_C(0x2000)\n+\t/* This bit must be '1' for the tunnel_type field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\t\t\t\t\t\tUINT32_C(0x4000)\n+\t/* This bit must be '1' for the dst_id field to be configured. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t\t\t\t\t\t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\t\t\t\t\t\tUINT32_C(0x10000)\n+\tuint32_t enables;\n+\n+\t/*\n+\t * This value sets the match value for the L2 MAC address. Destination\n+\t * MAC address for RX path. Source MAC address for TX path.\n+\t */\n+\tuint8_t l2_addr[6];\n+\n+\tuint8_t unused_0;\n+\tuint8_t unused_1;\n+\n+\t/*\n+\t * This value sets the mask value for the L2 address. A value of 0 will\n+\t * mask the corresponding bit from compare.\n+\t */\n+\tuint8_t l2_addr_mask[6];\n+\n+\t/* This value sets VLAN ID value for outer VLAN. */\n+\tuint16_t l2_ovlan;\n+\n+\t/*\n+\t * This value sets the mask value for the ovlan id. A value of 0 will\n+\t * mask the corresponding bit from compare.\n+\t */\n+\tuint16_t l2_ovlan_mask;\n+\n+\t/* This value sets VLAN ID value for inner VLAN. */\n+\tuint16_t l2_ivlan;\n+\n+\t/*\n+\t * This value sets the mask value for the ivlan id. A value of 0 will\n+\t * mask the corresponding bit from compare.\n+\t */\n+\tuint16_t l2_ivlan_mask;\n+\n+\tuint8_t unused_2;\n+\tuint8_t unused_3;\n+\n+\t/*\n+\t * This value sets the match value for the tunnel L2 MAC address.\n+\t * Destination MAC address for RX path. Source MAC address for TX path.\n+\t */\n+\tuint8_t t_l2_addr[6];\n+\n+\tuint8_t unused_4;\n+\tuint8_t unused_5;\n+\n+\t/*\n+\t * This value sets the mask value for the tunnel L2 address. A value of\n+\t * 0 will mask the corresponding bit from compare.\n+\t */\n+\tuint8_t t_l2_addr_mask[6];\n+\n+\t/* This value sets VLAN ID value for tunnel outer VLAN. */\n+\tuint16_t t_l2_ovlan;\n+\n+\t/*\n+\t * This value sets the mask value for the tunnel ovlan id. A value of 0\n+\t * will mask the corresponding bit from compare.\n+\t */\n+\tuint16_t t_l2_ovlan_mask;\n+\n+\t/* This value sets VLAN ID value for tunnel inner VLAN. */\n+\tuint16_t t_l2_ivlan;\n+\n+\t/*\n+\t * This value sets the mask value for the tunnel ivlan id. A value of 0\n+\t * will mask the corresponding bit from compare.\n+\t */\n+\tuint16_t t_l2_ivlan_mask;\n+\n+\t/* This value identifies the type of source of the packet. */\n+\t\t/* Network port */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \\\n+\t\t\t\t\t\t\t(UINT32_C(0x0) << 0)\n+\t\t/* Physical function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 0)\n+\t\t/* Virtual function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 0)\n+\t\t/* Virtual NIC of a function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \\\n+\t\t\t\t\t\t\t(UINT32_C(0x3) << 0)\n+\t\t/* Embedded processor for CFA management */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \\\n+\t\t\t\t\t\t\t(UINT32_C(0x4) << 0)\n+\t\t/* Embedded processor for OOB management */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \\\n+\t\t\t\t\t\t\t(UINT32_C(0x5) << 0)\n+\t\t/* Embedded processor for RoCE */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \\\n+\t\t\t\t\t\t\t(UINT32_C(0x6) << 0)\n+\t\t/* Embedded processor for network proxy functions */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \\\n+\t\t\t\t\t\t\t(UINT32_C(0x7) << 0)\n+\tuint8_t src_type;\n+\n+\tuint8_t unused_6;\n+\t/*\n+\t * This value is the id of the source. For a network port, it represents\n+\t * port_id. For a physical function, it represents fid. For a virtual\n+\t * function, it represents vf_id. For a vnic, it represents vnic_id. For\n+\t * embedded processors, this id is not valid. Notes: 1. The function ID\n+\t * is implied if it src_id is not provided for a src_type that is either\n+\t */\n+\tuint32_t src_id;\n+\n+\t/* Tunnel Type. */\n+\t\t/* Non-tunnel */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\t\t\t\t\t\t(UINT32_C(0x0) << 0)\n+\t\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 0)\n+\t\t/*\n+\t\t * Network Virtualization Generic Routing Encapsulation (NVGRE)\n+\t\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 0)\n+\t\t/*\n+\t\t * Generic Routing Encapsulation (GRE) inside Ethernet payload\n+\t\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\t\t\t\t\t\t(UINT32_C(0x3) << 0)\n+\t\t/* IP in IP */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\t\t\t\t\t\t(UINT32_C(0x4) << 0)\n+\t\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\t\t\t\t\t\t(UINT32_C(0x5) << 0)\n+\t\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\t\t\t\t\t\t(UINT32_C(0x6) << 0)\n+\t\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\t\t\t\t\t\t(UINT32_C(0x7) << 0)\n+\t\t/*\n+\t\t * Generic Routing Encapsulation (GRE) inside IP datagram\n+\t\t * payload\n+\t\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\t\t\t\t\t\t(UINT32_C(0x8) << 0)\n+\t\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\t\t\t\t\t\t(UINT32_C(0xff) << 0)\n+\tuint8_t tunnel_type;\n+\n+\tuint8_t unused_7;\n+\n+\t/*\n+\t * If set, this value shall represent the Logical VNIC ID of the\n+\t * destination VNIC for the RX path and network port id of the\n+\t * destination port for the TX path.\n+\t */\n+\tuint16_t dst_id;\n+\n+\t/* Logical VNIC ID of the VNIC where traffic is mirrored. */\n+\tuint16_t mirror_vnic_id;\n+\n+\t/*\n+\t * This hint is provided to help in placing the filter in the filter\n+\t * table.\n+\t */\n+\t\t/* No preference */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \\\n+\t\t\t\t\t\t\t(UINT32_C(0x0) << 0)\n+\t\t/* Above the given filter */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 0)\n+\t\t/* Below the given filter */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 0)\n+\t\t/* As high as possible */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \\\n+\t\t\t\t\t\t\t(UINT32_C(0x3) << 0)\n+\t\t/* As low as possible */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x4) << 0)\n+\tuint8_t pri_hint;\n+\n+\tuint8_t unused_8;\n+\tuint32_t unused_9;\n+\n+\t/*\n+\t * This is the ID of the filter that goes along with the pri_hint. This\n+\t * field is valid only for the following values. 1 - Above the given\n+\t * filter 2 - Below the given filter\n+\t */\n+\tuint64_t l2_filter_id_hint;\n+} __attribute__((packed));\n+\n+/* Output (24 bytes) */\n+struct hwrm_cfa_l2_filter_alloc_output {\n+\t/*\n+\t * Pass/Fail or error type Note: receiver to verify the in parameters,\n+\t * and fail the call with an error when appropriate\n+\t */\n+\tuint16_t error_code;\n+\n+\t/* This field returns the type of original request. */\n+\tuint16_t req_type;\n+\n+\t/* This field provides original sequence number of the command. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * This field is the length of the response in bytes. The last byte of\n+\t * the response is a valid flag that will read as '1' when the command\n+\t * has been completely written to memory.\n+\t */\n+\tuint16_t resp_len;\n+\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n+\t */\n+\tuint64_t l2_filter_id;\n+\n+\t/*\n+\t * This is the ID of the flow associated with this filter. This value\n+\t * shall be used to match and associate the flow identifier returned in\n+\t * completion records. A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t flow_id;\n+\n+\tuint8_t unused_0;\n+\tuint8_t unused_1;\n+\tuint8_t unused_2;\n+\n+\t/*\n+\t * This field is used in Output records to indicate that the output is\n+\t * completely written to RAM. This field should be read as '1' to\n+\t * indicate that the output has been completely written. When writing a\n+\t * command completion or response to an internal processor, the order of\n+\t * writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_l2_filter_free */\n+/*\n+ * Description: Free a L2 filter. The HWRM shall free all associated filter\n+ * resources with the L2 filter.\n+ */\n+\n+/* Input (24 bytes) */\n+struct hwrm_cfa_l2_filter_free_input {\n+\t/*\n+\t * This value indicates what type of request this is. The format for the\n+\t * rest of the command is determined by this field.\n+\t */\n+\tuint16_t req_type;\n+\n+\t/*\n+\t * This value indicates the what completion ring the request will be\n+\t * optionally completed on. If the value is -1, then no CR completion\n+\t * will be generated. Any other value must be a valid CR ring_id value\n+\t * for this function.\n+\t */\n+\tuint16_t cmpl_ring;\n+\n+\t/* This value indicates the command sequence number. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids\n+\t * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\n+\t/*\n+\t * This is the host address where the response will be written when the\n+\t * request is complete. This area must be 16B aligned and must be\n+\t * cleared to zero before the request is made.\n+\t */\n+\tuint64_t resp_addr;\n+\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n+\t */\n+\tuint64_t l2_filter_id;\n+} __attribute__((packed));\n+\n+/* Output (16 bytes) */\n+struct hwrm_cfa_l2_filter_free_output {\n+\t/*\n+\t * Pass/Fail or error type Note: receiver to verify the in parameters,\n+\t * and fail the call with an error when appropriate\n+\t */\n+\tuint16_t error_code;\n+\n+\t/* This field returns the type of original request. */\n+\tuint16_t req_type;\n+\n+\t/* This field provides original sequence number of the command. */\n+\tuint16_t seq_id;\n+\n+\t/*\n+\t * This field is the length of the response in bytes. The last byte of\n+\t * the response is a valid flag that will read as '1' when the command\n+\t * has been completely written to memory.\n+\t */\n+\tuint16_t resp_len;\n+\n+\tuint32_t unused_0;\n+\tuint8_t unused_1;\n+\tuint8_t unused_2;\n+\tuint8_t unused_3;\n+\n+\t/*\n+\t * This field is used in Output records to indicate that the output is\n+\t * completely written to RAM. This field should be read as '1' to\n+\t * indicate that the output has been completely written. When writing a\n+\t * command completion or response to an internal processor, the order of\n+\t * writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __attribute__((packed));\n+\n /* hwrm_exec_fwd_resp */\n /*\n * Description: This command is used to send an encapsulated request to the\n", "prefixes": [ "dpdk-dev", "v4", "09/39" ] }