Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/131631/?format=api
{ "id": 131631, "url": "https://patches.dpdk.org/api/patches/131631/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230919134222.2500033-6-amitprakashs@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230919134222.2500033-6-amitprakashs@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230919134222.2500033-6-amitprakashs@marvell.com", "date": "2023-09-19T13:42:21", "name": "[v1,6/7] dma/cnxk: support for DMA event enqueue dequeue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1fcfc226944672a9399ceb99d62740cf125e1188", "submitter": { "id": 2699, "url": "https://patches.dpdk.org/api/people/2699/?format=api", "name": "Amit Prakash Shukla", "email": "amitprakashs@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230919134222.2500033-6-amitprakashs@marvell.com/mbox/", "series": [ { "id": 29553, "url": "https://patches.dpdk.org/api/series/29553/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29553", "date": "2023-09-19T13:42:16", "name": "[v1,1/7] eventdev: introduce DMA event adapter library", "version": 1, "mbox": "https://patches.dpdk.org/series/29553/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131631/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83F4F42604;\n\tTue, 19 Sep 2023 15:43:27 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B3B0540E2D;\n\tTue, 19 Sep 2023 15:43:16 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 239B040E6E\n for <dev@dpdk.org>; Tue, 19 Sep 2023 15:43:14 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 38JDZvc1011940; Tue, 19 Sep 2023 06:43:14 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3t7cnq00wy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 19 Sep 2023 06:43:14 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 19 Sep 2023 06:43:12 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 19 Sep 2023 06:43:12 -0700", "from localhost.localdomain (unknown [10.28.36.157])\n by maili.marvell.com (Postfix) with ESMTP id 27D863F709B;\n Tue, 19 Sep 2023 06:43:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=UQ5OLJG+K3OGY1Hx0LmY5Cc2PvqPDowe2DWwBrgXQMs=;\n b=B5CMC9RX+DcjhOf98gzdS/DB/nlxKP22YdYizKALYCq68yfSBr5TuZjBMa9ryrIRqj0n\n q9FsX+drjMG9TLdjvpSr9ElvfpzQ1zoMUvaZdnq1EqO+Gq1q5AR9zktBFUWyImAXiVI4\n 9SjI89+az+L+D5lUy+phI8CL8Qvs1PyGhXQ1naS0YQtQDSR/rDbvdQJ9O6hmzIaGYij+\n cmngA4nK1+/0YRLxfi+GPJRtE4FKw8ZfWhkNLmTz/OzHl8PNUfo0tW29d7/Pup6T76lV\n JmpLCrBDHVBest/YTbwmZLTx8BZirVXRGEU4QP+y3T5+WhLyFzjyf2OwpD+6af1yUXW7 yw==", "From": "Amit Prakash Shukla <amitprakashs@marvell.com>", "To": "Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <fengchengwen@huawei.com>,\n <kevin.laatz@intel.com>, <bruce.richardson@intel.com>,\n <conor.walsh@intel.com>, <g.singh@nxp.com>,\n <sachin.saxena@oss.nxp.com>, <hemant.agrawal@nxp.com>,\n <cheng1.jiang@intel.com>, <ndabilpuram@marvell.com>,\n <anoobj@marvell.com>, <mb@smartsharesystems.com>,\n Amit Prakash Shukla <amitprakashs@marvell.com>", "Subject": "[PATCH v1 6/7] dma/cnxk: support for DMA event enqueue dequeue", "Date": "Tue, 19 Sep 2023 19:12:21 +0530", "Message-ID": "<20230919134222.2500033-6-amitprakashs@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230919134222.2500033-1-amitprakashs@marvell.com>", "References": "<20230919134222.2500033-1-amitprakashs@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "CRoc0BnV0j6ASP-iYdV_J5Bn--kP98c4", "X-Proofpoint-GUID": "CRoc0BnV0j6ASP-iYdV_J5Bn--kP98c4", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26\n definitions=2023-09-19_06,2023-09-19_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added cnxk driver support for dma event enqueue and dequeue.\n\nSigned-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>\n---\n drivers/dma/cnxk/cnxk_dma_event_dp.h | 22 +++\n drivers/dma/cnxk/cnxk_dmadev.h | 9 +-\n drivers/dma/cnxk/cnxk_dmadev_fp.c | 209 +++++++++++++++++++++++++++\n drivers/dma/cnxk/meson.build | 6 +-\n drivers/dma/cnxk/version.map | 9 ++\n 5 files changed, 253 insertions(+), 2 deletions(-)\n create mode 100644 drivers/dma/cnxk/cnxk_dma_event_dp.h\n create mode 100644 drivers/dma/cnxk/version.map", "diff": "diff --git a/drivers/dma/cnxk/cnxk_dma_event_dp.h b/drivers/dma/cnxk/cnxk_dma_event_dp.h\nnew file mode 100644\nindex 0000000000..bf9b01f8f1\n--- /dev/null\n+++ b/drivers/dma/cnxk/cnxk_dma_event_dp.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#ifndef _CNXK_DMA_EVENT_DP_H_\n+#define _CNXK_DMA_EVENT_DP_H_\n+\n+#include <stdint.h>\n+\n+#include <rte_common.h>\n+#include <rte_eventdev.h>\n+\n+__rte_internal\n+uint16_t cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events);\n+\n+__rte_internal\n+uint16_t cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events);\n+\n+__rte_internal\n+uintptr_t cnxk_dma_adapter_dequeue(uintptr_t get_work1);\n+\n+#endif /* _CNXK_DMA_EVENT_DP_H_ */\ndiff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h\nindex 75059b8843..9cba388d02 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.h\n+++ b/drivers/dma/cnxk/cnxk_dmadev.h\n@@ -40,6 +40,11 @@\n */\n #define CNXK_DPI_REQ_CDATA 0xFF\n \n+/* Set Completion data to 0xDEADBEEF when request submitted for SSO.\n+ * This helps differentiate if the dequeue is called after cnxk enueue.\n+ */\n+#define CNXK_DPI_REQ_SSO_CDATA 0xDEADBEEF\n+\n union cnxk_dpi_instr_cmd {\n \tuint64_t u;\n \tstruct cn9k_dpi_instr_cmd {\n@@ -85,7 +90,9 @@ union cnxk_dpi_instr_cmd {\n \n struct cnxk_dpi_compl_s {\n \tuint64_t cdata;\n-\tvoid *cb_data;\n+\tvoid *op;\n+\tuint16_t dev_id;\n+\tuint16_t vchan;\n \tuint32_t wqecs;\n };\n \ndiff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c b/drivers/dma/cnxk/cnxk_dmadev_fp.c\nindex 16d7b5426b..c7cd036a5b 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev_fp.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c\n@@ -5,6 +5,8 @@\n #include <rte_vect.h>\n \n #include \"cnxk_dmadev.h\"\n+#include \"cnxk_dma_event_dp.h\"\n+#include <rte_event_dma_adapter.h>\n \n static __plt_always_inline void\n __dpi_cpy_scalar(uint64_t *src, uint64_t *dst, uint8_t n)\n@@ -434,3 +436,210 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \n \treturn dpi_conf->desc_idx++;\n }\n+\n+uint16_t\n+cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tunion rte_event_dma_metadata *dma_mdata;\n+\tstruct rte_event_dma_request *req_info;\n+\tconst struct rte_dma_sge *src, *dst;\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\tstruct rte_event *rsp_info;\n+\tuint16_t nb_src, nb_dst;\n+\tstruct rte_dma_dev *dev;\n+\tuint64_t hdr[4];\n+\tuint16_t count;\n+\tint rc;\n+\n+\tPLT_SET_USED(ws);\n+\n+\tfor (count = 0; count < nb_events; count++) {\n+\t\top = ev[count].event_ptr;\n+\t\tdma_mdata = (union rte_event_dma_metadata *)((uint8_t *)op +\n+\t\t\t sizeof(struct rte_event_dma_adapter_op));\n+\t\trsp_info = &dma_mdata->response_info;\n+\t\treq_info = &dma_mdata->request_info;\n+\t\tdev = rte_dma_pmd_dev_get(req_info->dma_dev_id);\n+\t\tdpivf = dev->data->dev_private;\n+\t\tdpi_conf = &dpivf->conf[req_info->vchan];\n+\n+\t\tif (unlikely(((dpi_conf->c_desc.tail + 1) & dpi_conf->c_desc.max_cnt) ==\n+\t\t\t dpi_conf->c_desc.head))\n+\t\t\treturn count;\n+\n+\t\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\t\tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n+\t\tcomp_ptr->op = op;\n+\t\tcomp_ptr->dev_id = req_info->dma_dev_id;\n+\t\tcomp_ptr->vchan = req_info->vchan;\n+\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n+\n+\t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n+\t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n+\n+\t\thdr[0] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 54);\n+\t\thdr[0] |= (nb_dst << 6) | nb_src;\n+\t\thdr[1] = ((uint64_t)comp_ptr);\n+\t\thdr[2] = (RTE_EVENT_TYPE_DMADEV << 28 | (rsp_info->sub_event_type << 20) |\n+\t\t\t rsp_info->flow_id);\n+\t\thdr[2] |= ((uint64_t)(rsp_info->sched_type & DPI_HDR_TT_MASK)) << 32;\n+\t\thdr[2] |= ((uint64_t)(rsp_info->queue_id & DPI_HDR_GRP_MASK)) << 34;\n+\n+\t\tsrc = &op->src_seg[0];\n+\t\tdst = &op->dst_seg[0];\n+\n+\t\trc = __dpi_queue_write_sg(dpivf, hdr, src, dst, nb_src, nb_dst);\n+\t\tif (unlikely(rc)) {\n+\t\t\tCNXK_DPI_STRM_DEC(dpi_conf->c_desc, tail);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (op->flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\t\trte_wmb();\n+\t\t\tplt_write64(dpi_conf->pnum_words + CNXK_DPI_CMD_LEN(nb_src, nb_dst),\n+\t\t\t\t dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\t\t\tdpi_conf->stats.submitted += dpi_conf->pending + 1;\n+\t\t\tdpi_conf->pnum_words = 0;\n+\t\t\tdpi_conf->pending = 0;\n+\t\t} else {\n+\t\t\tdpi_conf->pnum_words += CNXK_DPI_CMD_LEN(nb_src, nb_dst);\n+\t\t\tdpi_conf->pending++;\n+\t\t}\n+\t}\n+\n+\treturn count;\n+}\n+\n+uint16_t\n+cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tunion rte_event_dma_metadata *dma_mdata;\n+\tstruct rte_event_dma_request *req_info;\n+\tconst struct rte_dma_sge *fptr, *lptr;\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\tstruct rte_event *rsp_info;\n+\tuint16_t nb_src, nb_dst;\n+\tstruct rte_dma_dev *dev;\n+\tuint64_t hdr[4];\n+\tuint16_t count;\n+\tint rc;\n+\n+\tPLT_SET_USED(ws);\n+\n+\tfor (count = 0; count < nb_events; count++) {\n+\t\top = ev[count].event_ptr;\n+\t\tdma_mdata = (union rte_event_dma_metadata *)((uint8_t *)op +\n+\t\t\t sizeof(struct rte_event_dma_adapter_op));\n+\t\trsp_info = &dma_mdata->response_info;\n+\t\treq_info = &dma_mdata->request_info;\n+\t\tdev = rte_dma_pmd_dev_get(req_info->dma_dev_id);\n+\t\tdpivf = dev->data->dev_private;\n+\t\tdpi_conf = &dpivf->conf[req_info->vchan];\n+\n+\t\tif (unlikely(((dpi_conf->c_desc.tail + 1) & dpi_conf->c_desc.max_cnt) ==\n+\t\t\t dpi_conf->c_desc.head))\n+\t\t\treturn count;\n+\n+\t\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\t\tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n+\t\tcomp_ptr->op = op;\n+\t\tcomp_ptr->dev_id = req_info->dma_dev_id;\n+\t\tcomp_ptr->vchan = req_info->vchan;\n+\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n+\n+\t\thdr[1] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 36);\n+\t\thdr[2] = (uint64_t)comp_ptr;\n+\n+\t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n+\t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n+\t\t/*\n+\t\t * For inbound case, src pointers are last pointers.\n+\t\t * For all other cases, src pointers are first pointers.\n+\t\t */\n+\t\tif (((dpi_conf->cmd.u >> 48) & DPI_HDR_XTYPE_MASK) == DPI_XTYPE_INBOUND) {\n+\t\t\tfptr = &op->dst_seg[0];\n+\t\t\tlptr = &op->src_seg[0];\n+\t\t\tRTE_SWAP(nb_src, nb_dst);\n+\t\t} else {\n+\t\t\tfptr = &op->src_seg[0];\n+\t\t\tlptr = &op->dst_seg[0];\n+\t\t}\n+\n+\t\thdr[0] = ((uint64_t)nb_dst << 54) | (uint64_t)nb_src << 48;\n+\t\thdr[0] |= (RTE_EVENT_TYPE_DMADEV << 28 | (rsp_info->sub_event_type << 20) |\n+\t\t\t rsp_info->flow_id);\n+\t\thdr[0] |= ((uint64_t)(rsp_info->sched_type & DPI_HDR_TT_MASK)) << 32;\n+\t\thdr[0] |= ((uint64_t)(rsp_info->queue_id & DPI_HDR_GRP_MASK)) << 34;\n+\n+\t\trc = __dpi_queue_write_sg(dpivf, hdr, fptr, lptr, nb_src, nb_dst);\n+\t\tif (unlikely(rc)) {\n+\t\t\tCNXK_DPI_STRM_DEC(dpi_conf->c_desc, tail);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (op->flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\t\trte_wmb();\n+\t\t\tplt_write64(dpi_conf->pnum_words + CNXK_DPI_CMD_LEN(nb_src, nb_dst),\n+\t\t\t\t dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\t\t\tdpi_conf->stats.submitted += dpi_conf->pending + 1;\n+\t\t\tdpi_conf->pnum_words = 0;\n+\t\t\tdpi_conf->pending = 0;\n+\t\t} else {\n+\t\t\tdpi_conf->pnum_words += CNXK_DPI_CMD_LEN(nb_src, nb_dst);\n+\t\t\tdpi_conf->pending++;\n+\t\t}\n+\t}\n+\n+\treturn count;\n+}\n+\n+uintptr_t\n+cnxk_dma_adapter_dequeue(uintptr_t get_work1)\n+{\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\tstruct rte_dma_dev *dev;\n+\tuint8_t *wqecs;\n+\n+\tcomp_ptr = (struct cnxk_dpi_compl_s *)get_work1;\n+\n+\t/* Dequeue can be called without calling cnx_enqueue in case of\n+\t * dma_adapter. When its called from adapter, dma op will not be\n+\t * embedded in completion pointer. In those cases return op.\n+\t */\n+\tif (comp_ptr->cdata != CNXK_DPI_REQ_SSO_CDATA)\n+\t\treturn (uintptr_t)comp_ptr;\n+\n+\tdev = rte_dma_pmd_dev_get(comp_ptr->dev_id);\n+\tdpivf = dev->data->dev_private;\n+\tdpi_conf = &dpivf->conf[comp_ptr->vchan];\n+\n+\twqecs = (uint8_t *)&comp_ptr->wqecs;\n+\tif (__atomic_load_n(wqecs, __ATOMIC_RELAXED) != 0)\n+\t\tdpi_conf->stats.errors++;\n+\n+\top = (struct rte_event_dma_adapter_op *)comp_ptr->op;\n+\n+\t/* We are done here. Reset completion buffer.*/\n+\tcomp_ptr->wqecs = ~0;\n+\tcomp_ptr->op = NULL;\n+\tcomp_ptr->dev_id = ~0;\n+\tcomp_ptr->vchan = ~0;\n+\tcomp_ptr->cdata = CNXK_DPI_REQ_CDATA;\n+\n+\tCNXK_DPI_STRM_INC(dpi_conf->c_desc, head);\n+\t/* Take into account errors also. This is similar to\n+\t * cnxk_dmadev_completed_status().\n+\t */\n+\tdpi_conf->stats.completed++;\n+\n+\treturn (uintptr_t)op;\n+}\ndiff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build\nindex e557349368..9cf5453b0b 100644\n--- a/drivers/dma/cnxk/meson.build\n+++ b/drivers/dma/cnxk/meson.build\n@@ -8,6 +8,10 @@ foreach flag: error_cflags\n endif\n endforeach\n \n-deps += ['bus_pci', 'common_cnxk', 'dmadev']\n+driver_sdk_headers = files(\n+ 'cnxk_dma_event_dp.h',\n+)\n+\n+deps += ['bus_pci', 'common_cnxk', 'dmadev', 'eventdev']\n sources = files('cnxk_dmadev.c', 'cnxk_dmadev_fp.c')\n require_iova_in_mbuf = false\ndiff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map\nnew file mode 100644\nindex 0000000000..6cc1c6aaa5\n--- /dev/null\n+++ b/drivers/dma/cnxk/version.map\n@@ -0,0 +1,9 @@\n+INTERNAL {\n+\tglobal:\n+\n+\tcn10k_dma_adapter_enqueue;\n+\tcn9k_dma_adapter_enqueue;\n+\tcnxk_dma_adapter_dequeue;\n+\n+\tlocal: *;\n+};\n", "prefixes": [ "v1", "6/7" ] }