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{
    "id": 131576,
    "url": "https://patches.dpdk.org/api/patches/131576/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230918163114.276722-3-hernan.vargas@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230918163114.276722-3-hernan.vargas@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230918163114.276722-3-hernan.vargas@intel.com",
    "date": "2023-09-18T16:31:12",
    "name": "[v3,2/4] baseband/fpga_5gnr_fec: add Vista Creek variant",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0bed7fc107c5501277fa3556bba166a7aa268f02",
    "submitter": {
        "id": 2659,
        "url": "https://patches.dpdk.org/api/people/2659/?format=api",
        "name": "Hernan Vargas",
        "email": "hernan.vargas@intel.com"
    },
    "delegate": {
        "id": 2642,
        "url": "https://patches.dpdk.org/api/users/2642/?format=api",
        "username": "mcoquelin",
        "first_name": "Maxime",
        "last_name": "Coquelin",
        "email": "maxime.coquelin@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230918163114.276722-3-hernan.vargas@intel.com/mbox/",
    "series": [
        {
            "id": 29537,
            "url": "https://patches.dpdk.org/api/series/29537/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29537",
            "date": "2023-09-18T16:31:10",
            "name": "changes for 23.11",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/29537/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/131576/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/131576/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 29D66425DD;\n\tMon, 18 Sep 2023 18:32:19 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 551C540A6D;\n\tMon, 18 Sep 2023 18:32:05 +0200 (CEST)",
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        ],
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        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10837\"; a=\"382451792\"",
            "E=Sophos;i=\"6.02,156,1688454000\"; d=\"scan'208\";a=\"382451792\"",
            "E=McAfee;i=\"6600,9927,10837\"; a=\"1076645892\"",
            "E=Sophos;i=\"6.02,156,1688454000\"; d=\"scan'208\";a=\"1076645892\""
        ],
        "X-ExtLoop1": "1",
        "From": "Hernan Vargas <hernan.vargas@intel.com>",
        "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com",
        "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>",
        "Subject": "[PATCH v3 2/4] baseband/fpga_5gnr_fec: add Vista Creek variant",
        "Date": "Mon, 18 Sep 2023 09:31:12 -0700",
        "Message-Id": "<20230918163114.276722-3-hernan.vargas@intel.com>",
        "X-Mailer": "git-send-email 2.37.1",
        "In-Reply-To": "<20230918163114.276722-1-hernan.vargas@intel.com>",
        "References": "<20230918163114.276722-1-hernan.vargas@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Create a new file vc_5gnr_pmd.h to store structures and macros specific\nto Vista Creek 5G FPGA implementation and rename functions specific to\nthe Vista Creek variant.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h    | 183 +-----\n .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c         | 531 +++++++++---------\n drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h  | 140 +++++\n 3 files changed, 426 insertions(+), 428 deletions(-)\n create mode 100644 drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h",
    "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\nindex 9300349a731b..982e956dc819 100644\n--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h\n@@ -8,6 +8,8 @@\n #include <stdint.h>\n #include <stdbool.h>\n \n+#include \"vc_5gnr_pmd.h\"\n+\n /* Helper macro for logging */\n #define rte_bbdev_log(level, fmt, ...) \\\n \trte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt \"\\n\", \\\n@@ -25,32 +27,20 @@\n #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf\n #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf\n \n-/* FPGA 5GNR FEC PCI vendor & device IDs */\n-#define FPGA_5GNR_FEC_VENDOR_ID (0x8086)\n-#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)\n-#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)\n-\n-/* Align DMA descriptors to 256 bytes - cache-aligned */\n-#define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8)\n-/* Ring size is in 256 bits (32 bytes) units */\n-#define FPGA_RING_DESC_LEN_UNIT_BYTES (32)\n-/* Maximum size of queue */\n-#define FPGA_5GNR_RING_MAX_SIZE (1024)\n-\n-#define FPGA_NUM_UL_QUEUES (32)\n-#define FPGA_NUM_DL_QUEUES (32)\n-#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)\n-#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)\n-\n #define FPGA_5GNR_INVALID_HW_QUEUE_ID (0xFFFFFFFF)\n-\n #define FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US (1000)\n #define FPGA_5GNR_HARQ_RDY_TIMEOUT (10)\n #define FPGA_5GNR_TIMEOUT_CHECK_INTERVAL (5)\n #define FPGA_5GNR_DDR_OVERFLOW (0x10)\n-\n #define FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES 8\n #define FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES 8\n+/* Align DMA descriptors to 256 bytes - cache-aligned. */\n+#define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8)\n+/* Maximum size of queue. */\n+#define FPGA_5GNR_RING_MAX_SIZE (1024)\n+\n+#define VC_5GNR_FPGA_VARIANT\t0\n+#define AGX100_FPGA_VARIANT\t1\n \n /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */\n #define N_ZC_1 66 /* N = 66 Zc for BG 1 */\n@@ -62,32 +52,7 @@\n #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */\n #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */\n \n-/* FPGA 5GNR FEC Register mapping on BAR0 */\n-enum {\n-\tFPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */\n-\tFPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */\n-\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */\n-\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */\n-\tFPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */\n-\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */\n-\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */\n-\tFPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */\n-\tFPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */\n-\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */\n-\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */\n-\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */\n-\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */\n-\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */\n-\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */\n-\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */\n-\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /* len: 4B */\n-\tFPGA_5GNR_FEC_MUTEX = 0x00000A60, /* len: 4B */\n-\tFPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68  /* len: 4B */\n-};\n-\n-/* FPGA 5GNR FEC Ring Control Registers */\n+/* FPGA 5GNR Ring Control Registers. */\n enum {\n \tFPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,\n \tFPGA_5GNR_FEC_RING_SIZE = 0x00000010,\n@@ -98,113 +63,27 @@ enum {\n \tFPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C\n };\n \n-/* FPGA 5GNR FEC DESCRIPTOR ERROR */\n+/* VC 5GNR and AGX100 common register mapping on BAR0. */\n enum {\n-\tDESC_ERR_NO_ERR = 0x0,\n-\tDESC_ERR_K_P_OUT_OF_RANGE = 0x1,\n-\tDESC_ERR_Z_C_NOT_LEGAL = 0x2,\n-\tDESC_ERR_DESC_OFFSET_ERR = 0x3,\n-\tDESC_ERR_DESC_READ_FAIL = 0x8,\n-\tDESC_ERR_DESC_READ_TIMEOUT = 0x9,\n-\tDESC_ERR_DESC_READ_TLP_POISONED = 0xA,\n-\tDESC_ERR_HARQ_INPUT_LEN = 0xB,\n-\tDESC_ERR_CB_READ_FAIL = 0xC,\n-\tDESC_ERR_CB_READ_TIMEOUT = 0xD,\n-\tDESC_ERR_CB_READ_TLP_POISONED = 0xE,\n-\tDESC_ERR_HBSTORE_ERR = 0xF\n-};\n-\n-\n-/* FPGA 5GNR FEC DMA Encoding Request Descriptor */\n-struct __rte_packed fpga_dma_enc_desc {\n-\tuint32_t done:1,\n-\t\trsrvd0:7,\n-\t\terror:4,\n-\t\trsrvd1:4,\n-\t\tnum_null:10,\n-\t\trsrvd2:6;\n-\tuint32_t ncb:15,\n-\t\trsrvd3:1,\n-\t\tk0:16;\n-\tuint32_t irq_en:1,\n-\t\tcrc_en:1,\n-\t\trsrvd4:1,\n-\t\tqm_idx:3,\n-\t\tbg_idx:1,\n-\t\tzc:9,\n-\t\tdesc_idx:10,\n-\t\trsrvd5:6;\n-\tuint16_t rm_e;\n-\tuint16_t k_;\n-\tuint32_t out_addr_lw;\n-\tuint32_t out_addr_hi;\n-\tuint32_t in_addr_lw;\n-\tuint32_t in_addr_hi;\n-\n-\tunion {\n-\t\tstruct {\n-\t\t\t/* Virtual addresses used to retrieve SW context info */\n-\t\t\tvoid *op_addr;\n-\t\t\t/* Stores information about total number of Code Blocks\n-\t\t\t * in currently processed Transport Block\n-\t\t\t */\n-\t\t\tuint64_t cbs_in_op;\n-\t\t};\n-\n-\t\tuint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *\n-\t\t\t\t\t(FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n-\t};\n-};\n-\n-\n-/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */\n-struct __rte_packed fpga_dma_dec_desc {\n-\tuint32_t done:1,\n-\t\titer:5,\n-\t\tet_pass:1,\n-\t\tcrcb_pass:1,\n-\t\terror:4,\n-\t\tqm_idx:3,\n-\t\tmax_iter:5,\n-\t\tbg_idx:1,\n-\t\trsrvd0:1,\n-\t\tharqin_en:1,\n-\t\tzc:9;\n-\tuint32_t hbstroe_offset:22,\n-\t\tnum_null:10;\n-\tuint32_t irq_en:1,\n-\t\tncb:15,\n-\t\tdesc_idx:10,\n-\t\tdrop_crc24b:1,\n-\t\tcrc24b_ind:1,\n-\t\trv:2,\n-\t\tet_dis:1,\n-\t\trsrvd2:1;\n-\tuint32_t harq_input_length:16,\n-\t\trm_e:16;/*the inbound data byte length*/\n-\tuint32_t out_addr_lw;\n-\tuint32_t out_addr_hi;\n-\tuint32_t in_addr_lw;\n-\tuint32_t in_addr_hi;\n-\n-\tunion {\n-\t\tstruct {\n-\t\t\t/* Virtual addresses used to retrieve SW context info */\n-\t\t\tvoid *op_addr;\n-\t\t\t/* Stores information about total number of Code Blocks\n-\t\t\t * in currently processed Transport Block\n-\t\t\t */\n-\t\t\tuint8_t cbs_in_op;\n-\t\t};\n-\n-\t\tuint32_t sw_ctxt[8 * (FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n-\t};\n-};\n-\n-/* FPGA 5GNR DMA Descriptor */\n-union fpga_dma_desc {\n-\tstruct fpga_dma_enc_desc enc_req;\n-\tstruct fpga_dma_dec_desc dec_req;\n+\tFPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */\n+\tFPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */\n+\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */\n+\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */\n+\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */\n+\tFPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68  /**< len: 4B. */\n };\n \n /* FPGA 5GNR Ring Control Register. */\n@@ -257,7 +136,7 @@ struct fpga_5gnr_fec_device {\n /** Structure associated with each queue. */\n struct __rte_cache_aligned fpga_5gnr_queue {\n \tstruct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg;  /**< Ring Control Register */\n-\tunion fpga_dma_desc *ring_addr;  /* Virtual address of software ring */\n+\tunion vc_5gnr_dma_desc *vc_5gnr_ring_addr; /**< Virtual address of VC 5GNR software ring. */\n \tuint64_t *ring_head_addr;  /* Virtual address of completion_head */\n \tuint64_t shadow_completion_head; /* Shadow completion head value */\n \tuint16_t head_free_desc;  /* Ring head */\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 5fbe913ddbe2..41e6e6b58905 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -69,12 +69,11 @@ print_ring_reg_debug_info(void *mmio_base, uint32_t offset)\n \t\t\t\tFPGA_5GNR_FEC_RING_HEAD_POINT));\n }\n \n-/* Read Static Register of FPGA 5GNR FEC device */\n+/* Read Static Register of Vista Creek device. */\n static inline void\n print_static_reg_debug_info(void *mmio_base)\n {\n-\tuint16_t config = fpga_5gnr_reg_read_16(mmio_base,\n-\t\t\tFPGA_5GNR_FEC_CONFIGURATION);\n+\tuint16_t config = fpga_5gnr_reg_read_16(mmio_base, VC_5GNR_CONFIGURATION);\n \tuint8_t qmap_done = fpga_5gnr_reg_read_8(mmio_base,\n \t\t\tFPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);\n \tuint16_t lb_factor = fpga_5gnr_reg_read_16(mmio_base,\n@@ -89,53 +88,53 @@ print_static_reg_debug_info(void *mmio_base)\n \trte_bbdev_log_debug(\"Queue-PF/VF Mapping Table = %s\",\n \t\t\t(qmap_done > 0) ? \"READY\" : \"NOT-READY\");\n \trte_bbdev_log_debug(\"Ring Descriptor Size = %u bytes\",\n-\t\t\tring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);\n+\t\t\tring_desc_len*VC_5GNR_RING_DESC_LEN_UNIT_BYTES);\n }\n \n-/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */\n+/* Print decode DMA Descriptor of Vista Creek Decoder device. */\n static void\n-print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)\n+vc_5gnr_print_dma_dec_desc_debug_info(union vc_5gnr_dma_desc *desc)\n {\n \trte_bbdev_log_debug(\"DMA response desc %p\\n\"\n-\t\t\"\\t-- done(%\"PRIu32\") | iter(%\"PRIu32\") | et_pass(%\"PRIu32\")\"\n-\t\t\" | crcb_pass (%\"PRIu32\") | error(%\"PRIu32\")\\n\"\n-\t\t\"\\t-- qm_idx(%\"PRIu32\") | max_iter(%\"PRIu32\") | \"\n-\t\t\"bg_idx (%\"PRIu32\") | harqin_en(%\"PRIu32\") | zc(%\"PRIu32\")\\n\"\n-\t\t\"\\t-- hbstroe_offset(%\"PRIu32\") | num_null (%\"PRIu32\") \"\n-\t\t\"| irq_en(%\"PRIu32\")\\n\"\n-\t\t\"\\t-- ncb(%\"PRIu32\") | desc_idx (%\"PRIu32\") | \"\n-\t\t\"drop_crc24b(%\"PRIu32\") | RV (%\"PRIu32\")\\n\"\n-\t\t\"\\t-- crc24b_ind(%\"PRIu32\") | et_dis (%\"PRIu32\")\\n\"\n-\t\t\"\\t-- harq_input_length(%\"PRIu32\") | rm_e(%\"PRIu32\")\\n\"\n-\t\t\"\\t-- cbs_in_op(%\"PRIu32\") | in_add (0x%08\"PRIx32\"%08\"PRIx32\")\"\n-\t\t\"| out_add (0x%08\"PRIx32\"%08\"PRIx32\")\",\n-\t\tdesc,\n-\t\t(uint32_t)desc->dec_req.done,\n-\t\t(uint32_t)desc->dec_req.iter,\n-\t\t(uint32_t)desc->dec_req.et_pass,\n-\t\t(uint32_t)desc->dec_req.crcb_pass,\n-\t\t(uint32_t)desc->dec_req.error,\n-\t\t(uint32_t)desc->dec_req.qm_idx,\n-\t\t(uint32_t)desc->dec_req.max_iter,\n-\t\t(uint32_t)desc->dec_req.bg_idx,\n-\t\t(uint32_t)desc->dec_req.harqin_en,\n-\t\t(uint32_t)desc->dec_req.zc,\n-\t\t(uint32_t)desc->dec_req.hbstroe_offset,\n-\t\t(uint32_t)desc->dec_req.num_null,\n-\t\t(uint32_t)desc->dec_req.irq_en,\n-\t\t(uint32_t)desc->dec_req.ncb,\n-\t\t(uint32_t)desc->dec_req.desc_idx,\n-\t\t(uint32_t)desc->dec_req.drop_crc24b,\n-\t\t(uint32_t)desc->dec_req.rv,\n-\t\t(uint32_t)desc->dec_req.crc24b_ind,\n-\t\t(uint32_t)desc->dec_req.et_dis,\n-\t\t(uint32_t)desc->dec_req.harq_input_length,\n-\t\t(uint32_t)desc->dec_req.rm_e,\n-\t\t(uint32_t)desc->dec_req.cbs_in_op,\n-\t\t(uint32_t)desc->dec_req.in_addr_hi,\n-\t\t(uint32_t)desc->dec_req.in_addr_lw,\n-\t\t(uint32_t)desc->dec_req.out_addr_hi,\n-\t\t(uint32_t)desc->dec_req.out_addr_lw);\n+\t\t\t\"\\t-- done(%\"PRIu32\") | iter(%\"PRIu32\") | et_pass(%\"PRIu32\")\"\n+\t\t\t\" | crcb_pass (%\"PRIu32\") | error(%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- qm_idx(%\"PRIu32\") | max_iter(%\"PRIu32\") | \"\n+\t\t\t\"bg_idx (%\"PRIu32\") | harqin_en(%\"PRIu32\") | zc(%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- hbstroe_offset(%\"PRIu32\") | num_null (%\"PRIu32\") \"\n+\t\t\t\"| irq_en(%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- ncb(%\"PRIu32\") | desc_idx (%\"PRIu32\") | \"\n+\t\t\t\"drop_crc24b(%\"PRIu32\") | RV (%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- crc24b_ind(%\"PRIu32\") | et_dis (%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- harq_input_length(%\"PRIu32\") | rm_e(%\"PRIu32\")\\n\"\n+\t\t\t\"\\t-- cbs_in_op(%\"PRIu32\") | in_add (0x%08\"PRIx32\"%08\"PRIx32\")\"\n+\t\t\t\"| out_add (0x%08\"PRIx32\"%08\"PRIx32\")\",\n+\t\t\tdesc,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.done,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.iter,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.et_pass,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.crcb_pass,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.error,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.qm_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.max_iter,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.bg_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.harqin_en,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.zc,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.hbstroe_offset,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.num_null,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.irq_en,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.ncb,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.desc_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.drop_crc24b,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.rv,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.crc24b_ind,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.et_dis,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.harq_input_length,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.rm_e,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.cbs_in_op,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.in_addr_hi,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.in_addr_lw,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.out_addr_hi,\n+\t\t\t(uint32_t)desc->vc_5gnr_dec_req.out_addr_lw);\n \tuint32_t *word = (uint32_t *) desc;\n \trte_bbdev_log_debug(\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\"\n \t\t\t\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\",\n@@ -143,9 +142,9 @@ print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)\n \t\t\tword[4], word[5], word[6], word[7]);\n }\n \n-/* Print decode DMA Descriptor of FPGA 5GNR encoder device */\n+/* Print decode DMA Descriptor of Vista Creek encoder device. */\n static void\n-print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)\n+vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc)\n {\n \trte_bbdev_log_debug(\"DMA response desc %p\\n\"\n \t\t\t\"%\"PRIu32\" %\"PRIu32\"\\n\"\n@@ -153,22 +152,22 @@ print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)\n \t\t\t\"BG %\"PRIu32\" Qm %\"PRIu32\" CRC %\"PRIu32\" IRQ %\"PRIu32\"\\n\"\n \t\t\t\"k0 %\"PRIu32\" Ncb %\"PRIu32\" F %\"PRIu32\"\\n\",\n \t\t\tdesc,\n-\t\t\t(uint32_t)desc->enc_req.done,\n-\t\t\t(uint32_t)desc->enc_req.error,\n-\n-\t\t\t(uint32_t)desc->enc_req.k_,\n-\t\t\t(uint32_t)desc->enc_req.rm_e,\n-\t\t\t(uint32_t)desc->enc_req.desc_idx,\n-\t\t\t(uint32_t)desc->enc_req.zc,\n-\n-\t\t\t(uint32_t)desc->enc_req.bg_idx,\n-\t\t\t(uint32_t)desc->enc_req.qm_idx,\n-\t\t\t(uint32_t)desc->enc_req.crc_en,\n-\t\t\t(uint32_t)desc->enc_req.irq_en,\n-\n-\t\t\t(uint32_t)desc->enc_req.k0,\n-\t\t\t(uint32_t)desc->enc_req.ncb,\n-\t\t\t(uint32_t)desc->enc_req.num_null);\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.done,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.error,\n+\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.k_,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.rm_e,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.desc_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.zc,\n+\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.bg_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.qm_idx,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.crc_en,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.irq_en,\n+\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.k0,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.ncb,\n+\t\t\t(uint32_t)desc->vc_5gnr_enc_req.num_null);\n \tuint32_t *word = (uint32_t *) desc;\n \trte_bbdev_log_debug(\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\"\n \t\t\t\"%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n%08\"PRIx32\"\\n\",\n@@ -204,9 +203,9 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t * replaced with a queue ID and if it's not then\n \t * FPGA_5GNR_INVALID_HW_QUEUE_ID is returned.\n \t */\n-\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n+\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n \t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));\n+\t\t\t\tVC_5GNR_QUEUE_MAP + (q_id << 2));\n \n \t\trte_bbdev_log_debug(\"%s: queue ID: %u, registry queue ID: %u\",\n \t\t\t\tdev->device->name, q_id, hw_q_id);\n@@ -216,8 +215,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t\t\t/* Clear queue register of found queue */\n \t\t\toffset = FPGA_5GNR_FEC_RING_CTRL_REGS +\n \t\t\t\t(sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_id);\n-\t\t\tfpga_ring_reg_write(d->mmio_base,\n-\t\t\t\t\toffset, ring_reg);\n+\t\t\tfpga_ring_reg_write(d->mmio_base, offset, ring_reg);\n \t\t\t++hw_q_num;\n \t\t}\n \t}\n@@ -234,7 +232,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id\n \t\treturn -EINVAL;\n \t}\n \n-\tring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);\n+\tring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct vc_5gnr_dma_dec_desc);\n \n \t/* Enforce 32 byte alignment */\n \tRTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);\n@@ -369,9 +367,9 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_\n \n \t/* Calculates number of queues assigned to device */\n \tdev_info->max_num_queues = 0;\n-\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n+\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n \t\tuint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base,\n-\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));\n+\t\t\t\tVC_5GNR_QUEUE_MAP + (q_id << 2));\n \t\tif (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID)\n \t\t\tdev_info->max_num_queues++;\n \t}\n@@ -396,11 +394,11 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev,\n \tstruct fpga_5gnr_fec_device *d = dev->data->dev_private;\n \tuint64_t q_idx;\n \tuint8_t i = 0;\n-\tuint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;\n+\tuint8_t range = VC_5GNR_TOTAL_NUM_QUEUES >> 1;\n \n \tif (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) {\n-\t\ti = FPGA_NUM_DL_QUEUES;\n-\t\trange = FPGA_TOTAL_NUM_QUEUES;\n+\t\ti = VC_5GNR_NUM_DL_QUEUES;\n+\t\trange = VC_5GNR_TOTAL_NUM_QUEUES;\n \t}\n \n \tfor (; i < range; ++i) {\n@@ -447,7 +445,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tq->q_idx = q_idx;\n \n \t/* Set ring_base_addr */\n-\tq->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));\n+\tq->vc_5gnr_ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));\n \tq->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + (d->sw_ring_size * queue_id);\n \n \t/* Allocate memory for Completion Head variable*/\n@@ -663,7 +661,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg)\n \tuint8_t i;\n \n \t/* Scan queue assigned to this device */\n-\tfor (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {\n+\tfor (i = 0; i < VC_5GNR_TOTAL_NUM_QUEUES; ++i) {\n \t\tq_idx = 1ULL << i;\n \t\tif (d->q_bound_bit_map & q_idx) {\n \t\t\tqueue_id = get_queue_id(dev->data, i);\n@@ -723,13 +721,12 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev)\n \t * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where\n \t * the IRQ number is a direct translation to the queue number.\n \t *\n-\t * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()\n+\t * 63 (VC_5GNR_NUM_INTR_VEC) event fds are created as rte_intr_enable()\n \t * mapped the first IRQ to already created interrupt event file\n \t * descriptor (intr_handle->fd).\n \t */\n-\tif (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {\n-\t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\",\n-\t\t\t\tdev->data->num_queues);\n+\tif (rte_intr_efd_enable(dev->intr_handle, VC_5GNR_NUM_INTR_VEC)) {\n+\t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\", dev->data->num_queues);\n \t\treturn -1;\n \t}\n \n@@ -738,16 +735,14 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev)\n \t * It ensures that callback function assigned to that descriptor will\n \t * invoked when any FPGA queue issues interrupt.\n \t */\n-\tfor (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {\n+\tfor (i = 0; i < VC_5GNR_NUM_INTR_VEC; ++i) {\n \t\tif (rte_intr_efds_index_set(dev->intr_handle, i,\n \t\t\t\trte_intr_fd_get(dev->intr_handle)))\n \t\t\treturn -rte_errno;\n \t}\n \n-\tif (rte_intr_vec_list_alloc(dev->intr_handle, \"intr_vec\",\n-\t\t\tdev->data->num_queues)) {\n-\t\trte_bbdev_log(ERR, \"Failed to allocate %u vectors\",\n-\t\t\t\tdev->data->num_queues);\n+\tif (rte_intr_vec_list_alloc(dev->intr_handle, \"intr_vec\", dev->data->num_queues)) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate %u vectors\", dev->data->num_queues);\n \t\treturn -ENOMEM;\n \t}\n \n@@ -810,52 +805,52 @@ check_bit(uint32_t bitmap, uint32_t bitmask)\n \treturn bitmap & bitmask;\n }\n \n-/* Print an error if a descriptor error has occurred.\n- *  Return 0 on success, 1 on failure\n+/* Vista Creek 5GNR FPGA descriptor errors.\n+ * Print an error if a descriptor error has occurred.\n+ * Return 0 on success, 1 on failure.\n  */\n static inline int\n-check_desc_error(uint32_t error_code) {\n+vc_5gnr_check_desc_error(uint32_t error_code) {\n \tswitch (error_code) {\n-\tcase DESC_ERR_NO_ERR:\n+\tcase VC_5GNR_DESC_ERR_NO_ERR:\n \t\treturn 0;\n-\tcase DESC_ERR_K_P_OUT_OF_RANGE:\n+\tcase VC_5GNR_DESC_ERR_K_P_OUT_OF_RANGE:\n \t\trte_bbdev_log(ERR, \"Encode block size K' is out of range\");\n \t\tbreak;\n-\tcase DESC_ERR_Z_C_NOT_LEGAL:\n+\tcase VC_5GNR_DESC_ERR_Z_C_NOT_LEGAL:\n \t\trte_bbdev_log(ERR, \"Zc is illegal\");\n \t\tbreak;\n-\tcase DESC_ERR_DESC_OFFSET_ERR:\n+\tcase VC_5GNR_DESC_ERR_DESC_OFFSET_ERR:\n \t\trte_bbdev_log(ERR,\n \t\t\t\t\"Queue offset does not meet the expectation in the FPGA\"\n \t\t\t\t);\n \t\tbreak;\n-\tcase DESC_ERR_DESC_READ_FAIL:\n+\tcase VC_5GNR_DESC_ERR_DESC_READ_FAIL:\n \t\trte_bbdev_log(ERR, \"Unsuccessful completion for descriptor read\");\n \t\tbreak;\n-\tcase DESC_ERR_DESC_READ_TIMEOUT:\n+\tcase VC_5GNR_DESC_ERR_DESC_READ_TIMEOUT:\n \t\trte_bbdev_log(ERR, \"Descriptor read time-out\");\n \t\tbreak;\n-\tcase DESC_ERR_DESC_READ_TLP_POISONED:\n+\tcase VC_5GNR_DESC_ERR_DESC_READ_TLP_POISONED:\n \t\trte_bbdev_log(ERR, \"Descriptor read TLP poisoned\");\n \t\tbreak;\n-\tcase DESC_ERR_HARQ_INPUT_LEN:\n+\tcase VC_5GNR_DESC_ERR_HARQ_INPUT_LEN:\n \t\trte_bbdev_log(ERR, \"HARQ input length is invalid\");\n \t\tbreak;\n-\tcase DESC_ERR_CB_READ_FAIL:\n+\tcase VC_5GNR_DESC_ERR_CB_READ_FAIL:\n \t\trte_bbdev_log(ERR, \"Unsuccessful completion for code block\");\n \t\tbreak;\n-\tcase DESC_ERR_CB_READ_TIMEOUT:\n+\tcase VC_5GNR_DESC_ERR_CB_READ_TIMEOUT:\n \t\trte_bbdev_log(ERR, \"Code block read time-out\");\n \t\tbreak;\n-\tcase DESC_ERR_CB_READ_TLP_POISONED:\n+\tcase VC_5GNR_DESC_ERR_CB_READ_TLP_POISONED:\n \t\trte_bbdev_log(ERR, \"Code block read TLP poisoned\");\n \t\tbreak;\n-\tcase DESC_ERR_HBSTORE_ERR:\n+\tcase VC_5GNR_DESC_ERR_HBSTORE_ERR:\n \t\trte_bbdev_log(ERR, \"Hbstroe exceeds HARQ buffer size.\");\n \t\tbreak;\n \tdefault:\n-\t\trte_bbdev_log(ERR, \"Descriptor error unknown error code %u\",\n-\t\t\t\terror_code);\n+\t\trte_bbdev_log(ERR, \"Descriptor error unknown error code %u\", error_code);\n \t\tbreak;\n \t}\n \treturn 1;\n@@ -894,6 +889,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)\n }\n \n /**\n+ * Vista Creek 5GNR FPGA\n  * Set DMA descriptor for encode operation (1 Code Block)\n  *\n  * @param op\n@@ -918,8 +914,8 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)\n  *   Number of CBs contained in one operation.\n  */\n static inline int\n-fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n-\t\tstruct fpga_dma_enc_desc *desc, struct rte_mbuf *input,\n+vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n+\t\tstruct vc_5gnr_dma_enc_desc *desc, struct rte_mbuf *input,\n \t\tstruct rte_mbuf *output, uint16_t k_,  uint16_t e,\n \t\tuint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,\n \t\tuint8_t cbs_in_op)\n@@ -958,6 +954,7 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n }\n \n /**\n+ * Vista Creek 5GNR FPGA\n  * Set DMA descriptor for decode operation (1 Code Block)\n  *\n  * @param op\n@@ -976,8 +973,8 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,\n  *   Number of CBs contained in one operation.\n  */\n static inline int\n-fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n-\t\tstruct fpga_dma_dec_desc *desc,\n+vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n+\t\tstruct vc_5gnr_dma_dec_desc *desc,\n \t\tstruct rte_mbuf *input,\tstruct rte_mbuf *output,\n \t\tuint16_t harq_in_length,\n \t\tuint32_t in_offset, uint32_t out_offset,\n@@ -1024,16 +1021,14 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,\n \treturn 0;\n }\n \n-/* Validates LDPC encoder parameters */\n+/* Validates LDPC encoder parameters for VC 5GNR FPGA. */\n static inline int\n-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n+vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n {\n \tstruct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;\n+\tint z_c, n_filler, K, Kp, q_m, n_cb, N, k0, crc24;\n+\tint32_t L, Lcb, cw, cw_rm, e;\n \n-\tif (op->mempool == NULL) {\n-\t\trte_bbdev_log(ERR, \"Invalid mempool pointer\");\n-\t\treturn -1;\n-\t}\n \tif (ldpc_enc->input.data == NULL) {\n \t\trte_bbdev_log(ERR, \"Invalid input pointer\");\n \t\treturn -1;\n@@ -1073,7 +1068,8 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t\t\t\tRTE_BBDEV_LDPC_MAX_CB_SIZE);\n \t\treturn -1;\n \t}\n-\tint z_c = ldpc_enc->z_c;\n+\n+\tz_c = ldpc_enc->z_c;\n \t/* Check Zc is valid value */\n \tif ((z_c > 384) || (z_c < 4)) {\n \t\trte_bbdev_log(ERR, \"Zc (%u) is out of range\", z_c);\n@@ -1106,19 +1102,17 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t\t}\n \t}\n \n-\tint n_filler = ldpc_enc->n_filler;\n-\tint K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c;\n-\tint Kp = K - n_filler;\n-\tint q_m = ldpc_enc->q_m;\n-\tint n_cb = ldpc_enc->n_cb;\n-\tint N = (ldpc_enc->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c;\n-\tint k0 = get_k0(n_cb, z_c, ldpc_enc->basegraph,\n-\t\t\tldpc_enc->rv_index);\n-\tint crc24 = 0;\n-\tint32_t L, Lcb, cw, cw_rm;\n-\tint32_t e = ldpc_enc->cb_params.e;\n-\tif (check_bit(op->ldpc_enc.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH))\n+\tn_filler = ldpc_enc->n_filler;\n+\tK = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c;\n+\tKp = K - n_filler;\n+\tq_m = ldpc_enc->q_m;\n+\tn_cb = ldpc_enc->n_cb;\n+\tN = (ldpc_enc->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c;\n+\tk0 = get_k0(n_cb, z_c, ldpc_enc->basegraph, ldpc_enc->rv_index);\n+\tcrc24 = 0;\n+\te = ldpc_enc->cb_params.e;\n+\n+\tif (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH))\n \t\tcrc24 = 24;\n \n \tif (K < (int) (ldpc_enc->input.length * 8 + n_filler) + crc24) {\n@@ -1161,8 +1155,7 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \t\treturn -1;\n \t}\n \t/* K0 range check */\n-\tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c))\n-\t\t\t&& (k0 < (K - 2 * z_c)))) {\n+\tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) {\n \t\trte_bbdev_log(ERR, \"K0 (%u) is out of range\", k0);\n \t\treturn -1;\n \t}\n@@ -1223,20 +1216,21 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)\n \telse\n \t\tcw_rm = cw - n_filler;\n \tif (cw_rm <= 32) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Invalid Ratematching\");\n+\t\trte_bbdev_log(ERR, \"Invalid Ratematching\");\n \t\treturn -1;\n \t}\n \treturn 0;\n }\n \n-/* Validates LDPC decoder parameters */\n+/* Validates LDPC decoder parameters for VC 5GNR FPGA. */\n static inline int\n-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n+vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n {\n \tstruct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;\n-\tif (check_bit(ldpc_dec->op_flags,\n-\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK))\n+\tint z_c, n_filler, K, Kp, q_m, n_cb, N, k0, crc24;\n+\tint32_t L, Lcb, cw, cw_rm, e;\n+\n+\tif (check_bit(ldpc_dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK))\n \t\treturn 0;\n \tif (ldpc_dec->input.data == NULL) {\n \t\trte_bbdev_log(ERR, \"Invalid input pointer\");\n@@ -1274,17 +1268,15 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\t\t\tldpc_dec->code_block_mode);\n \t\treturn -1;\n \t}\n-\tif (check_bit(op->ldpc_dec.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_DECODE_BYPASS)) {\n+\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DECODE_BYPASS)) {\n \t\trte_bbdev_log(ERR, \"Avoid LDPC Decode bypass\");\n \t\treturn -1;\n \t}\n-\tint z_c = ldpc_dec->z_c;\n+\n+\tz_c = ldpc_dec->z_c;\n \t/* Check Zc is valid value */\n \tif ((z_c > 384) || (z_c < 4)) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Zc (%u) is out of range\",\n-\t\t\t\tz_c);\n+\t\trte_bbdev_log(ERR, \"Zc (%u) is out of range\", z_c);\n \t\treturn -1;\n \t}\n \tif (z_c > 256) {\n@@ -1314,24 +1306,21 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\t}\n \t}\n \n-\tint n_filler = ldpc_dec->n_filler;\n-\tint K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c;\n-\tint Kp = K - n_filler;\n-\tint q_m = ldpc_dec->q_m;\n-\tint n_cb = ldpc_dec->n_cb;\n-\tint N = (ldpc_dec->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c;\n-\tint k0 = get_k0(n_cb, z_c, ldpc_dec->basegraph,\n-\t\t\tldpc_dec->rv_index);\n-\tint crc24 = 0;\n-\tint32_t L, Lcb, cw, cw_rm;\n-\tint32_t e = ldpc_dec->cb_params.e;\n-\tif (check_bit(op->ldpc_dec.op_flags,\n-\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK))\n+\tn_filler = ldpc_dec->n_filler;\n+\tK = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c;\n+\tKp = K - n_filler;\n+\tq_m = ldpc_dec->q_m;\n+\tn_cb = ldpc_dec->n_cb;\n+\tN = (ldpc_dec->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c;\n+\tk0 = get_k0(n_cb, z_c, ldpc_dec->basegraph, ldpc_dec->rv_index);\n+\tcrc24 = 0;\n+\te = ldpc_dec->cb_params.e;\n+\n+\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK))\n \t\tcrc24 = 24;\n \n \tif (ldpc_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"TB mode not supported\");\n+\t\trte_bbdev_log(ERR, \"TB mode not supported\");\n \t\treturn -1;\n \t}\n \t/* Enforce HARQ input length */\n@@ -1353,34 +1342,24 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \n \t/* K' range check */\n \tif (Kp % 8 > 0) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"K' not byte aligned %u\",\n-\t\t\t\tKp);\n+\t\trte_bbdev_log(ERR, \"K' not byte aligned %u\", Kp);\n \t\treturn -1;\n \t}\n \tif ((crc24 > 0) && (Kp < 292)) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Invalid CRC24 for small block %u\",\n-\t\t\t\tKp);\n+\t\trte_bbdev_log(ERR, \"Invalid CRC24 for small block %u\", Kp);\n \t\treturn -1;\n \t}\n \tif (Kp < 24) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"K' too small %u\",\n-\t\t\t\tKp);\n+\t\trte_bbdev_log(ERR, \"K' too small %u\", Kp);\n \t\treturn -1;\n \t}\n \tif (n_filler >= (K - 2 * z_c)) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"K - F invalid %u %u\",\n-\t\t\t\tK, n_filler);\n+\t\trte_bbdev_log(ERR, \"K - F invalid %u %u\", K, n_filler);\n \t\treturn -1;\n \t}\n \t/* Ncb range check */\n \tif (n_cb != N) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Ncb (%u) is out of range K  %d N %d\",\n-\t\t\t\tn_cb, K, N);\n+\t\trte_bbdev_log(ERR, \"Ncb (%u) is out of range K  %d N %d\", n_cb, K, N);\n \t\treturn -1;\n \t}\n \t/* Qm range check */\n@@ -1388,34 +1367,26 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\t\tRTE_BBDEV_LDPC_INTERLEAVER_BYPASS) &&\n \t\t\t((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1))\n \t\t\t|| (q_m > 8))) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Qm (%u) is out of range\",\n-\t\t\t\tq_m);\n+\t\trte_bbdev_log(ERR, \"Qm (%u) is out of range\", q_m);\n \t\treturn -1;\n \t}\n \t/* K0 range check */\n-\tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c))\n-\t\t\t&& (k0 < (K - 2 * z_c)))) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"K0 (%u) is out of range\",\n-\t\t\t\tk0);\n+\tif (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) {\n+\t\trte_bbdev_log(ERR, \"K0 (%u) is out of range\", k0);\n \t\treturn -1;\n \t}\n \t/* E range check */\n \tif (e <= RTE_MAX(32, z_c)) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"E is too small\");\n+\t\trte_bbdev_log(ERR, \"E is too small\");\n \t\treturn -1;\n \t}\n \tif ((e > 0xFFFF)) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"E is too large\");\n+\t\trte_bbdev_log(ERR, \"E is too large\");\n \t\treturn -1;\n \t}\n \tif (q_m > 0) {\n \t\tif (e % q_m > 0) {\n-\t\t\trte_bbdev_log(ERR,\n-\t\t\t\t\t\"E not multiple of qm %d\", q_m);\n+\t\t\trte_bbdev_log(ERR, \"E not multiple of qm %d\", q_m);\n \t\t\treturn -1;\n \t\t}\n \t}\n@@ -1424,8 +1395,8 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t\tL = k0 + e;\n \telse\n \t\tL = k0 + e + n_filler;\n-\tLcb = RTE_MIN(n_cb, RTE_MAX(L,\n-\t\t\t(int32_t) ldpc_dec->harq_combined_input.length));\n+\n+\tLcb = RTE_MIN(n_cb, RTE_MAX(L, (int32_t) ldpc_dec->harq_combined_input.length));\n \tif (ldpc_dec->basegraph == 1) {\n \t\tif (Lcb <= 25 * z_c)\n \t\t\tcw = 25 * z_c;\n@@ -1455,8 +1426,7 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)\n \t}\n \tcw_rm = cw - n_filler;\n \tif (cw_rm <= 32) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"Invalid Ratematching\");\n+\t\trte_bbdev_log(ERR, \"Invalid Ratematching\");\n \t\treturn -1;\n \t}\n \treturn 0;\n@@ -1627,7 +1597,7 @@ static inline int\n enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *op,\n \t\tuint16_t desc_offset)\n {\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *vc_5gnr_desc;\n \tint ret;\n \tuint8_t c, crc24_bits = 0;\n \tstruct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;\n@@ -1641,8 +1611,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \tuint16_t ring_offset;\n \tuint16_t K, k_;\n \n-\n-\tif (validate_ldpc_enc_op(op) == -1) {\n+\tif (vc_5gnr_validate_ldpc_enc_op(op) == -1) {\n \t\trte_bbdev_log(ERR, \"LDPC encoder validation rejected\");\n \t\treturn -EINVAL;\n \t}\n@@ -1690,9 +1659,8 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \t/* Offset into the ring */\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \t/* Setup DMA Descriptor */\n-\tdesc = q->ring_addr + ring_offset;\n-\n-\tret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out,\n+\tvc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset;\n+\tret = vc_5gnr_dma_desc_te_fill(op, &vc_5gnr_desc->vc_5gnr_enc_req, m_in, m_out,\n \t\t\tk_, e, in_offset, out_offset, ring_offset, c);\n \tif (unlikely(ret < 0))\n \t\treturn ret;\n@@ -1709,16 +1677,16 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o\n \t}\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\tprint_dma_enc_desc_debug_info(desc);\n+\tvc_5gnr_print_dma_enc_desc_debug_info(vc_5gnr_desc);\n #endif\n \treturn 1;\n }\n \n static inline int\n-enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *op,\n+vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *op,\n \t\tuint16_t desc_offset)\n {\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *desc;\n \tint ret;\n \tuint16_t ring_offset;\n \tuint8_t c;\n@@ -1733,7 +1701,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \tuint16_t out_offset = dec->hard_output.offset;\n \tuint32_t harq_offset = 0;\n \n-\tif (validate_ldpc_dec_op(op) == -1) {\n+\tif (vc_5gnr_validate_ldpc_dec_op(op) == -1) {\n \t\trte_bbdev_log(ERR, \"LDPC decoder validation rejected\");\n \t\treturn -EINVAL;\n \t}\n@@ -1743,7 +1711,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \n \t/* Setup DMA Descriptor */\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n-\tdesc = q->ring_addr + ring_offset;\n+\tdesc = q->vc_5gnr_ring_addr + ring_offset;\n \n \tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {\n \t\tstruct rte_mbuf *harq_in = dec->harq_combined_input.data;\n@@ -1769,13 +1737,14 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \t\t}\n \n \t\t/* Set descriptor for dequeue */\n-\t\tdesc->dec_req.done = 1;\n-\t\tdesc->dec_req.error = 0;\n-\t\tdesc->dec_req.op_addr = op;\n-\t\tdesc->dec_req.cbs_in_op = 1;\n+\t\tdesc->vc_5gnr_dec_req.done = 1;\n+\t\tdesc->vc_5gnr_dec_req.error = 0;\n+\t\tdesc->vc_5gnr_dec_req.op_addr = op;\n+\t\tdesc->vc_5gnr_dec_req.cbs_in_op = 1;\n \n \t\t/* Mark this dummy descriptor to be dropped by HW */\n-\t\tdesc->dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask;\n+\t\tdesc->vc_5gnr_dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask;\n+\n \t\treturn ret; /* Error or number of CB */\n \t}\n \n@@ -1799,24 +1768,21 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \tin_length = e;\n \tseg_total_left = dec->input.length;\n \n-\tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) {\n-\t\tharq_in_length = RTE_MIN(dec->harq_combined_input.length,\n-\t\t\t\t(uint32_t)dec->n_cb);\n-\t}\n+\tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))\n+\t\tharq_in_length = RTE_MIN(dec->harq_combined_input.length, (uint32_t)dec->n_cb);\n \n \tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {\n-\t\tk0 = get_k0(dec->n_cb, dec->z_c,\n-\t\t\t\tdec->basegraph, dec->rv_index);\n+\t\tk0 = get_k0(dec->n_cb, dec->z_c, dec->basegraph, dec->rv_index);\n \t\tif (k0 > parity_offset)\n \t\t\tl = k0 + e;\n \t\telse\n \t\t\tl = k0 + e + dec->n_filler;\n-\t\tharq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l),\n-\t\t\t\tdec->n_cb);\n+\t\tharq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l), dec->n_cb);\n \t\tdec->harq_combined_output.length = harq_out_length;\n \t}\n \n \tmbuf_append(m_out_head, m_out, out_length);\n+\n \tif (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))\n \t\tharq_offset = dec->harq_combined_input.offset;\n \telse if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))\n@@ -1828,9 +1794,10 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \t\treturn -1;\n \t}\n \n-\tret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out,\n+\tret = vc_5gnr_dma_desc_ld_fill(op, &desc->vc_5gnr_dec_req, m_in, m_out,\n \t\tharq_in_length, in_offset, out_offset, harq_offset,\n \t\tring_offset, c);\n+\n \tif (unlikely(ret < 0))\n \t\treturn ret;\n \t/* Update lengths */\n@@ -1844,7 +1811,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o\n \t}\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\tprint_dma_dec_desc_debug_info(desc);\n+\tvc_5gnr_print_dma_dec_desc_debug_info(desc);\n #endif\n \n \treturn 1;\n@@ -1858,11 +1825,10 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \tint32_t avail;\n \tint enqueued_cbs;\n \tstruct fpga_5gnr_queue *q = q_data->queue_private;\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *vc_5gnr_desc;\n \n \t/* Check if queue is not full */\n-\tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==\n-\t\t\tq->head_free_desc))\n+\tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc))\n \t\treturn 0;\n \n \t/* Calculates available space */\n@@ -1871,7 +1837,6 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\tq->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;\n \n \tfor (i = 0; i < num; ++i) {\n-\n \t\t/* Check if there is available space for further\n \t\t * processing\n \t\t */\n@@ -1893,9 +1858,9 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt\n \t * only when all previous CBs were already processed.\n \t */\n-\tdesc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)\n-\t\t\t& q->sw_ring_wrap_mask);\n-\tdesc->enc_req.irq_en = q->irq_enable;\n+\tvc_5gnr_desc = q->vc_5gnr_ring_addr +\n+\t\t\t((q->tail + total_enqueued_cbs - 1) & q->sw_ring_wrap_mask);\n+\tvc_5gnr_desc->vc_5gnr_enc_req.irq_en = q->irq_enable;\n \n \tfpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n \n@@ -1914,7 +1879,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \tint32_t avail;\n \tint enqueued_cbs;\n \tstruct fpga_5gnr_queue *q = q_data->queue_private;\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *vc_5gnr_desc;\n \n \t/* Check if queue is not full */\n \tif (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc))\n@@ -1933,7 +1898,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\tif (unlikely(avail - 1 < 0))\n \t\t\tbreak;\n \t\tavail -= 1;\n-\t\tenqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i],\n+\t\tenqueued_cbs = vc_5gnr_enqueue_ldpc_dec_one_op_cb(q, ops[i],\n \t\t\t\ttotal_enqueued_cbs);\n \n \t\tif (enqueued_cbs < 0)\n@@ -1953,25 +1918,25 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt\n \t * only when all previous CBs were already processed.\n \t */\n-\tdesc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)\n-\t\t\t& q->sw_ring_wrap_mask);\n-\tdesc->enc_req.irq_en = q->irq_enable;\n+\tvc_5gnr_desc = q->vc_5gnr_ring_addr +\n+\t\t\t((q->tail + total_enqueued_cbs - 1) & q->sw_ring_wrap_mask);\n+\tvc_5gnr_desc->vc_5gnr_enc_req.irq_en = q->irq_enable;\n \tfpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);\n \treturn i;\n }\n \n \n static inline int\n-dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **op,\n+vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **op,\n \t\tuint16_t desc_offset)\n {\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *desc;\n \tint desc_error;\n \t/* Set current desc */\n-\tdesc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n+\tdesc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n \n \t/*check if done */\n-\tif (desc->enc_req.done == 0)\n+\tif (desc->vc_5gnr_enc_req.done == 0)\n \t\treturn -1;\n \n \t/* make sure the response is read atomically */\n@@ -1980,12 +1945,11 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **\n \trte_bbdev_log_debug(\"DMA response desc %p\", desc);\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\tprint_dma_enc_desc_debug_info(desc);\n+\tvc_5gnr_print_dma_enc_desc_debug_info(desc);\n #endif\n-\n-\t*op = desc->enc_req.op_addr;\n+\t*op = desc->vc_5gnr_enc_req.op_addr;\n \t/* Check the descriptor error field, return 1 on error */\n-\tdesc_error = check_desc_error(desc->enc_req.error);\n+\tdesc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_enc_req.error);\n \t(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;\n \n \treturn 1;\n@@ -1993,27 +1957,27 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **\n \n \n static inline int\n-dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **op,\n+vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **op,\n \t\tuint16_t desc_offset)\n {\n-\tunion fpga_dma_desc *desc;\n+\tunion vc_5gnr_dma_desc *desc;\n \tint desc_error;\n+\n \t/* Set descriptor */\n-\tdesc = q->ring_addr + ((q->head_free_desc + desc_offset)\n-\t\t\t& q->sw_ring_wrap_mask);\n+\tdesc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask);\n \n \t/* Verify done bit is set */\n-\tif (desc->dec_req.done == 0)\n+\tif (desc->vc_5gnr_dec_req.done == 0)\n \t\treturn -1;\n \n \t/* make sure the response is read atomically */\n \trte_smp_rmb();\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n-\tprint_dma_dec_desc_debug_info(desc);\n+\tvc_5gnr_print_dma_dec_desc_debug_info(desc);\n #endif\n \n-\t*op = desc->dec_req.op_addr;\n+\t*op = desc->vc_5gnr_dec_req.op_addr;\n \n \tif (check_bit((*op)->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {\n@@ -2022,15 +1986,20 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **\n \t}\n \n \t/* FPGA reports iterations based on round-up minus 1 */\n-\t(*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1;\n+\t(*op)->ldpc_dec.iter_count = desc->vc_5gnr_dec_req.iter + 1;\n+\n \t/* CRC Check criteria */\n-\tif (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass))\n+\tif (desc->vc_5gnr_dec_req.crc24b_ind && !(desc->vc_5gnr_dec_req.crcb_pass))\n \t\t(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;\n+\n \t/* et_pass = 0 when decoder fails */\n-\t(*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;\n+\t(*op)->status |= !(desc->vc_5gnr_dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;\n+\n \t/* Check the descriptor error field, return 1 on error */\n-\tdesc_error = check_desc_error(desc->dec_req.error);\n+\tdesc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_dec_req.error);\n+\n \t(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;\n+\n \treturn 1;\n }\n \n@@ -2045,7 +2014,7 @@ fpga_5gnr_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \tint ret;\n \n \tfor (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {\n-\t\tret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);\n+\t\tret = vc_5gnr_dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);\n \n \t\tif (ret < 0)\n \t\t\tbreak;\n@@ -2077,7 +2046,7 @@ fpga_5gnr_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \tint ret;\n \n \tfor (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {\n-\t\tret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);\n+\t\tret = vc_5gnr_dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);\n \n \t\tif (ret < 0)\n \t\t\tbreak;\n@@ -2167,9 +2136,8 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,\n \t\t\tbbdev->data->dev_id, dev_name);\n \n \tstruct fpga_5gnr_fec_device *d = bbdev->data->dev_private;\n-\tuint32_t version_id = fpga_5gnr_reg_read_32(d->mmio_base,\n-\t\t\tFPGA_5GNR_FEC_VERSION_ID);\n-\trte_bbdev_log(INFO, \"FEC FPGA RTL v%u.%u\",\n+\tuint32_t version_id = fpga_5gnr_reg_read_32(d->mmio_base, FPGA_5GNR_FEC_VERSION_ID);\n+\trte_bbdev_log(INFO, \"Vista Creek FPGA RTL v%u.%u\",\n \t\t((uint16_t)(version_id >> 16)), ((uint16_t)version_id));\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n@@ -2237,10 +2205,8 @@ fpga_5gnr_set_default_conf(struct rte_fpga_5gnr_fec_conf *def_conf)\n \tdef_conf->ul_load_balance = 64;\n }\n \n-/* Initial configuration of FPGA 5GNR FEC device */\n-int\n-rte_fpga_5gnr_fec_configure(const char *dev_name,\n-\t\tconst struct rte_fpga_5gnr_fec_conf *conf)\n+/* Initial configuration of Vista Creek device. */\n+static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf)\n {\n \tuint32_t payload_32, address;\n \tuint16_t payload_16;\n@@ -2259,8 +2225,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \tstruct fpga_5gnr_fec_device *d = bbdev->data->dev_private;\n \n \tif (conf == NULL) {\n-\t\trte_bbdev_log(ERR,\n-\t\t\t\t\"FPGA Configuration was not provided. Default configuration will be loaded.\");\n+\t\trte_bbdev_log(ERR, \"VC FPGA Configuration was not provided.\");\n+\t\trte_bbdev_log(ERR, \"Default configuration will be loaded.\");\n \t\tfpga_5gnr_set_default_conf(&def_conf);\n \t\tconf = &def_conf;\n \t}\n@@ -2271,13 +2237,13 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t * [15:8]: DL weight\n \t */\n \tpayload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;\n-\taddress = FPGA_5GNR_FEC_CONFIGURATION;\n+\taddress = VC_5GNR_CONFIGURATION;\n \tfpga_5gnr_reg_write_16(d->mmio_base, address, payload_16);\n \n \t/* Clear all queues registers */\n \tpayload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID;\n-\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n-\t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\taddress = (q_id << 2) + VC_5GNR_QUEUE_MAP;\n \t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t}\n \n@@ -2285,7 +2251,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t * If PF mode is enabled allocate all queues for PF only.\n \t *\n \t * For VF mode each VF can have different number of UL and DL queues.\n-\t * Total number of queues to configure cannot exceed FPGA\n+\t * Total number of queues to configure cannot exceed VC FPGA\n \t * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.\n \t * Queues mapping is done according to configuration:\n \t *\n@@ -2337,8 +2303,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t */\n \tif (conf->pf_mode_en) {\n \t\tpayload_32 = 0x1;\n-\t\tfor (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {\n-\t\t\taddress = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\t\tfor (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) {\n+\t\t\taddress = (q_id << 2) + VC_5GNR_QUEUE_MAP;\n \t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address, payload_32);\n \t\t}\n \t} else {\n@@ -2353,21 +2319,20 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t\t * Check if total number of queues to configure does not exceed\n \t\t * FPGA capabilities (64 queues - 32 UL and 32 DL queues)\n \t\t */\n-\t\tif ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||\n-\t\t\t(total_dl_q_id > FPGA_NUM_DL_QUEUES) ||\n-\t\t\t(total_q_id > FPGA_TOTAL_NUM_QUEUES)) {\n+\t\tif ((total_ul_q_id > VC_5GNR_NUM_UL_QUEUES) ||\n+\t\t\t(total_dl_q_id > VC_5GNR_NUM_DL_QUEUES) ||\n+\t\t\t(total_q_id > VC_5GNR_TOTAL_NUM_QUEUES)) {\n \t\t\trte_bbdev_log(ERR,\n-\t\t\t\t\t\"FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u\",\n+\t\t\t\t\t\"VC 5GNR FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u\",\n \t\t\t\t\ttotal_ul_q_id, total_dl_q_id,\n-\t\t\t\t\tFPGA_TOTAL_NUM_QUEUES);\n+\t\t\t\t\tVC_5GNR_TOTAL_NUM_QUEUES);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\ttotal_ul_q_id = 0;\n \t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n \t\t\tfor (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];\n \t\t\t\t\t++q_id, ++total_ul_q_id) {\n-\t\t\t\taddress = (total_ul_q_id << 2) +\n-\t\t\t\t\t\tFPGA_5GNR_FEC_QUEUE_MAP;\n+\t\t\t\taddress = (total_ul_q_id << 2) + VC_5GNR_QUEUE_MAP;\n \t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n \t\t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address,\n \t\t\t\t\t\tpayload_32);\n@@ -2377,8 +2342,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \t\tfor (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {\n \t\t\tfor (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];\n \t\t\t\t\t++q_id, ++total_dl_q_id) {\n-\t\t\t\taddress = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)\n-\t\t\t\t\t\t<< 2) + FPGA_5GNR_FEC_QUEUE_MAP;\n+\t\t\t\taddress = ((total_dl_q_id + VC_5GNR_NUM_UL_QUEUES)\n+\t\t\t\t\t\t<< 2) + VC_5GNR_QUEUE_MAP;\n \t\t\t\tpayload_32 = ((0x80 + vf_id) << 16) | 0x1;\n \t\t\t\tfpga_5gnr_reg_write_32(d->mmio_base, address,\n \t\t\t\t\t\tpayload_32);\n@@ -2401,8 +2366,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \taddress = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;\n \tfpga_5gnr_reg_write_8(d->mmio_base, address, payload_8);\n \n-\trte_bbdev_log_debug(\"PF FPGA 5GNR FEC configuration complete for %s\",\n-\t\t\tdev_name);\n+\trte_bbdev_log_debug(\"PF Vista Creek 5GNR FPGA configuration complete for %s\", dev_name);\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \tprint_static_reg_debug_info(d->mmio_base);\n@@ -2410,11 +2374,27 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,\n \treturn 0;\n }\n \n+int rte_fpga_5gnr_fec_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf)\n+{\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR, \"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\t\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);\n+\tprintf(\"Configure dev id %x\\n\", pci_dev->id.device_id);\n+\tif (pci_dev->id.device_id == VC_5GNR_PF_DEVICE_ID)\n+\t\treturn vc_5gnr_configure(dev_name, conf);\n+\n+\trte_bbdev_log(ERR, \"Invalid device_id (%d)\", pci_dev->id.device_id);\n+\treturn -ENODEV;\n+}\n+\n /* FPGA 5GNR FEC PCI PF address map */\n static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {\n \t{\n-\t\tRTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,\n-\t\t\t\tFPGA_5GNR_FEC_PF_DEVICE_ID)\n+\t\tRTE_PCI_DEVICE(VC_5GNR_VENDOR_ID, VC_5GNR_PF_DEVICE_ID)\n \t},\n \t{.device_id = 0},\n };\n@@ -2429,8 +2409,7 @@ static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {\n /* FPGA 5GNR FEC PCI VF address map */\n static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {\n \t{\n-\t\tRTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,\n-\t\t\t\tFPGA_5GNR_FEC_VF_DEVICE_ID)\n+\t\tRTE_PCI_DEVICE(VC_5GNR_VENDOR_ID, VC_5GNR_VF_DEVICE_ID)\n \t},\n \t{.device_id = 0},\n };\ndiff --git a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h\nnew file mode 100644\nindex 000000000000..4c14cb70e9f6\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h\n@@ -0,0 +1,140 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _VC_5GNR_PMD_H_\n+#define _VC_5GNR_PMD_H_\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+\n+/* VC 5GNR FPGA FEC PCI vendor & device IDs. */\n+#define VC_5GNR_VENDOR_ID\t(0x8086)\n+#define VC_5GNR_PF_DEVICE_ID\t(0x0D8F)\n+#define VC_5GNR_VF_DEVICE_ID\t(0x0D90)\n+\n+#define VC_5GNR_NUM_UL_QUEUES (32)\n+#define VC_5GNR_NUM_DL_QUEUES (32)\n+#define VC_5GNR_TOTAL_NUM_QUEUES (VC_5GNR_NUM_UL_QUEUES + VC_5GNR_NUM_DL_QUEUES)\n+#define VC_5GNR_NUM_INTR_VEC (VC_5GNR_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)\n+\n+/* VC 5GNR Ring size is in 256 bits (32 bytes) units. */\n+#define VC_5GNR_RING_DESC_LEN_UNIT_BYTES (32)\n+\n+/* Align DMA descriptors to 256 bytes - cache-aligned. */\n+#define VC_5GNR_RING_DESC_ENTRY_LENGTH (8)\n+\n+/* VC 5GNR FPGA Register mapping on BAR0. */\n+enum {\n+\tVC_5GNR_CONFIGURATION = 0x00000004, /* len: 2B. */\n+\tVC_5GNR_QUEUE_MAP = 0x00000040\t/* len: 256B. */\n+};\n+\n+/* VC 5GNR FPGA FEC DESCRIPTOR ERROR. */\n+enum {\n+\tVC_5GNR_DESC_ERR_NO_ERR = 0x0,\n+\tVC_5GNR_DESC_ERR_K_P_OUT_OF_RANGE = 0x1,\n+\tVC_5GNR_DESC_ERR_Z_C_NOT_LEGAL = 0x2,\n+\tVC_5GNR_DESC_ERR_DESC_OFFSET_ERR = 0x3,\n+\tVC_5GNR_DESC_ERR_DESC_READ_FAIL = 0x8,\n+\tVC_5GNR_DESC_ERR_DESC_READ_TIMEOUT = 0x9,\n+\tVC_5GNR_DESC_ERR_DESC_READ_TLP_POISONED = 0xA,\n+\tVC_5GNR_DESC_ERR_HARQ_INPUT_LEN = 0xB,\n+\tVC_5GNR_DESC_ERR_CB_READ_FAIL = 0xC,\n+\tVC_5GNR_DESC_ERR_CB_READ_TIMEOUT = 0xD,\n+\tVC_5GNR_DESC_ERR_CB_READ_TLP_POISONED = 0xE,\n+\tVC_5GNR_DESC_ERR_HBSTORE_ERR = 0xF\n+};\n+\n+/* VC 5GNR FPGA FEC DMA Encoding Request Descriptor. */\n+struct __rte_packed vc_5gnr_dma_enc_desc {\n+\tuint32_t done:1,\n+\t\trsrvd0:7,\n+\t\terror:4,\n+\t\trsrvd1:4,\n+\t\tnum_null:10,\n+\t\trsrvd2:6;\n+\tuint32_t ncb:15,\n+\t\trsrvd3:1,\n+\t\tk0:16;\n+\tuint32_t irq_en:1,\n+\t\tcrc_en:1,\n+\t\trsrvd4:1,\n+\t\tqm_idx:3,\n+\t\tbg_idx:1,\n+\t\tzc:9,\n+\t\tdesc_idx:10,\n+\t\trsrvd5:6;\n+\tuint16_t rm_e;\n+\tuint16_t k_;\n+\tuint32_t out_addr_lw;\n+\tuint32_t out_addr_hi;\n+\tuint32_t in_addr_lw;\n+\tuint32_t in_addr_hi;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\t/** Virtual addresses used to retrieve SW context info. */\n+\t\t\tvoid *op_addr;\n+\t\t\t/** Stores information about total number of Code Blocks\n+\t\t\t * in currently processed Transport Block.\n+\t\t\t */\n+\t\t\tuint64_t cbs_in_op;\n+\t\t};\n+\n+\t\tuint8_t sw_ctxt[VC_5GNR_RING_DESC_LEN_UNIT_BYTES *\n+\t\t\t\t\t(VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n+\t};\n+};\n+\n+/* VC 5GNR FPGA DPC FEC DMA Decoding Request Descriptor. */\n+struct __rte_packed vc_5gnr_dma_dec_desc {\n+\tuint32_t done:1,\n+\t\titer:5,\n+\t\tet_pass:1,\n+\t\tcrcb_pass:1,\n+\t\terror:4,\n+\t\tqm_idx:3,\n+\t\tmax_iter:5,\n+\t\tbg_idx:1,\n+\t\trsrvd0:1,\n+\t\tharqin_en:1,\n+\t\tzc:9;\n+\tuint32_t hbstroe_offset:22,\n+\t\tnum_null:10;\n+\tuint32_t irq_en:1,\n+\t\tncb:15,\n+\t\tdesc_idx:10,\n+\t\tdrop_crc24b:1,\n+\t\tcrc24b_ind:1,\n+\t\trv:2,\n+\t\tet_dis:1,\n+\t\trsrvd2:1;\n+\tuint32_t harq_input_length:16,\n+\t\trm_e:16; /**< the inbound data byte length. */\n+\tuint32_t out_addr_lw;\n+\tuint32_t out_addr_hi;\n+\tuint32_t in_addr_lw;\n+\tuint32_t in_addr_hi;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\t/** Virtual addresses used to retrieve SW context info. */\n+\t\t\tvoid *op_addr;\n+\t\t\t/** Stores information about total number of Code Blocks\n+\t\t\t * in currently processed Transport Block.\n+\t\t\t */\n+\t\t\tuint8_t cbs_in_op;\n+\t\t};\n+\n+\t\tuint32_t sw_ctxt[8 * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)];\n+\t};\n+};\n+\n+/* Vista Creek 5GNR DMA Descriptor. */\n+union vc_5gnr_dma_desc {\n+\tstruct vc_5gnr_dma_enc_desc vc_5gnr_enc_req;\n+\tstruct vc_5gnr_dma_dec_desc vc_5gnr_dec_req;\n+};\n+\n+#endif /* _VC_5GNR_PMD_H_ */\n",
    "prefixes": [
        "v3",
        "2/4"
    ]
}