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GET /api/patches/131367/?format=api
{ "id": 131367, "url": "https://patches.dpdk.org/api/patches/131367/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230912173039.1612287-8-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230912173039.1612287-8-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230912173039.1612287-8-beilei.xing@intel.com", "date": "2023-09-12T17:30:36", "name": "[v6,07/10] net/cpfl: parse representor devargs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7b285c504e55082afa5d4bbd290ceae611877c1a", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230912173039.1612287-8-beilei.xing@intel.com/mbox/", "series": [ { "id": 29486, "url": "https://patches.dpdk.org/api/series/29486/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29486", "date": "2023-09-12T17:30:29", "name": "net/cpfl: support port representor", "version": 6, "mbox": "https://patches.dpdk.org/series/29486/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131367/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 34FCA4257B;\n\tTue, 12 Sep 2023 11:12:59 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 81D1240C35;\n\tTue, 12 Sep 2023 11:12:19 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id DD97540A7D\n for <dev@dpdk.org>; Tue, 12 Sep 2023 11:12:16 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Sep 2023 02:12:14 -0700", "from dpdk-beileix-icelake.sh.intel.com ([10.67.116.248])\n by fmsmga008.fm.intel.com with ESMTP; 12 Sep 2023 02:12:12 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1694509937; x=1726045937;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=0K5AGADklr5dGJn/sfapQsyXMRc0rku1bBU8AtPi7cI=;\n b=PxJwDqX3IBqmS6r2XOGzaBfb7gzqNYCJFrzajMiAZkW/btbxORfPdXET\n pmMjM2V9k2Yac2yy9OHe8h2bbQ+Y2or5Oj6ipbuMoP8Mnsj49k/hv8OV0\n lWiz5GmFUZGzt0uPQMkvxgzpmb4qFt2XI84PBrvTVnh4kb7Quoc1jh4IX\n 9heVfIEZRb219p4/hHxv1AqYPVLQSrQKJX7gCv78jxFH3AVMDoZPAdCOI\n pMGyY4lq83cAVkRjmTN17oAirwV7gglR3kTbzL+C0bNZpqBzvF7uBZUMB\n UaPSEnBRgYN15zrck7Ie2FffM/rlaXOotCUAPf9AtwYq2SkZYuenGtLHm g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10830\"; a=\"375652078\"", "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"375652078\"", "E=McAfee;i=\"6600,9927,10830\"; a=\"809164441\"", "E=Sophos;i=\"6.02,245,1688454000\"; d=\"scan'208\";a=\"809164441\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Qi Zhang <qi.z.zhang@intel.com>", "Subject": "[PATCH v6 07/10] net/cpfl: parse representor devargs", "Date": "Tue, 12 Sep 2023 17:30:36 +0000", "Message-Id": "<20230912173039.1612287-8-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230912173039.1612287-1-beilei.xing@intel.com>", "References": "<20230912162640.1439383-1-beilei.xing@intel.com>\n <20230912173039.1612287-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nFormat:\n\n[[c<controller_id>]pf<pf_id>]vf<vf_id>\n\n controller_id:\n\n 0 : host (default)\n 1: acc\n\n pf_id:\n\n 0 : apf (default)\n 1 : cpf\n\nExample:\n\nrepresentor=c0pf0vf[0-3]\n -- host > apf > vf 0,1,2,3\n same as pf0vf[0-3] and vf[0-3] if omit default value.\n\nrepresentor=c0pf0\n -- host > apf\n same as pf0 if omit default value.\n\nrepresentor=c1pf0\n -- accelerator core > apf\n\nmultiple representor devargs are supported.\ne.g.: create 4 representors for 4 vfs on host APF and one\nrepresentor for APF on accelerator core.\n\n -- representor=vf[0-3],representor=c1pf0\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n doc/guides/nics/cpfl.rst | 36 +++++\n doc/guides/rel_notes/release_23_11.rst | 3 +\n drivers/net/cpfl/cpfl_ethdev.c | 179 +++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_ethdev.h | 8 ++\n 4 files changed, 226 insertions(+)", "diff": "diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst\nindex 39a2b603f3..83a18c3f2e 100644\n--- a/doc/guides/nics/cpfl.rst\n+++ b/doc/guides/nics/cpfl.rst\n@@ -92,6 +92,42 @@ Runtime Configuration\n Then the PMD will configure Tx queue with single queue mode.\n Otherwise, split queue mode is chosen by default.\n \n+- ``representor`` (default ``not enabled``)\n+\n+ The cpfl PMD supports the creation of APF/CPF/VF port representors.\n+ Each port representor corresponds to a single function of that device.\n+ Using the ``devargs`` option ``representor`` the user can specify\n+ which functions to create port representors.\n+\n+ Format is::\n+\n+ [[c<controller_id>]pf<pf_id>]vf<vf_id>\n+\n+ Controller_id 0 is host (default), while 1 is accelerator core.\n+ Pf_id 0 is APF (default), while 1 is CPF.\n+ Default value can be omitted.\n+\n+ Create 4 representors for 4 vfs on host APF::\n+\n+ -a BDF,representor=c0pf0vf[0-3]\n+\n+ Or::\n+\n+ -a BDF,representor=pf0vf[0-3]\n+\n+ Or::\n+\n+ -a BDF,representor=vf[0-3]\n+\n+ Create a representor for CPF on accelerator core::\n+\n+ -a BDF,representor=c1pf1\n+\n+ Multiple representor devargs are supported. Create 4 representors for 4\n+ vfs on host APF and one representor for CPF on accelerator core::\n+\n+ -a BDF,representor=vf[0-3],representor=c1pf1\n+\n \n Driver compilation and testing\n ------------------------------\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 333e1d95a2..3d9be208d0 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -78,6 +78,9 @@ New Features\n * build: Optional libraries can now be selected with the new ``enable_libs``\n build option similarly to the existing ``enable_drivers`` build option.\n \n+* **Updated Intel cpfl driver.**\n+\n+ * Added support for port representor.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex a7a045ace4..b6fcfe4275 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -13,8 +13,10 @@\n #include <rte_hash_crc.h>\n \n #include \"cpfl_ethdev.h\"\n+#include <ethdev_private.h>\n #include \"cpfl_rxtx.h\"\n \n+#define CPFL_REPRESENTOR\t\"representor\"\n #define CPFL_TX_SINGLE_Q\t\"tx_single\"\n #define CPFL_RX_SINGLE_Q\t\"rx_single\"\n #define CPFL_VPORT\t\t\"vport\"\n@@ -25,6 +27,7 @@ struct cpfl_adapter_list cpfl_adapter_list;\n bool cpfl_adapter_list_init;\n \n static const char * const cpfl_valid_args[] = {\n+\tCPFL_REPRESENTOR,\n \tCPFL_TX_SINGLE_Q,\n \tCPFL_RX_SINGLE_Q,\n \tCPFL_VPORT,\n@@ -1407,6 +1410,128 @@ parse_bool(const char *key, const char *value, void *args)\n \treturn 0;\n }\n \n+static int\n+enlist(uint16_t *list, uint16_t *len_list, const uint16_t max_list, uint16_t val)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < *len_list; i++) {\n+\t\tif (list[i] == val)\n+\t\t\treturn 0;\n+\t}\n+\tif (*len_list >= max_list)\n+\t\treturn -1;\n+\tlist[(*len_list)++] = val;\n+\treturn 0;\n+}\n+\n+static const char *\n+process_range(const char *str, uint16_t *list, uint16_t *len_list,\n+\tconst uint16_t max_list)\n+{\n+\tuint16_t lo, hi, val;\n+\tint result, n = 0;\n+\tconst char *pos = str;\n+\n+\tresult = sscanf(str, \"%hu%n-%hu%n\", &lo, &n, &hi, &n);\n+\tif (result == 1) {\n+\t\tif (enlist(list, len_list, max_list, lo) != 0)\n+\t\t\treturn NULL;\n+\t} else if (result == 2) {\n+\t\tif (lo > hi)\n+\t\t\treturn NULL;\n+\t\tfor (val = lo; val <= hi; val++) {\n+\t\t\tif (enlist(list, len_list, max_list, val) != 0)\n+\t\t\t\treturn NULL;\n+\t\t}\n+\t} else {\n+\t\treturn NULL;\n+\t}\n+\treturn pos + n;\n+}\n+\n+static const char *\n+process_list(const char *str, uint16_t *list, uint16_t *len_list, const uint16_t max_list)\n+{\n+\tconst char *pos = str;\n+\n+\tif (*pos == '[')\n+\t\tpos++;\n+\twhile (1) {\n+\t\tpos = process_range(pos, list, len_list, max_list);\n+\t\tif (pos == NULL)\n+\t\t\treturn NULL;\n+\t\tif (*pos != ',') /* end of list */\n+\t\t\tbreak;\n+\t\tpos++;\n+\t}\n+\tif (*str == '[' && *pos != ']')\n+\t\treturn NULL;\n+\tif (*pos == ']')\n+\t\tpos++;\n+\treturn pos;\n+}\n+\n+static int\n+parse_repr(const char *key __rte_unused, const char *value, void *args)\n+{\n+\tstruct cpfl_devargs *devargs = args;\n+\tstruct rte_eth_devargs *eth_da;\n+\tconst char *str = value;\n+\n+\tif (devargs->repr_args_num == CPFL_REPR_ARG_NUM_MAX)\n+\t\treturn -EINVAL;\n+\n+\teth_da = &devargs->repr_args[devargs->repr_args_num];\n+\n+\tif (str[0] == 'c') {\n+\t\tstr += 1;\n+\t\tstr = process_list(str, eth_da->mh_controllers,\n+\t\t\t\tð_da->nb_mh_controllers,\n+\t\t\t\tRTE_DIM(eth_da->mh_controllers));\n+\t\tif (str == NULL)\n+\t\t\tgoto done;\n+\t}\n+\tif (str[0] == 'p' && str[1] == 'f') {\n+\t\teth_da->type = RTE_ETH_REPRESENTOR_PF;\n+\t\tstr += 2;\n+\t\tstr = process_list(str, eth_da->ports,\n+\t\t\t\tð_da->nb_ports, RTE_DIM(eth_da->ports));\n+\t\tif (str == NULL || str[0] == '\\0')\n+\t\t\tgoto done;\n+\t} else if (eth_da->nb_mh_controllers > 0) {\n+\t\t/* 'c' must followed by 'pf'. */\n+\t\tstr = NULL;\n+\t\tgoto done;\n+\t}\n+\tif (str[0] == 'v' && str[1] == 'f') {\n+\t\teth_da->type = RTE_ETH_REPRESENTOR_VF;\n+\t\tstr += 2;\n+\t} else if (str[0] == 's' && str[1] == 'f') {\n+\t\teth_da->type = RTE_ETH_REPRESENTOR_SF;\n+\t\tstr += 2;\n+\t} else {\n+\t\t/* 'pf' must followed by 'vf' or 'sf'. */\n+\t\tif (eth_da->type == RTE_ETH_REPRESENTOR_PF) {\n+\t\t\tstr = NULL;\n+\t\t\tgoto done;\n+\t\t}\n+\t\teth_da->type = RTE_ETH_REPRESENTOR_VF;\n+\t}\n+\tstr = process_list(str, eth_da->representor_ports,\n+\t\tð_da->nb_representor_ports,\n+\t\tRTE_DIM(eth_da->representor_ports));\n+done:\n+\tif (str == NULL) {\n+\t\tRTE_LOG(ERR, EAL, \"wrong representor format: %s\\n\", str);\n+\t\treturn -1;\n+\t}\n+\n+\tdevargs->repr_args_num++;\n+\n+\treturn 0;\n+}\n+\n static int\n cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n {\n@@ -1431,6 +1556,12 @@ cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adap\n \t\treturn -EINVAL;\n \t}\n \n+\tcpfl_args->repr_args_num = 0;\n+\tret = rte_kvargs_process(kvlist, CPFL_REPRESENTOR, &parse_repr, cpfl_args);\n+\n+\tif (ret != 0)\n+\t\tgoto fail;\n+\n \tret = rte_kvargs_process(kvlist, CPFL_VPORT, &parse_vport,\n \t\t\t\t cpfl_args);\n \tif (ret != 0)\n@@ -2087,6 +2218,48 @@ cpfl_vport_devargs_process(struct cpfl_adapter_ext *adapter)\n \treturn 0;\n }\n \n+static int\n+cpfl_repr_devargs_process(struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct cpfl_devargs *devargs = &adapter->devargs;\n+\tint i, j;\n+\n+\t/* check and refine repr args */\n+\tfor (i = 0; i < devargs->repr_args_num; i++) {\n+\t\tstruct rte_eth_devargs *eth_da = &devargs->repr_args[i];\n+\n+\t\t/* set default host_id to xeon host */\n+\t\tif (eth_da->nb_mh_controllers == 0) {\n+\t\t\teth_da->nb_mh_controllers = 1;\n+\t\t\teth_da->mh_controllers[0] = CPFL_HOST_ID_HOST;\n+\t\t} else {\n+\t\t\tfor (j = 0; j < eth_da->nb_mh_controllers; j++) {\n+\t\t\t\tif (eth_da->mh_controllers[j] > CPFL_HOST_ID_ACC) {\n+\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n+\t\t\t\t\t\t eth_da->mh_controllers[j]);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* set default pf to APF */\n+\t\tif (eth_da->nb_ports == 0) {\n+\t\t\teth_da->nb_ports = 1;\n+\t\t\teth_da->ports[0] = CPFL_PF_TYPE_APF;\n+\t\t} else {\n+\t\t\tfor (j = 0; j < eth_da->nb_ports; j++) {\n+\t\t\t\tif (eth_da->ports[j] > CPFL_PF_TYPE_CPF) {\n+\t\t\t\t\tPMD_INIT_LOG(ERR, \"Invalid Host ID %d\",\n+\t\t\t\t\t\t eth_da->ports[j]);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n cpfl_vport_create(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n {\n@@ -2165,6 +2338,12 @@ cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\tgoto err;\n \t}\n \n+\tretval = cpfl_repr_devargs_process(adapter);\n+\tif (retval != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to process repr devargs\");\n+\t\tgoto err;\n+\t}\n+\n \treturn 0;\n \n err:\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex eb51a12fac..362cad155d 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -60,16 +60,24 @@\n #define IDPF_DEV_ID_CPF\t\t\t0x1453\n #define VIRTCHNL2_QUEUE_GROUP_P2P\t0x100\n \n+#define CPFL_HOST_ID_HOST\t0\n+#define CPFL_HOST_ID_ACC\t1\n+#define CPFL_PF_TYPE_APF\t0\n+#define CPFL_PF_TYPE_CPF\t1\n+\n struct cpfl_vport_param {\n \tstruct cpfl_adapter_ext *adapter;\n \tuint16_t devarg_id; /* arg id from user */\n \tuint16_t idx; /* index in adapter->vports[]*/\n };\n \n+#define CPFL_REPR_ARG_NUM_MAX\t4\n /* Struct used when parse driver specific devargs */\n struct cpfl_devargs {\n \tuint16_t req_vports[CPFL_MAX_VPORT_NUM];\n \tuint16_t req_vport_nb;\n+\tuint8_t repr_args_num;\n+\tstruct rte_eth_devargs repr_args[CPFL_REPR_ARG_NUM_MAX];\n };\n \n struct p2p_queue_chunks_info {\n", "prefixes": [ "v6", "07/10" ] }