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GET /api/patches/131010/?format=api
{ "id": 131010, "url": "https://patches.dpdk.org/api/patches/131010/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230901023050.40893-6-caowenbo@mucse.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230901023050.40893-6-caowenbo@mucse.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230901023050.40893-6-caowenbo@mucse.com", "date": "2023-09-01T02:30:47", "name": "[v6,5/8] net/rnp add reset code for Chip Init process", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "e168b64e2c19875d5dfb059416f2c3fc50809c58", "submitter": { "id": 2142, "url": "https://patches.dpdk.org/api/people/2142/?format=api", "name": "11", "email": "caowenbo@mucse.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230901023050.40893-6-caowenbo@mucse.com/mbox/", "series": [ { "id": 29398, "url": "https://patches.dpdk.org/api/series/29398/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29398", "date": "2023-09-01T02:30:42", "name": "drivers/net Add Support mucse N10 Pmd Driver", "version": 6, "mbox": "https://patches.dpdk.org/series/29398/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131010/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1843942219;\n\tFri, 1 Sep 2023 04:32:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 969AF402BE;\n\tFri, 1 Sep 2023 04:31:48 +0200 (CEST)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by mails.dpdk.org (Postfix) with ESMTP id 44D9C402B8\n for <dev@dpdk.org>; Fri, 1 Sep 2023 04:31:45 +0200 (CEST)", "from steven.localdomain ( [183.81.182.182])\n by bizesmtp.qq.com (ESMTP) with\n id ; Fri, 01 Sep 2023 10:31:23 +0800 (CST)" ], "X-QQ-mid": "bizesmtp81t1693535485t9qqbwxu", "X-QQ-SSF": "01400000000000D0F000000A0000000", "X-QQ-FEAT": "Kol1Dm0TdrASHb7dWm+0pTaJpS0IhSsDtsBL9qMc/4QyR2oha1e888R99Q+mK\n qYMzyusR3zfDER7LxOwabMlyOq7YEPO1GxPuq839vBxS8iSEhVqokWvXIunKNefJD0BmSZz\n WorTMMvttb/fKfc4wqEQWb1Z3hyVisYEZINvjguCwymWUr+g3vMvf0VDguWes12YFO/T9NP\n Fym+C7pGnCEYBcbmeL502iD8DZJI39YkZbVDTWJ4hbuo9IilkkT64Di759gtCijJFA8kCoT\n u46lBRjpDkA7GK9WlAQg6xSFnYlr9Gvm1jOFo10BikLpmX4PHQQS3krDnxOwOeUE5CsID7X\n +dne9oWPaEpzS/72ILyK/mtscsNdjqLygjV0PL1SWqFJTQ/hyAopLkIwRP0TTK4SFOVJ+R6\n uSe5/F1Eysg=", "X-QQ-GoodBg": "2", "X-BIZMAIL-ID": "889999060884530103", "From": "Wenbo Cao <caowenbo@mucse.com>", "To": "Wenbo Cao <caowenbo@mucse.com>", "Cc": "dev@dpdk.org, ferruh.yigit@amd.com, thomas@monjalon.net,\n andrew.rybchenko@oktetlabs.ru, yaojun@mucse.com", "Subject": "[PATCH v6 5/8] net/rnp add reset code for Chip Init process", "Date": "Fri, 1 Sep 2023 02:30:47 +0000", "Message-Id": "<20230901023050.40893-6-caowenbo@mucse.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230901023050.40893-1-caowenbo@mucse.com>", "References": "<20230901023050.40893-1-caowenbo@mucse.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:mucse.com:qybglogicsvrgz:qybglogicsvrgz5a-0", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "we must get the shape info of nic from Firmware for\nreset. so the related codes is first get firmware info\nand then reset the chip\n\nSigned-off-by: Wenbo Cao <caowenbo@mucse.com>\n---\n drivers/net/rnp/base/rnp_hw.h | 56 +++++++++++-\n drivers/net/rnp/meson.build | 3 +\n drivers/net/rnp/rnp.h | 27 ++++++\n drivers/net/rnp/rnp_ethdev.c | 93 ++++++++++++++++++-\n drivers/net/rnp/rnp_mbx_fw.h | 163 +++++++++++++++++++++++++++++++++-\n 5 files changed, 339 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/rnp/base/rnp_hw.h b/drivers/net/rnp/base/rnp_hw.h\nindex 1db966cf21..57b7dc75a0 100644\n--- a/drivers/net/rnp/base/rnp_hw.h\n+++ b/drivers/net/rnp/base/rnp_hw.h\n@@ -8,6 +8,9 @@\n #include <ethdev_driver.h>\n \n #include \"rnp_osdep.h\"\n+#include \"rnp_dma_regs.h\"\n+#include \"rnp_eth_regs.h\"\n+#include \"rnp_cfg.h\"\n \n static inline unsigned int rnp_rd_reg(volatile void *addr)\n {\n@@ -29,7 +32,18 @@ static inline void rnp_wr_reg(volatile void *reg, int val)\n \trnp_rd_reg((uint8_t *)(_base) + (_off))\n #define rnp_io_wr(_base, _off, _val)\t\\\n \trnp_wr_reg((uint8_t *)(_base) + (_off), (_val))\n-\n+#define rnp_eth_rd(_hw, _off)\t\t\\\n+\trnp_rd_reg((uint8_t *)((_hw)->eth_base) + (_off))\n+#define rnp_eth_wr(_hw, _off, _val)\t\\\n+\trnp_wr_reg((uint8_t *)((_hw)->eth_base) + (_off), (_val))\n+#define rnp_dma_rd(_hw, _off)\t\t\\\n+\trnp_rd_reg((uint8_t *)((_hw)->dma_base) + (_off))\n+#define rnp_dma_wr(_hw, _off, _val)\t\\\n+\trnp_wr_reg((uint8_t *)((_hw)->dma_base) + (_off), (_val))\n+#define rnp_top_rd(_hw, _off)\t\t\\\n+\trnp_rd_reg((uint8_t *)((_hw)->comm_reg_base) + (_off))\n+#define rnp_top_wr(_hw, _off, _val)\t\\\n+\trnp_wr_reg((uint8_t *)((_hw)->comm_reg_base) + (_off), (_val))\n struct rnp_hw;\n /* Mbx Operate info */\n enum MBX_ID {\n@@ -98,6 +112,17 @@ struct rnp_mbx_info {\n \trte_atomic16_t state;\n } __rte_cache_aligned;\n \n+struct rnp_mac_api {\n+\tint32_t (*init_hw)(struct rnp_hw *hw);\n+\tint32_t (*reset_hw)(struct rnp_hw *hw);\n+};\n+\n+struct rnp_mac_info {\n+\tuint8_t assign_addr[RTE_ETHER_ADDR_LEN];\n+\tuint8_t set_addr[RTE_ETHER_ADDR_LEN];\n+\tstruct rnp_mac_api ops;\n+} __rte_cache_aligned;\n+\n struct rnp_eth_adapter;\n #define RNP_MAX_HW_PORT_PERR_PF (4)\n struct rnp_hw {\n@@ -111,8 +136,10 @@ struct rnp_hw {\n \tvoid *eth_base;\n \tvoid *veb_base;\n \tvoid *mac_base[RNP_MAX_HW_PORT_PERR_PF];\n+\tvoid *comm_reg_base;\n \tvoid *msix_base;\n \t/* === dma == */\n+\tvoid *dev_version;\n \tvoid *dma_axi_en;\n \tvoid *dma_axi_st;\n \n@@ -120,10 +147,37 @@ struct rnp_hw {\n \tuint16_t vendor_id;\n \tuint16_t function;\n \tuint16_t pf_vf_num;\n+\tint pfvfnum;\n \tuint16_t max_vfs;\n+\n+\tbool ncsi_en;\n+\tuint8_t ncsi_rar_entries;\n+\n+\tint sgmii_phy_id;\n+\tint is_sgmii;\n+\tu16 phy_type;\n+\tuint8_t force_10g_1g_speed_ablity;\n+\tuint8_t force_speed_stat;\n+#define FORCE_SPEED_STAT_DISABLED (0)\n+#define FORCE_SPEED_STAT_1G (1)\n+#define FORCE_SPEED_STAT_10G (2)\n+\tuint32_t speed;\n+\tunsigned int axi_mhz;\n+\n+\tint fw_version; /* Primary FW Version */\n+\tuint32_t fw_uid; /* Subclass Fw Version */\n+\n+\tint nic_mode;\n+\tunsigned char lane_mask;\n+\tint lane_of_port[4];\n+\tchar phy_port_ids[4]; /* port id: for lane0~3: value: 0 ~ 7 */\n+\tuint8_t max_port_num; /* Max Port Num This PF Have */\n+\n \tvoid *cookie_pool;\n \tchar cookie_p_name[RTE_MEMZONE_NAMESIZE];\n \n+\tstruct rnp_mac_info mac;\n \tstruct rnp_mbx_info mbx;\n+\trte_spinlock_t fw_lock;\n } __rte_cache_aligned;\n #endif /* __RNP_H__*/\ndiff --git a/drivers/net/rnp/meson.build b/drivers/net/rnp/meson.build\nindex 60bba486fc..855c894032 100644\n--- a/drivers/net/rnp/meson.build\n+++ b/drivers/net/rnp/meson.build\n@@ -9,5 +9,8 @@ endif\n sources = files(\n \t\t'rnp_ethdev.c',\n \t\t'rnp_mbx.c',\n+\t\t'rnp_mbx_fw.c',\n+\t\t'base/rnp_api.c',\n )\n+\n includes += include_directories('base')\ndiff --git a/drivers/net/rnp/rnp.h b/drivers/net/rnp/rnp.h\nindex 6e12885877..45638aae5b 100644\n--- a/drivers/net/rnp/rnp.h\n+++ b/drivers/net/rnp/rnp.h\n@@ -13,6 +13,20 @@\n #define RNP_CFG_BAR\t\t(4)\n #define RNP_PF_INFO_BAR\t\t(0)\n \n+enum rnp_resource_share_m {\n+\tRNP_SHARE_CORPORATE = 0,\n+\tRNP_SHARE_INDEPENDENT,\n+};\n+/*\n+ * Structure to store private data for each driver instance (for each port).\n+ */\n+enum rnp_work_mode {\n+\tRNP_SINGLE_40G = 0,\n+\tRNP_SINGLE_10G = 1,\n+\tRNP_DUAL_10G = 2,\n+\tRNP_QUAD_10G = 3,\n+};\n+\n struct rnp_eth_port {\n \tstruct rnp_eth_adapter *adapt;\n \tstruct rnp_hw *hw;\n@@ -21,9 +35,12 @@ struct rnp_eth_port {\n \n struct rnp_share_ops {\n \tconst struct rnp_mbx_api *mbx_api;\n+\tconst struct rnp_mac_api *mac_api;\n } __rte_cache_aligned;\n \n struct rnp_eth_adapter {\n+\tenum rnp_work_mode mode;\n+\tenum rnp_resource_share_m s_mode; /* Port Resource Share Policy */\n \tstruct rnp_hw hw;\n \tuint16_t max_vfs;\n \tstruct rte_pci_device *pdev;\n@@ -31,7 +48,9 @@ struct rnp_eth_adapter {\n \tstruct rnp_eth_port *ports[RNP_MAX_PORT_OF_PF];\n \tstruct rnp_share_ops *share_priv;\n \n+\tint max_link_speed;\n \tuint8_t num_ports; /* Cur Pf Has physical Port Num */\n+\tuint8_t lane_mask;\n } __rte_cache_aligned;\n \n #define RNP_DEV_TO_PORT(eth_dev) \\\n@@ -40,9 +59,14 @@ struct rnp_eth_adapter {\n \t((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT(eth_dev)->adapt))\n #define RNP_DEV_TO_HW(eth_dev) \\\n \t(&((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT((eth_dev))->adapt))->hw)\n+#define RNP_HW_TO_ADAPTER(hw) \\\n+\t((struct rnp_eth_adapter *)((hw)->back))\n #define RNP_DEV_PP_PRIV_TO_MBX_OPS(dev) \\\n \t(((struct rnp_share_ops *)(dev)->process_private)->mbx_api)\n #define RNP_DEV_TO_MBX_OPS(dev)\tRNP_DEV_PP_PRIV_TO_MBX_OPS(dev)\n+#define RNP_DEV_PP_PRIV_TO_MAC_OPS(dev) \\\n+\t(((struct rnp_share_ops *)(dev)->process_private)->mac_api)\n+#define RNP_DEV_TO_MAC_OPS(dev) RNP_DEV_PP_PRIV_TO_MAC_OPS(dev)\n \n static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n {\n@@ -56,6 +80,7 @@ static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n \t\thw->msix_base = (void *)((uint8_t *)hw->iobar4 + 0xa4000);\n \t}\n \t/* === dma status/config====== */\n+\thw->dev_version = (void *)((uint8_t *)hw->iobar4 + 0x0000);\n \thw->link_sync = (void *)((uint8_t *)hw->iobar4 + 0x000c);\n \thw->dma_axi_en = (void *)((uint8_t *)hw->iobar4 + 0x0010);\n \thw->dma_axi_st = (void *)((uint8_t *)hw->iobar4 + 0x0014);\n@@ -69,5 +94,7 @@ static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n \t/* mac */\n \tfor (i = 0; i < RNP_MAX_HW_PORT_PERR_PF; i++)\n \t\thw->mac_base[i] = (void *)((uint8_t *)hw->iobar4 + 0x60000 + 0x10000 * i);\n+\t/* === top reg === */\n+\thw->comm_reg_base = (void *)((uint8_t *)hw->iobar4 + 0x30000);\n }\n #endif /* __RNP_H__ */\ndiff --git a/drivers/net/rnp/rnp_ethdev.c b/drivers/net/rnp/rnp_ethdev.c\nindex a2dc27548a..8bb4fd5963 100644\n--- a/drivers/net/rnp/rnp_ethdev.c\n+++ b/drivers/net/rnp/rnp_ethdev.c\n@@ -8,7 +8,9 @@\n #include <ethdev_driver.h>\n \n #include \"rnp.h\"\n+#include \"rnp_api.h\"\n #include \"rnp_mbx.h\"\n+#include \"rnp_mbx_fw.h\"\n #include \"rnp_logs.h\"\n \n static int\n@@ -92,7 +94,30 @@ rnp_alloc_eth_port(struct rte_pci_device *primary_pci, char *name)\n \n static void rnp_get_nic_attr(struct rnp_eth_adapter *adapter)\n {\n-\tRTE_SET_USED(adapter);\n+\tstruct rnp_hw *hw = &adapter->hw;\n+\tint lane_mask = 0, err, mode = 0;\n+\n+\trnp_mbx_link_event_enable(adapter->eth_dev, false);\n+\n+\terr = rnp_mbx_get_capability(adapter->eth_dev, &lane_mask, &mode);\n+\tif (err < 0 || !lane_mask) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: mbx_get_capability error! errcode=%d\\n\",\n+\t\t\t\t__func__, hw->speed);\n+\t\treturn;\n+\t}\n+\n+\tadapter->num_ports = __builtin_popcount(lane_mask);\n+\tadapter->max_link_speed = hw->speed;\n+\tadapter->lane_mask = lane_mask;\n+\tadapter->mode = hw->nic_mode;\n+\n+\tPMD_DRV_LOG(INFO, \"max link speed:%d lane_mask:0x%x nic-mode:0x%x\\n\",\n+\t\t\t(int)adapter->max_link_speed,\n+\t\t\t(int)adapter->num_ports, adapter->mode);\n+\tif (adapter->num_ports && adapter->num_ports == 1)\n+\t\tadapter->s_mode = RNP_SHARE_CORPORATE;\n+\telse\n+\t\tadapter->s_mode = RNP_SHARE_INDEPENDENT;\n }\n \n static int\n@@ -125,6 +150,72 @@ rnp_process_resource_init(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static int32_t rnp_init_hw_pf(struct rnp_hw *hw)\n+{\n+\tstruct rnp_eth_adapter *adapter = RNP_HW_TO_ADAPTER(hw);\n+\tuint32_t version;\n+\tuint32_t reg;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tversion = rnp_rd_reg(hw->dev_version);\n+\tPMD_DRV_LOG(INFO, \"NIC HW Version:0x%.2x\\n\", version);\n+\n+\t/* Disable Rx/Tx Dma */\n+\trnp_wr_reg(hw->dma_axi_en, false);\n+\t/* Check Dma Chanle Status */\n+\twhile (rnp_rd_reg(hw->dma_axi_st) == 0)\n+\t\t;\n+\n+\t/* Reset Nic All Hardware */\n+\tif (rnp_reset_hw(adapter->eth_dev, hw))\n+\t\treturn -EPERM;\n+\n+\t/* Rx Proto Offload No-BYPASS */\n+\trnp_eth_wr(hw, RNP_ETH_ENGINE_BYPASS, false);\n+\t/* Enable Flow Filter Engine */\n+\trnp_eth_wr(hw, RNP_HOST_FILTER_EN, true);\n+\t/* Enable VXLAN Parse */\n+\trnp_eth_wr(hw, RNP_EN_TUNNEL_VXLAN_PARSE, true);\n+\t/* Enabled REDIR ACTION */\n+\trnp_eth_wr(hw, RNP_REDIR_CTRL, true);\n+\n+\t/* Setup Scatter DMA Mem Size */\n+\treg = ((RTE_ETHER_MAX_LEN / 16) << RNP_DMA_SCATTER_MEM_SHIFT);\n+\trnp_dma_wr(hw, RNP_DMA_CTRL, reg);\n+#ifdef PHYTIUM_SUPPORT\n+#define RNP_DMA_PADDING (1 << 8)\n+\treg = rnp_dma_rd(hw, RNP_DMA_CTRL);\n+\treg |= RNP_DMA_PADDING;\n+\trnp_dma_wr(hw, RNP_DMA_CTRL, reg);\n+#endif\n+\t/* Enable Rx/Tx Dma */\n+\trnp_wr_reg(hw->dma_axi_en, 0b1111);\n+\n+\trnp_top_wr(hw, RNP_TX_QINQ_WORKAROUND, 1);\n+\n+\treturn 0;\n+}\n+\n+static int32_t rnp_reset_hw_pf(struct rnp_hw *hw)\n+{\n+\tstruct rnp_eth_adapter *adapter = hw->back;\n+\n+\trnp_top_wr(hw, RNP_NIC_RESET, 0);\n+\trte_wmb();\n+\trnp_top_wr(hw, RNP_NIC_RESET, 1);\n+\n+\trnp_mbx_fw_reset_phy(adapter->eth_dev);\n+\n+\tPMD_DRV_LOG(INFO, \"PF[%d] reset nic finish\\n\",\n+\t\t\thw->function);\n+\treturn 0;\n+}\n+\n+const struct rnp_mac_api rnp_mac_ops = {\n+\t.reset_hw\t= rnp_reset_hw_pf,\n+\t.init_hw\t= rnp_init_hw_pf\n+};\n+\n static void\n rnp_common_ops_init(struct rnp_eth_adapter *adapter)\n {\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.h b/drivers/net/rnp/rnp_mbx_fw.h\nindex 439090b5a3..f842639c86 100644\n--- a/drivers/net/rnp/rnp_mbx_fw.h\n+++ b/drivers/net/rnp/rnp_mbx_fw.h\n@@ -16,7 +16,168 @@ struct mbx_req_cookie {\n \tint priv_len;\n \tchar priv[RNP_MAX_SHARE_MEM];\n };\n+enum GENERIC_CMD {\n+\t/* link configuration admin commands */\n+\tGET_PHY_ABALITY = 0x0601,\n+\tRESET_PHY = 0x0603,\n+\tSET_EVENT_MASK = 0x0613,\n+};\n+\n+enum link_event_mask {\n+\tEVT_LINK_UP = 1,\n+\tEVT_NO_MEDIA = 2,\n+\tEVT_LINK_FAULT = 3,\n+\tEVT_PHY_TEMP_ALARM = 4,\n+\tEVT_EXCESSIVE_ERRORS = 5,\n+\tEVT_SIGNAL_DETECT = 6,\n+\tEVT_AUTO_NEGOTIATION_DONE = 7,\n+\tEVT_MODULE_QUALIFICATION_FAILED = 8,\n+\tEVT_PORT_TX_SUSPEND = 9,\n+};\n+\n+enum pma_type {\n+\tPHY_TYPE_NONE = 0,\n+\tPHY_TYPE_1G_BASE_KX,\n+\tPHY_TYPE_SGMII,\n+\tPHY_TYPE_10G_BASE_KR,\n+\tPHY_TYPE_25G_BASE_KR,\n+\tPHY_TYPE_40G_BASE_KR4,\n+\tPHY_TYPE_10G_BASE_SR,\n+\tPHY_TYPE_40G_BASE_SR4,\n+\tPHY_TYPE_40G_BASE_CR4,\n+\tPHY_TYPE_40G_BASE_LR4,\n+\tPHY_TYPE_10G_BASE_LR,\n+\tPHY_TYPE_10G_BASE_ER,\n+};\n+\n+struct phy_abilities {\n+\tunsigned char link_stat;\n+\tunsigned char lane_mask;\n+\n+\tint speed;\n+\tshort phy_type;\n+\tshort nic_mode;\n+\tshort pfnum;\n+\tunsigned int fw_version;\n+\tunsigned int axi_mhz;\n+\tuint8_t port_ids[4];\n+\tuint32_t fw_uid;\n+\tuint32_t phy_id;\n+\n+\tint wol_status;\n+\n+\tunion {\n+\t\tunsigned int ext_ablity;\n+\t\tstruct {\n+\t\t\tunsigned int valid : 1;\n+\t\t\tunsigned int wol_en : 1;\n+\t\t\tunsigned int pci_preset_runtime_en : 1;\n+\t\t\tunsigned int smbus_en : 1;\n+\t\t\tunsigned int ncsi_en : 1;\n+\t\t\tunsigned int rpu_en : 1;\n+\t\t\tunsigned int v2 : 1;\n+\t\t\tunsigned int pxe_en : 1;\n+\t\t\tunsigned int mctp_en : 1;\n+\t\t} e;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+/* firmware -> driver */\n struct mbx_fw_cmd_reply {\n-} __rte_cache_aligned;\n+\t/* fw must set: DD, CMP, Error(if error), copy value */\n+\tunsigned short flags;\n+\t/* from command: LB,RD,VFC,BUF,SI,EI,FE */\n+\tunsigned short opcode; /* 2-3: copy from req */\n+\tunsigned short error_code; /* 4-5: 0 if no error */\n+\tunsigned short datalen; /* 6-7: */\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned int cookie_lo; /* 8-11: */\n+\t\t\tunsigned int cookie_hi; /* 12-15: */\n+\t\t};\n+\t\tvoid *cookie;\n+\t};\n+\t/* ===== data ==== [16-64] */\n+\tunion {\n+\t\tstruct phy_abilities phy_abilities;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+#define MBX_REQ_HDR_LEN 24\n+/* driver -> firmware */\n+struct mbx_fw_cmd_req {\n+\tunsigned short flags; /* 0-1 */\n+\tunsigned short opcode; /* 2-3 enum LINK_ADM_CMD */\n+\tunsigned short datalen; /* 4-5 */\n+\tunsigned short ret_value; /* 6-7 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned int cookie_lo; /* 8-11 */\n+\t\t\tunsigned int cookie_hi; /* 12-15 */\n+\t\t};\n+\t\tvoid *cookie;\n+\t};\n+\tunsigned int reply_lo; /* 16-19 5dw */\n+\tunsigned int reply_hi; /* 20-23 */\n+\t/* === data === [24-64] 7dw */\n+\tunion {\n+\t\tstruct {\n+\t\t\tint requester;\n+#define REQUEST_BY_DPDK 0xa1\n+#define REQUEST_BY_DRV 0xa2\n+#define REQUEST_BY_PXE 0xa3\n+\t\t} get_phy_ablity;\n+\n+\t\tstruct {\n+\t\t\tunsigned short enable_stat;\n+\t\t\tunsigned short event_mask; /* enum link_event_mask */\n+\t\t} stat_event_mask;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+static inline void\n+build_phy_abalities_req(struct mbx_fw_cmd_req *req, void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = GET_PHY_ABALITY;\n+\treq->datalen = 0;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->cookie = cookie;\n+}\n+\n+/* enum link_event_mask or */\n+static inline void\n+build_link_set_event_mask(struct mbx_fw_cmd_req *req,\n+\t\t\t unsigned short event_mask,\n+\t\t\t unsigned short enable,\n+\t\t\t void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = SET_EVENT_MASK;\n+\treq->datalen = sizeof(req->stat_event_mask);\n+\treq->cookie = cookie;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->stat_event_mask.event_mask = event_mask;\n+\treq->stat_event_mask.enable_stat = enable;\n+}\n+\n+static inline void\n+build_reset_phy_req(struct mbx_fw_cmd_req *req,\n+\t\t void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = RESET_PHY;\n+\treq->datalen = 0;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->cookie = cookie;\n+}\n \n+int rnp_mbx_get_capability(struct rte_eth_dev *dev,\n+\t\t\t int *lane_mask,\n+\t\t\t int *nic_mode);\n+int rnp_mbx_link_event_enable(struct rte_eth_dev *dev, int enable);\n+int rnp_mbx_fw_reset_phy(struct rte_eth_dev *dev);\n #endif /* __RNP_MBX_FW_H__*/\n", "prefixes": [ "v6", "5/8" ] }