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GET /api/patches/128565/?format=api
{ "id": 128565, "url": "https://patches.dpdk.org/api/patches/128565/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230613102009.2390568-3-gakhil@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613102009.2390568-3-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613102009.2390568-3-gakhil@marvell.com", "date": "2023-06-13T10:19:56", "name": "[v4,02/15] common/cnxk: add MACsec SA configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "0e599327976cbb99795a9b888700e8c8ce737c20", "submitter": { "id": 2094, "url": "https://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230613102009.2390568-3-gakhil@marvell.com/mbox/", "series": [ { "id": 28480, "url": "https://patches.dpdk.org/api/series/28480/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28480", "date": "2023-06-13T10:19:54", "name": "net/cnxk: add MACsec support", "version": 4, "mbox": "https://patches.dpdk.org/series/28480/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/128565/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/128565/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D919A42CA8;\n\tTue, 13 Jun 2023 12:20:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E1B1342D0C;\n\tTue, 13 Jun 2023 12:20:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B18CD41149\n for <dev@dpdk.org>; Tue, 13 Jun 2023 12:20:23 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35D566e9005537; Tue, 13 Jun 2023 03:20:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r65023qqy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Jun 2023 03:20:22 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 13 Jun 2023 03:20:20 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 13 Jun 2023 03:20:20 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id 8B4F25C68E3;\n Tue, 13 Jun 2023 03:20:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gHP4iRk11xbbzV0BPqN2egs1bV2C9463G8IoxkRIZpI=;\n b=GY49TB2S1euf5JpEwx4p7UBLw8Um0X6iEL8yCq1KAcm8vTzsCcMlzM8Jzws+fAr1fZMj\n Aikvok9tBmz3nO16XskLlMSa22hmfpB50qJuc0iu7bUbpfep8+NAr8q9F01ddOIbkmCl\n 75k6Q2fy5FbQau08gDhlhFIB9Ki/dUwOBTdc7e2wv5Fqw+D+6mNO3wLC2jCk/liojdkC\n E3cGDW8l2Q/hhaaH8SDsJ9Y7WHVPnBr209SDaFbcVjJZKU4f4CzGN4TE8tpSOfLJmo1y\n hiwcexWSTLevDuREFShxH9FmAE7b5FkIpGylpUO1kMxcLkcpqDvLG4GfDldhOv8VWwvG mg==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v4 02/15] common/cnxk: add MACsec SA configuration", "Date": "Tue, 13 Jun 2023 15:49:56 +0530", "Message-ID": "<20230613102009.2390568-3-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613102009.2390568-1-gakhil@marvell.com>", "References": "<20230613071614.2259604-1-gakhil@marvell.com>\n <20230613102009.2390568-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "8Tg3DVQmvmuUbTY5haZXbYlHrb1sSHfG", "X-Proofpoint-GUID": "8Tg3DVQmvmuUbTY5haZXbYlHrb1sSHfG", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs to allocate/free MACsec resources\nand APIs to write SA policy.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_mbox.h | 12 ++\n drivers/common/cnxk/roc_mcs.h | 43 ++++++\n drivers/common/cnxk/roc_mcs_sec_cfg.c | 211 ++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 4 +\n 5 files changed, 271 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_mcs_sec_cfg.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex e33c002676..589baf74fe 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -27,6 +27,7 @@ sources = files(\n 'roc_ie_ot.c',\n 'roc_mbox.c',\n 'roc_mcs.c',\n+ 'roc_mcs_sec_cfg.c',\n 'roc_ml.c',\n 'roc_model.c',\n 'roc_nix.c',\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex ef7a7d6513..ab1173e805 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -300,6 +300,7 @@ struct mbox_msghdr {\n \tM(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \\\n \t mcs_alloc_rsrc_rsp) \\\n \tM(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \\\n+\tM(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \\\n \tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n@@ -725,6 +726,17 @@ struct mcs_free_rsrc_req {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_sa_plcy_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io plcy[2][9]; /* Support 2 SA policy */\n+\tuint8_t __io sa_index[2];\n+\tuint8_t __io sa_cnt;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+\n struct mcs_hw_info {\n \tstruct mbox_msghdr hdr;\n \tuint8_t __io num_mcs_blks; /* Number of MCS blocks */\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex 2f06ce2659..ea4c6ddc05 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -7,6 +7,39 @@\n \n #define MCS_AES_GCM_256_KEYLEN 32\n \n+struct roc_mcs_alloc_rsrc_req {\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_cnt; /* Resources count */\n+\tuint8_t dir;\t /* Macsec ingress or egress side */\n+\tuint8_t all;\t /* Allocate all resource type one each */\n+};\n+\n+struct roc_mcs_alloc_rsrc_rsp {\n+\tuint8_t flow_ids[128]; /* Index of reserved entries */\n+\tuint8_t secy_ids[128];\n+\tuint8_t sc_ids[128];\n+\tuint8_t sa_ids[256];\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_cnt; /* No of entries reserved */\n+\tuint8_t dir;\n+\tuint8_t all;\n+};\n+\n+struct roc_mcs_free_rsrc_req {\n+\tuint8_t rsrc_id; /* Index of the entry to be freed */\n+\tuint8_t rsrc_type;\n+\tuint8_t dir;\n+\tuint8_t all; /* Free all the cam resources */\n+};\n+\n+\n+struct roc_mcs_sa_plcy_write_req {\n+\tuint64_t plcy[2][9];\n+\tuint8_t sa_index[2];\n+\tuint8_t sa_cnt;\n+\tuint8_t dir;\n+};\n+\n struct roc_mcs_hw_info {\n \tuint8_t num_mcs_blks; /* Number of MCS blocks */\n \tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n@@ -38,4 +71,14 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs);\n __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx);\n /* HW info get */\n __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info);\n+\n+/* Resource allocation and free */\n+__roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n+\t\t\t\t struct roc_mcs_alloc_rsrc_rsp *rsp);\n+__roc_api int roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req);\n+/* SA policy read and write */\n+__roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n+__roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n #endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c\nnew file mode 100644\nindex 0000000000..041be51b4b\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c\n@@ -0,0 +1,211 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n+\t\t struct roc_mcs_alloc_rsrc_rsp *rsp)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_alloc_rsrc_req *rsrc_req;\n+\tstruct mcs_alloc_rsrc_rsp *rsrc_rsp;\n+\tint rc, i;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL || rsp == NULL)\n+\t\treturn -EINVAL;\n+\n+\trsrc_req = mbox_alloc_msg_mcs_alloc_resources(mcs->mbox);\n+\tif (rsrc_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trsrc_req->rsrc_type = req->rsrc_type;\n+\trsrc_req->rsrc_cnt = req->rsrc_cnt;\n+\trsrc_req->mcs_id = mcs->idx;\n+\trsrc_req->dir = req->dir;\n+\trsrc_req->all = req->all;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsrc_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rsrc_rsp->all) {\n+\t\trsrc_rsp->rsrc_cnt = 1;\n+\t\trsrc_rsp->rsrc_type = 0xFF;\n+\t}\n+\n+\tfor (i = 0; i < rsrc_rsp->rsrc_cnt; i++) {\n+\t\tswitch (rsrc_rsp->rsrc_type) {\n+\t\tcase MCS_RSRC_TYPE_FLOWID:\n+\t\t\trsp->flow_ids[i] = rsrc_rsp->flow_ids[i];\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.tcam_bmap,\n+\t\t\t\t rsp->flow_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SECY:\n+\t\t\trsp->secy_ids[i] = rsrc_rsp->secy_ids[i];\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.secy_bmap,\n+\t\t\t\t rsp->secy_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SC:\n+\t\t\trsp->sc_ids[i] = rsrc_rsp->sc_ids[i];\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.sc_bmap,\n+\t\t\t\t rsp->sc_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sc_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SA:\n+\t\t\trsp->sa_ids[i] = rsrc_rsp->sa_ids[i];\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.sa_bmap,\n+\t\t\t\t rsp->sa_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trsp->flow_ids[i] = rsrc_rsp->flow_ids[i];\n+\t\t\trsp->secy_ids[i] = rsrc_rsp->secy_ids[i];\n+\t\t\trsp->sc_ids[i] = rsrc_rsp->sc_ids[i];\n+\t\t\trsp->sa_ids[i] = rsrc_rsp->sa_ids[i];\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.tcam_bmap,\n+\t\t\t\t rsp->flow_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.secy_bmap,\n+\t\t\t\t rsp->secy_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.sc_bmap,\n+\t\t\t\t rsp->sc_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sc_entries : 0));\n+\t\t\tplt_bitmap_set(priv->dev_rsrc.sa_bmap,\n+\t\t\t\t rsp->sa_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\trsp->rsrc_type = rsrc_rsp->rsrc_type;\n+\trsp->rsrc_cnt = rsrc_rsp->rsrc_cnt;\n+\trsp->dir = rsrc_rsp->dir;\n+\trsp->all = rsrc_rsp->all;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *free_req)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_free_rsrc_req *req;\n+\tstruct msg_rsp *rsp;\n+\tuint32_t pos;\n+\tint i, rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (free_req == NULL)\n+\t\treturn -EINVAL;\n+\n+\treq = mbox_alloc_msg_mcs_free_resources(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->rsrc_id = free_req->rsrc_id;\n+\treq->rsrc_type = free_req->rsrc_type;\n+\treq->mcs_id = mcs->idx;\n+\treq->dir = free_req->dir;\n+\treq->all = free_req->all;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tswitch (free_req->rsrc_type) {\n+\tcase MCS_RSRC_TYPE_FLOWID:\n+\t\tpos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->tcam_entries : 0);\n+\t\tplt_bitmap_clear(priv->dev_rsrc.tcam_bmap, pos);\n+\t\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].tcam_bmap, pos);\n+\n+\t\t\tif (set) {\n+\t\t\t\tplt_bitmap_clear(priv->port_rsrc[i].tcam_bmap, pos);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SECY:\n+\t\tpos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->secy_entries : 0);\n+\t\tplt_bitmap_clear(priv->dev_rsrc.secy_bmap, pos);\n+\t\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, pos);\n+\n+\t\t\tif (set) {\n+\t\t\t\tplt_bitmap_clear(priv->port_rsrc[i].secy_bmap, pos);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SC:\n+\t\tpos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sc_entries : 0);\n+\t\tplt_bitmap_clear(priv->dev_rsrc.sc_bmap, pos);\n+\t\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, pos);\n+\n+\t\t\tif (set) {\n+\t\t\t\tplt_bitmap_clear(priv->port_rsrc[i].sc_bmap, pos);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SA:\n+\t\tpos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sa_entries : 0);\n+\t\tplt_bitmap_clear(priv->dev_rsrc.sa_bmap, pos);\n+\t\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].sa_bmap, pos);\n+\n+\t\t\tif (set) {\n+\t\t\t\tplt_bitmap_clear(priv->port_rsrc[i].sa_bmap, pos);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy)\n+{\n+\tstruct mcs_sa_plcy_write_req *sa;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (sa_plcy == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsa = mbox_alloc_msg_mcs_sa_plcy_write(mcs->mbox);\n+\tif (sa == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tmbox_memcpy(sa->plcy, sa_plcy->plcy, sizeof(uint64_t) * 2 * 9);\n+\tsa->sa_index[0] = sa_plcy->sa_index[0];\n+\tsa->sa_index[1] = sa_plcy->sa_index[1];\n+\tsa->sa_cnt = sa_plcy->sa_cnt;\n+\tsa->mcs_id = mcs->idx;\n+\tsa->dir = sa_plcy->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_sa_plcy_write_req *sa __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 900290b866..bd8a3095f9 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -139,6 +139,10 @@ INTERNAL {\n \troc_mcs_dev_fini;\n \troc_mcs_dev_get;\n \troc_mcs_hw_info_get;\n+\troc_mcs_rsrc_alloc;\n+\troc_mcs_rsrc_free;\n+\troc_mcs_sa_policy_read;\n+\troc_mcs_sa_policy_write;\n \troc_nix_bpf_alloc;\n \troc_nix_bpf_config;\n \troc_nix_bpf_connect;\n", "prefixes": [ "v4", "02/15" ] }