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GET /api/patches/126869/?format=api
{ "id": 126869, "url": "https://patches.dpdk.org/api/patches/126869/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230516063747.3047758-5-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230516063747.3047758-5-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230516063747.3047758-5-michaelba@nvidia.com", "date": "2023-05-16T06:37:44", "name": "[v1,4/7] net/mlx5: reduce modify field encapsulation level size", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1506a5e38e26001dae1f154f3dfce1d001cbd6d9", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230516063747.3047758-5-michaelba@nvidia.com/mbox/", "series": [ { "id": 28001, "url": "https://patches.dpdk.org/api/series/28001/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28001", "date": "2023-05-16T06:37:40", "name": "ethdev: modify field API for multiple headers", "version": 1, "mbox": "https://patches.dpdk.org/series/28001/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126869/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126869/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EF9F642B1F;\n\tTue, 16 May 2023 08:38:28 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8647142D56;\n\tTue, 16 May 2023 08:38:12 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2053.outbound.protection.outlook.com [40.107.94.53])\n by mails.dpdk.org (Postfix) with ESMTP id DE8DA42D3A\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Ori Kam <orika@nvidia.com>, Aman Singh <aman.deep.singh@intel.com>,\n \"Yuying Zhang\" <yuying.zhang@intel.com>, Ferruh Yigit <ferruh.yigit@amd.com>,\n \"Thomas Monjalon\" <thomas@monjalon.net>", "Subject": "[PATCH v1 4/7] net/mlx5: reduce modify field encapsulation level size", "Date": "Tue, 16 May 2023 09:37:44 +0300", "Message-ID": "<20230516063747.3047758-5-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230516063747.3047758-1-michaelba@nvidia.com>", "References": "<20230516063747.3047758-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000C984:EE_|SA1PR12MB7409:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a577ea9c-86bf-42e5-05e7-08db55d81c24", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n nZa/ZTawxvJHJ8oBH69ipkXsP7J1XK5Ijrc0ypCdfm21akeXDCYovNwiwEhaWw1Hgvh9M8itiKFfB6ekH32iPYvRQ7MnbmVkyuiP95yGSqsUKmhfmQ6D/MHa/w/tOZrWJ0C94ajRz1B7kg8Mf6UM0E/kiq53NJR052PjSoeuSvi7Dx5GVdUf55GXC7wBA31ezV5ezyzeOpQDHyiJXTdt383lHHSJbCV7hObs2FkGch1lXFZlt9sLSf+HLn443bdlJtj/vzKHozP1xeuZoKl2vKIk981N9RMdon8oRsckJYF32Fz7kaW9xz2K2CTGuPY9UpkVL51nKgCDQuPdHRdeTj+0s3ljxoqE0ODPd+K7MIDqX3KtH8Pr+bay5hwJTfzQ+T+rXwVWPmlyi656LtqiFgCCtC8f2G6QS6p62KV5F4sEN49y+hdHT7L+/SB3aHyUcU027AWzPSVE4fP0lGvPxbby3eFEkcPnS8HllnTDcMpeBpIxBtq1buMFV4zII0ei4ABoBJk4Aegeri5dvDshuXb5Pj3x2WNjVP5lrdiQum3ROM7QeOIOz/8bQKE5LcCCaVYCVsQIKgVbd/PKredlHT3z1PBnilUaAkql5OXS3E8F7p4BdcV8Z2rfRXwfdUMw96R14Ehv87JnOUxnSbHaNHjpcCv/F5HrHCa5WD/aUFxlRwyMvY5POzaS+BBmTNSuelyseqF0UKj03tnYbydO2F6QQ0nmoKqQelZ3RQo9iZA=", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199021)(36840700001)(40470700004)(46966006)(83380400001)(36860700001)(47076005)(336012)(426003)(478600001)(6666004)(7696005)(54906003)(2616005)(1076003)(26005)(6286002)(186003)(40460700003)(2906002)(36756003)(4326008)(70206006)(82740400003)(6916009)(70586007)(7636003)(356005)(41300700001)(8676002)(82310400005)(8936002)(316002)(55016003)(86362001)(40480700001)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 May 2023 06:38:07.5539 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a577ea9c-86bf-42e5-05e7-08db55d81c24", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000C984.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7409", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The type of \"level\" field in \"rte_flow_action_modify_data\" structure is\nuint32_t for now, but it is going to be changed to uint8_t in the next\npatch.\n\nFor representing encapsulation level, 8 bits are more than enough and\nthis change shouldn't affect the current implementation.\nHowever, when action template is created, the PMD requests to provide\nthis field \"fully masked\" in action mask. The \"fully masked\" value is\ndifferent between uint32_t and uint8_t types.\n\nThis patch reduces all modify field encapsulation level \"fully masked\"\ninitializations to use UINT8_MAX instead of UINT32_MAX. This change will\navoid compilation warning after it will be changed to uint8_t by API.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 22 +++++++++++-----------\n 1 file changed, 11 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7e0ee8d883..1b68a19900 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3565,7 +3565,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"immediate value, pointer and hash result cannot be used as destination\");\n-\tif (mask_conf->dst.level != UINT32_MAX)\n+\tif (mask_conf->dst.level != UINT8_MAX)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\"destination encapsulation level must be fully masked\");\n@@ -3579,7 +3579,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,\n \t\t\t\t\"destination field mask and template are not equal\");\n \tif (action_conf->src.field != RTE_FLOW_FIELD_POINTER &&\n \t action_conf->src.field != RTE_FLOW_FIELD_VALUE) {\n-\t\tif (mask_conf->src.level != UINT32_MAX)\n+\t\tif (mask_conf->src.level != UINT8_MAX)\n \t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"source encapsulation level must be fully masked\");\n@@ -4450,7 +4450,7 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev,\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = RTE_FLOW_FIELD_VLAN_ID,\n-\t\t\t.level = 0xffffffff, .offset = 0xffffffff,\n+\t\t\t.level = 0xff, .offset = 0xffffffff,\n \t\t},\n \t\t.src = {\n \t\t\t.field = RTE_FLOW_FIELD_VALUE,\n@@ -4583,12 +4583,12 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev,\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.src = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.width = UINT32_MAX,\n@@ -5653,7 +5653,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev)\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.src = {\n@@ -5677,12 +5677,12 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev)\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.src = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.width = UINT32_MAX,\n@@ -6009,7 +6009,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev)\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.src = {\n@@ -6182,12 +6182,12 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev)\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n \t\t.dst = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.src = {\n \t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t\t.level = UINT32_MAX,\n+\t\t\t.level = UINT8_MAX,\n \t\t\t.offset = UINT32_MAX,\n \t\t},\n \t\t.width = UINT32_MAX,\n", "prefixes": [ "v1", "4/7" ] }