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GET /api/patches/126813/?format=api
{ "id": 126813, "url": "https://patches.dpdk.org/api/patches/126813/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230511075504.664871-3-dongzhou@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230511075504.664871-3-dongzhou@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230511075504.664871-3-dongzhou@nvidia.com", "date": "2023-05-11T07:55:03", "name": "[v1,2/3] net/mlx5: add support for infiniband BTH match", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3866d6e05dfc5071ced29d6c9efa8ac59ad4c168", "submitter": { "id": 2011, "url": "https://patches.dpdk.org/api/people/2011/?format=api", "name": "Dong Zhou", "email": "dongzhou@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230511075504.664871-3-dongzhou@nvidia.com/mbox/", "series": [ { "id": 27973, "url": "https://patches.dpdk.org/api/series/27973/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27973", "date": "2023-05-11T07:55:01", "name": "add support for infiniband BTH match", "version": 1, "mbox": "https://patches.dpdk.org/series/27973/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126813/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/126813/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 28B6742AD3;\n\tThu, 11 May 2023 09:56:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1641742D69;\n\tThu, 11 May 2023 09:56:18 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2058.outbound.protection.outlook.com [40.107.244.58])\n by mails.dpdk.org (Postfix) with ESMTP id 574F042D64\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dong Zhou <dongzhou@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v1 2/3] net/mlx5: add support for infiniband BTH match", "Date": "Thu, 11 May 2023 10:55:03 +0300", "Message-ID": "<20230511075504.664871-3-dongzhou@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230511075504.664871-1-dongzhou@nvidia.com>", "References": "<20230511075504.664871-1-dongzhou@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT103:EE_|CH3PR12MB7572:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b31c6eb0-a3fc-4bb3-997a-08db51f531d9", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VhNBzRwKxAMBDj3/5RxPXJVrnCVyou+H7C8HovlnUM/ogWhy8PIPpKA0pro0IacQmP0vOkBlBJaGhIPkBeYhTTaKPX/dPsdJ6ONsuP3Z7XzGBySe/UaX9wJ5xJjfTlgL0AiEYi79YcB17nLSf6ukyTPYjcG9AeT+Vt1f05+hm8HfABEjZ1O7nS83QfoqrtevTpn4oMX+pdGdryHv7LtvyS2RxUKk0fbuqpywoxNsA0+ZlTeyexoKjrvdJ5wSU/cq5eyE8wIwjude6AEMXJgNAoiHTXDxc4XjOndq4+0Zu3TZPL6Tx7XCtavg4h+eCoeUtxxHzZqh4hLEP01G4d6vteelqQ5UC6bQ9mJBSEKxw/armTiqqwMZ2OI7QJIFdYDupNsBA8ktNz7UVprcPr29oUx+Zt5fhStglCzeVRw7BowxbbXSPVhytF2i+/yRBbgbxnYv+G9fZWZwys4v9od/NYCkeetwhzS0jFW3QhDthJIlgaqLA49L3XEsceFRaV9L8oIQeuTb+3aRSwFuYh8KXqcl3/3YRf6LimmFj/xecUtDsUE8//FQKPcbuqgXW0yfkX24wWkpKbumtM337SBoADprWUDbZyDW/oXh7QMfQaUI1UOr57KjjG78fnh7inNGYPTNUf1sxD5h5JZd1TpETcggzLURHfiuQSzVyKoMbU1+vCYtfXljwF+p5RCRa4zjfB9IxFyR9yGc5goXDw3D7A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(346002)(396003)(39860400002)(376002)(451199021)(46966006)(40470700004)(36840700001)(4326008)(6636002)(8676002)(82310400005)(70586007)(478600001)(70206006)(41300700001)(82740400003)(8936002)(7696005)(110136005)(316002)(86362001)(5660300002)(54906003)(107886003)(186003)(26005)(1076003)(40460700003)(6286002)(16526019)(2906002)(7636003)(47076005)(55016003)(356005)(426003)(2616005)(83380400001)(336012)(40480700001)(36756003)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 May 2023 07:56:14.6520 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b31c6eb0-a3fc-4bb3-997a-08db51f531d9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT103.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB7572", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support to match opcode and dst_qp fields in\ninfiniband BTH. Currently, only the RoCEv2 packet is supported,\nthe input BTH match item is defaulted to match one RoCEv2 packet.\n\nSigned-off-by: Dong Zhou <dongzhou@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 5 +-\n drivers/net/mlx5/mlx5_flow.h | 6 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 102 ++++++++++++++++++++++++++++++++\n 3 files changed, 111 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ed3d5efbb7..8f55fd59b3 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -932,7 +932,7 @@ struct mlx5_ifc_fte_match_set_misc_bits {\n \tu8 gre_key_h[0x18];\n \tu8 gre_key_l[0x8];\n \tu8 vxlan_vni[0x18];\n-\tu8 reserved_at_b8[0x8];\n+\tu8 bth_opcode[0x8];\n \tu8 geneve_vni[0x18];\n \tu8 lag_rx_port_affinity[0x4];\n \tu8 reserved_at_e8[0x2];\n@@ -945,7 +945,8 @@ struct mlx5_ifc_fte_match_set_misc_bits {\n \tu8 reserved_at_120[0xa];\n \tu8 geneve_opt_len[0x6];\n \tu8 geneve_protocol_type[0x10];\n-\tu8 reserved_at_140[0x20];\n+\tu8 reserved_at_140[0x8];\n+\tu8 bth_dst_qp[0x18];\n \tu8 inner_esp_spi[0x20];\n \tu8 outer_esp_spi[0x20];\n \tu8 reserved_at_1a0[0x60];\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 1d116ea0f6..c1d6a71708 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -227,6 +227,9 @@ enum mlx5_feature_name {\n /* Aggregated affinity item */\n #define MLX5_FLOW_ITEM_AGGR_AFFINITY (UINT64_C(1) << 49)\n \n+/* IB BTH ITEM. */\n+#define MLX5_FLOW_ITEM_IB_BTH (1ull << 51)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -364,6 +367,9 @@ enum mlx5_feature_name {\n #define MLX5_UDP_PORT_VXLAN 4789\n #define MLX5_UDP_PORT_VXLAN_GPE 4790\n \n+/* UDP port numbers for RoCEv2. */\n+#define MLX5_UDP_PORT_ROCEv2 4791\n+\n /* UDP port numbers for GENEVE. */\n #define MLX5_UDP_PORT_GENEVE 6081\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f136f43b0a..b7dc8ecaf7 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7193,6 +7193,65 @@ flow_dv_validate_item_flex(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Validate IB BTH item.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] udp_dport\n+ * UDP destination port\n+ * @param[in] item\n+ * Item specification.\n+ * @param root\n+ * Whether action is on root table.\n+ * @param[out] error\n+ * Pointer to the error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_flow_validate_item_ib_bth(struct rte_eth_dev *dev,\n+\t\t\t uint16_t udp_dport,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t bool root,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_ib_bth *mask = item->mask;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_item_ib_bth *valid_mask;\n+\tint ret;\n+\n+\tvalid_mask = &rte_flow_item_ib_bth_mask;\n+\tif (udp_dport && udp_dport != MLX5_UDP_PORT_ROCEv2)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"protocol filtering not compatible\"\n+\t\t\t\t\t \" with UDP layer\");\n+\tif (mask && (mask->hdr.se || mask->hdr.m || mask->hdr.padcnt ||\n+\t\tmask->hdr.tver || mask->hdr.pkey || mask->hdr.f || mask->hdr.b ||\n+\t\tmask->hdr.rsvd0 || mask->hdr.a || mask->hdr.rsvd1 ||\n+\t\tmask->hdr.psn[0] || mask->hdr.psn[1] || mask->hdr.psn[2]))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"only opcode and dst_qp are supported\");\n+\tif (root || priv->sh->steering_format_version ==\n+\t\tMLX5_STEERING_LOGIC_FORMAT_CONNECTX_5)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t item,\n+\t\t\t\t\t \"IB BTH item is not supported\");\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_ib_bth_mask;\n+\tret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,\n+\t\t\t\t\t(const uint8_t *)valid_mask,\n+\t\t\t\t\tsizeof(struct rte_flow_item_ib_bth),\n+\t\t\t\t\tMLX5_ITEM_RANGE_NOT_ACCEPTED, error);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 0;\n+}\n+\n /**\n * Internal validation function. For validating both actions and items.\n *\n@@ -7700,6 +7759,14 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\t\tret = mlx5_flow_validate_item_ib_bth(dev, udp_dport,\n+\t\t\t\t\t\t\t items, is_root, error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\n+\t\t\tlast_item = MLX5_FLOW_ITEM_IB_BTH;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -10971,6 +11038,37 @@ flow_dv_translate_item_aggr_affinity(void *key,\n \t\t affinity_v->affinity & affinity_m->affinity);\n }\n \n+static void\n+flow_dv_translate_item_ib_bth(void *key,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t int inner, uint32_t key_type)\n+{\n+\tconst struct rte_flow_item_ib_bth *bth_m;\n+\tconst struct rte_flow_item_ib_bth *bth_v;\n+\tvoid *headers_v, *misc_v;\n+\tuint16_t udp_dport;\n+\tchar *qpn_v;\n+\tint i, size;\n+\n+\theaders_v = inner ? MLX5_ADDR_OF(fte_match_param, key, inner_headers) :\n+\t\tMLX5_ADDR_OF(fte_match_param, key, outer_headers);\n+\tif (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {\n+\t\tudp_dport = key_type & MLX5_SET_MATCHER_M ?\n+\t\t\t0xFFFF : MLX5_UDP_PORT_ROCEv2;\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, udp_dport);\n+\t}\n+\tif (MLX5_ITEM_VALID(item, key_type))\n+\t\treturn;\n+\tMLX5_ITEM_UPDATE(item, key_type, bth_v, bth_m, &rte_flow_item_ib_bth_mask);\n+\tmisc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n+\tMLX5_SET(fte_match_set_misc, misc_v, bth_opcode,\n+\t\t bth_v->hdr.opcode & bth_m->hdr.opcode);\n+\tqpn_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, bth_dst_qp);\n+\tsize = sizeof(bth_m->hdr.dst_qp);\n+\tfor (i = 0; i < size; ++i)\n+\t\tqpn_v[i] = bth_m->hdr.dst_qp[i] & bth_v->hdr.dst_qp[i];\n+}\n+\n static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };\n \n #define HEADER_IS_ZERO(match_criteria, headers)\t\t\t\t \\\n@@ -13772,6 +13870,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \t\tflow_dv_translate_item_aggr_affinity(key, items, key_type);\n \t\tlast_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;\n \t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\tflow_dv_translate_item_ib_bth(key, items, tunnel, key_type);\n+\t\tlast_item = MLX5_FLOW_ITEM_IB_BTH;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n", "prefixes": [ "v1", "2/3" ] }