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GET /api/patches/126591/?format=api
{ "id": 126591, "url": "https://patches.dpdk.org/api/patches/126591/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-25-qiming.yang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-25-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-25-qiming.yang@intel.com", "date": "2023-04-27T06:19:55", "name": "[24/30] net/ice/base: cleanup timestamp registers correct", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f2fcec7e8b199b99bc1e1c7b5263e4c1fe216369", "submitter": { "id": 522, "url": "https://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-25-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "https://patches.dpdk.org/api/series/27885/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "https://patches.dpdk.org/series/27885/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126591/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/126591/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96A2242A08;\n\tThu, 27 Apr 2023 08:40:35 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BA73242FC8;\n\tThu, 27 Apr 2023 08:38:30 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 74D5E42FEE\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:28 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:27 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:25 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577508; x=1714113508;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=RTWZG6CbobzfAdjJq9ogTnAwsK38yYIWdCErbBqrIYI=;\n b=UuRGhZ4CKVBjOf38mVpWseTfaLKeab1zxSqqfqVJO8jRchAKfuFXKSEf\n cPRnliVsAwAz0nylR1SAPGIjVIX6ZD6dySCw4ug6dmLwoihUTsZyzTNEJ\n dFLxd8lvYOTXwiJ5UYEepWAYvjrvojv+lxbQjE9GRlfZhs8uobGbTxkvl\n 8pd/eYJiIoGNXZqYE06k52H4GDGIcKdHbiTJtujPvNV2p1gb76Ri1Ngs+\n ZqFLTH8GgeVHRtTO6P4yMmjA4CDo1YeuGnIfhRuk3zts2rVK/ZPqOvD60\n wEt8dho8iiVJB48R6ePTqEIVKiDBHtS4ktrUDCHSIutOz6Vk82wdq14E0 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324391\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324391\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845872\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845872\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Karol Kolacinski <karol.kolacinski@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Subject": "[PATCH 24/30] net/ice/base: cleanup timestamp registers correct", "Date": "Thu, 27 Apr 2023 06:19:55 +0000", "Message-Id": "<20230427062001.478032-25-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "E822 PHY TS registers should not be written and the only way to cleanup\nthem is to reset QUAD memory.\n\nTo ensure that the status bit for the timestamp index is cleared, ensure\nthat ice_clear_phy_tstamp implementations first read the timestamp out.\nImplementations which can write the register continue to do so.\n\nAdd a note to indicate this function should only be called on timestamps\nwhich have their valid bit set.\n\nSigned-off-by: Karol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 54 ++++++++++++++++++-------------\n 1 file changed, 31 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 29840b2b91..e559d4907f 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -1020,34 +1020,31 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)\n }\n \n /**\n- * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block\n+ * ice_clear_phy_tstamp_e822 - Drop a timestamp from the quad block\n * @hw: pointer to the HW struct\n * @quad: the quad to read from\n * @idx: the timestamp index to reset\n *\n- * Clear a timestamp, resetting its valid bit, from the PHY quad block that is\n- * shared between the internal PHYs on the E822 devices.\n+ * Read the timetamp out of the quad to clear its timestamp status bit from\n+ * the PHY quad block that is shared between the internal PHYs of the E822\n+ * devices.\n+ *\n+ * Note that software cannot directly write the quad memory bank registers,\n+ * and must use ice_ptp_reset_ts_memory_quad_e822 for that purpose.\n+ *\n+ * This function should only be called on an idx whose bit is set according to\n+ * ice_get_phy_tx_tstamp_ready.\n */\n static enum ice_status\n ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n {\n \tenum ice_status status;\n-\tu16 lo_addr, hi_addr;\n-\n-\tlo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);\n-\thi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);\n-\n-\tstatus = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear low PTP timestamp register, status %d\\n\",\n-\t\t\t status);\n-\t\treturn status;\n-\t}\n+\tu64 unused_tstamp;\n \n-\tstatus = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);\n+\tstatus = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear high PTP timestamp register, status %d\\n\",\n-\t\t\t status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read the timestamp register for quad %u, idx %u, status %d\\n\",\n+\t\t\t quad, idx, status);\n \t\treturn status;\n \t}\n \n@@ -2926,29 +2923,40 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)\n * @lport: the lport to read from\n * @idx: the timestamp index to reset\n *\n- * Clear a timestamp, resetting its valid bit, from the timestamp block of the\n- * external PHY on the E810 device.\n+ * Read the timestamp and then forcibly overwrite its value to clear the valid\n+ * bit from the timestamp block of the external PHY on the E810 device.\n+ *\n+ * This function should only be called on an idx whose bit is set according to\n+ * ice_get_phy_tx_tstamp_ready.\n */\n static enum ice_status\n ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)\n {\n \tenum ice_status status;\n \tu32 lo_addr, hi_addr;\n+\tu64 unused_tstamp;\n+\n+\tstatus = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read the timestamp register for lport %u, idx %u, status %d\\n\",\n+\t\t\t lport, idx, status);\n+\t\treturn status;\n+\t}\n \n \tlo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);\n \thi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);\n \n \tstatus = ice_write_phy_reg_e810(hw, lo_addr, 0);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear low PTP timestamp register, status %d\\n\",\n-\t\t\t status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear low PTP timestamp register for lport %u, idx %u, status %d\\n\",\n+\t\t\t lport, idx, status);\n \t\treturn status;\n \t}\n \n \tstatus = ice_write_phy_reg_e810(hw, hi_addr, 0);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear high PTP timestamp register, status %d\\n\",\n-\t\t\t status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear high PTP timestamp register for lport %u, idx %u, status %d\\n\",\n+\t\t\t lport, idx, status);\n \t\treturn status;\n \t}\n \n", "prefixes": [ "24/30" ] }