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GET /api/patches/126349/?format=api
{ "id": 126349, "url": "https://patches.dpdk.org/api/patches/126349/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230421065048.106899-6-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230421065048.106899-6-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230421065048.106899-6-beilei.xing@intel.com", "date": "2023-04-21T06:50:43", "name": "[05/10] net/cpfl: support hairpin queue setup and release", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "346d4c34db6050260b7966251eaf0495ca665932", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230421065048.106899-6-beilei.xing@intel.com/mbox/", "series": [ { "id": 27810, "url": "https://patches.dpdk.org/api/series/27810/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27810", "date": "2023-04-21T06:50:38", "name": "add hairpin queue support", "version": 1, "mbox": "https://patches.dpdk.org/series/27810/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126349/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126349/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 764BD429A9;\n\tFri, 21 Apr 2023 09:14:28 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 424DB42D2F;\n\tFri, 21 Apr 2023 09:14:02 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id A6B3542D2F\n for <dev@dpdk.org>; Fri, 21 Apr 2023 09:14:00 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2023 00:13:59 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2023 00:13:57 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682061240; x=1713597240;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=qajTJ8Odv/ZNSadz28uM+4imjGOqqx6eA53lPbWo4Pw=;\n b=cYKVER/CKyWvHzzZXXmvoi9sWF3kuBT6pGL2FsY8AC/5Y8oA17dGaS0/\n PsTIqVLG4xaMifBlV0CI2vr+WAkxW1gx5Q4OenOtkxciQtbWvinsKAx7D\n /c61+/3gmhbn6R5FnCvIGEj0x1xIC1S59YqHYlmJ68pWyt91paI4MKI18\n 3yiyu6h+q8diRZDV7RxOSKEWGmXUI0R972feL1HRrbk8xcnsPIJfU8rAn\n oYCw9FxvLWIE0E5LtrohfwZA60N/6VKlWotRv4eONRoQHbCcl45kzPCpa\n rKSzpBETzSxMRG201RMXl+0EVxw4D/qGNIRrVfVP9vnqMh8hhhrhPNeWQ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10686\"; a=\"326260067\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"326260067\"", "E=McAfee;i=\"6600,9927,10686\"; a=\"722669115\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"722669115\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Xiao Wang <xiao.w.wang@intel.com>", "Subject": "[PATCH 05/10] net/cpfl: support hairpin queue setup and release", "Date": "Fri, 21 Apr 2023 06:50:43 +0000", "Message-Id": "<20230421065048.106899-6-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230421065048.106899-1-beilei.xing@intel.com>", "References": "<20230421065048.106899-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nSupport hairpin Rx/Tx queue setup and release.\n\nSigned-off-by: Xiao Wang <xiao.w.wang@intel.com>\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 6 +\n drivers/net/cpfl/cpfl_ethdev.h | 10 +\n drivers/net/cpfl/cpfl_rxtx.c | 373 +++++++++++++++++++++++-\n drivers/net/cpfl/cpfl_rxtx.h | 28 ++\n drivers/net/cpfl/cpfl_rxtx_vec_common.h | 4 +\n 5 files changed, 420 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex ad5ddebd3a..d3300f17cc 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -878,6 +878,10 @@ cpfl_dev_close(struct rte_eth_dev *dev)\n \tstruct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);\n \n \tcpfl_dev_stop(dev);\n+\tif (cpfl_vport->p2p_mp) {\n+\t\trte_mempool_free(cpfl_vport->p2p_mp);\n+\t\tcpfl_vport->p2p_mp = NULL;\n+\t}\n \n \tcpfl_p2p_queue_grps_del(vport);\n \n@@ -919,6 +923,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.xstats_get_names\t\t= cpfl_dev_xstats_get_names,\n \t.xstats_reset\t\t\t= cpfl_dev_xstats_reset,\n \t.hairpin_cap_get\t\t= cpfl_hairpin_cap_get,\n+\t.rx_hairpin_queue_setup\t\t= cpfl_rx_hairpin_queue_setup,\n+\t.tx_hairpin_queue_setup\t\t= cpfl_tx_hairpin_queue_setup,\n };\n \n static int\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex 5e2e7a1bfb..2cc8790da0 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -88,6 +88,16 @@ struct p2p_queue_chunks_info {\n struct cpfl_vport {\n \tstruct idpf_vport base;\n \tstruct p2p_queue_chunks_info p2p_q_chunks_info;\n+\n+\tstruct rte_mempool *p2p_mp;\n+\n+\tuint16_t nb_data_rxq;\n+\tuint16_t nb_data_txq;\n+\tuint16_t nb_p2p_rxq;\n+\tuint16_t nb_p2p_txq;\n+\n+\tstruct idpf_rx_queue *p2p_rx_bufq;\n+\tstruct idpf_tx_queue *p2p_tx_complq;\n };\n \n struct cpfl_adapter_ext {\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex a441e2ffbe..64ed331a6d 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -10,6 +10,79 @@\n #include \"cpfl_rxtx.h\"\n #include \"cpfl_rxtx_vec_common.h\"\n \n+uint16_t\n+cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset)\n+{\n+\treturn start_qid + offset;\n+}\n+\n+uint64_t\n+cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t tail_spacing)\n+{\n+\treturn tail_start + offset * tail_spacing;\n+}\n+\n+static inline void\n+cpfl_tx_hairpin_descq_reset(struct idpf_tx_queue *txq)\n+{\n+\tuint32_t i, size;\n+\n+\tif (!txq) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Pointer to txq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tsize = txq->nb_tx_desc * CPFL_P2P_DESC_LEN;\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)txq->desc_ring)[i] = 0;\n+}\n+\n+static inline void\n+cpfl_tx_hairpin_complq_reset(struct idpf_tx_queue *cq)\n+{\n+\tuint32_t i, size;\n+\n+\tif (!cq) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Pointer to complq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tsize = cq->nb_tx_desc * CPFL_P2P_DESC_LEN;\n+\tfor (i = 0; i < size; i++)\n+\t\t((volatile char *)cq->compl_ring)[i] = 0;\n+}\n+\n+static inline void\n+cpfl_rx_hairpin_descq_reset(struct idpf_rx_queue *rxq)\n+{\n+\tuint16_t len;\n+\tuint32_t i;\n+\n+\tif (!rxq)\n+\t\treturn;\n+\n+\tlen = rxq->nb_rx_desc;\n+\tfor (i = 0; i < len * CPFL_P2P_DESC_LEN; i++)\n+\t\t((volatile char *)rxq->rx_ring)[i] = 0;\n+}\n+\n+static inline void\n+cpfl_rx_hairpin_bufq_reset(struct idpf_rx_queue *rxbq)\n+{\n+\tuint16_t len;\n+\tuint32_t i;\n+\n+\tif (!rxbq)\n+\t\treturn;\n+\n+\tlen = rxbq->nb_rx_desc;\n+\tfor (i = 0; i < len * CPFL_P2P_DESC_LEN; i++)\n+\t\t((volatile char *)rxbq->rx_ring)[i] = 0;\n+\n+\trxbq->bufq1 = NULL;\n+\trxbq->bufq2 = NULL;\n+}\n+\n static uint64_t\n cpfl_rx_offload_convert(uint64_t offload)\n {\n@@ -233,7 +306,10 @@ cpfl_rx_queue_release(void *rxq)\n \n \t/* Split queue */\n \tif (!q->adapter->is_rx_singleq) {\n-\t\tif (q->bufq2)\n+\t\t/* the mz is shared between Tx/Rx hairpin, let Rx_release\n+\t\t * free the buf, q->bufq1->mz and q->mz.\n+\t\t */\n+\t\tif (!cpfl_rxq->hairpin_info.hairpin_q && q->bufq2)\n \t\t\tcpfl_rx_split_bufq_release(q->bufq2);\n \n \t\tif (q->bufq1)\n@@ -384,6 +460,7 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t}\n \t}\n \n+\tcpfl_vport->nb_data_rxq++;\n \trxq->q_set = true;\n \tdev->data->rx_queues[queue_idx] = cpfl_rxq;\n \n@@ -547,6 +624,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \ttxq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start +\n \t\t\tqueue_idx * vport->chunks_info.tx_qtail_spacing);\n \ttxq->ops = &def_txq_ops;\n+\tcpfl_vport->nb_data_txq++;\n \ttxq->q_set = true;\n \tdev->data->tx_queues[queue_idx] = cpfl_txq;\n \n@@ -561,6 +639,297 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \treturn ret;\n }\n \n+static int\n+cpfl_rx_hairpin_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *bufq,\n+\t\t\t uint16_t logic_qid, uint16_t nb_desc)\n+{\n+\tstruct cpfl_vport *cpfl_vport =\n+\t (struct cpfl_vport *)dev->data->dev_private;\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct rte_mempool *mp;\n+\tchar pool_name[RTE_MEMPOOL_NAMESIZE];\n+\n+\tmp = cpfl_vport->p2p_mp;\n+\tif (!mp) {\n+\t\tsnprintf(pool_name, RTE_MEMPOOL_NAMESIZE, \"p2p_mb_pool_%u\",\n+\t\t\t dev->data->port_id);\n+\t\tmp = rte_pktmbuf_pool_create(pool_name, CPFL_P2P_NB_MBUF, CPFL_P2P_CACHE_SIZE,\n+\t\t\t\t\t 0, CPFL_P2P_MBUF_SIZE, dev->device->numa_node);\n+\t\tif (!mp) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate mbuf pool for p2p\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tcpfl_vport->p2p_mp = mp;\n+\t}\n+\n+\tbufq->mp = mp;\n+\tbufq->nb_rx_desc = nb_desc;\n+\tbufq->queue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.rx_buf_start_qid, logic_qid);\n+\tbufq->port_id = dev->data->port_id;\n+\tbufq->adapter = adapter;\n+\tbufq->rx_buf_len = CPFL_P2P_MBUF_SIZE - RTE_PKTMBUF_HEADROOM;\n+\n+\tbufq->sw_ring = rte_zmalloc(\"sw ring\",\n+\t\t\t\t sizeof(struct rte_mbuf *) * nb_desc,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!bufq->sw_ring) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for SW ring\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbufq->q_set = true;\n+\tbufq->ops = &def_rxq_ops;\n+\n+\treturn 0;\n+}\n+\n+int\n+cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc,\n+\t\t\t const struct rte_eth_hairpin_conf *conf)\n+{\n+\tstruct cpfl_vport *cpfl_vport = (struct cpfl_vport *)dev->data->dev_private;\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tstruct idpf_adapter *adapter_base = vport->adapter;\n+\tuint16_t logic_qid = cpfl_vport->nb_p2p_rxq;\n+\tstruct cpfl_rxq_hairpin_info *hairpin_info;\n+\tstruct cpfl_rx_queue *cpfl_rxq;\n+\tstruct idpf_rx_queue *bufq1 = NULL;\n+\tstruct idpf_rx_queue *rxq;\n+\tuint16_t peer_port, peer_q;\n+\tuint16_t qid;\n+\tint ret;\n+\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\tPMD_INIT_LOG(ERR, \"Only spilt queue model supports hairpin queue.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->peer_count != 1) {\n+\t\tPMD_INIT_LOG(ERR, \"Can't support Rx hairpin queue peer count %d\", conf->peer_count);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpeer_port = conf->peers[0].port;\n+\tpeer_q = conf->peers[0].queue;\n+\n+\tif (nb_desc % CPFL_ALIGN_RING_DESC != 0 ||\n+\t nb_desc > CPFL_MAX_RING_DESC ||\n+\t nb_desc < CPFL_MIN_RING_DESC) {\n+\t\tPMD_INIT_LOG(ERR, \"Number (%u) of receive descriptors is invalid\", nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Free memory if needed */\n+\tif (dev->data->rx_queues[queue_idx]) {\n+\t\tcpfl_rx_queue_release(dev->data->rx_queues[queue_idx]);\n+\t\tdev->data->rx_queues[queue_idx] = NULL;\n+\t}\n+\n+\t/* Setup Rx description queue */\n+\tcpfl_rxq = rte_zmalloc_socket(\"cpfl hairpin rxq\",\n+\t\t\t\t sizeof(struct cpfl_rx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t SOCKET_ID_ANY);\n+\tif (!cpfl_rxq) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for rx queue data structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trxq = &cpfl_rxq->base;\n+\thairpin_info = &cpfl_rxq->hairpin_info;\n+\trxq->nb_rx_desc = nb_desc * 2;\n+\trxq->queue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.rx_start_qid, logic_qid);\n+\trxq->port_id = dev->data->port_id;\n+\trxq->adapter = adapter_base;\n+\trxq->rx_buf_len = CPFL_P2P_MBUF_SIZE - RTE_PKTMBUF_HEADROOM;\n+\thairpin_info->hairpin_q = true;\n+\thairpin_info->peer_txp = peer_port;\n+\thairpin_info->peer_txq_id = peer_q;\n+\n+\tif (conf->manual_bind != 0)\n+\t\thairpin_info->manual_bind = true;\n+\telse\n+\t\thairpin_info->manual_bind = false;\n+\n+\t/* setup 1 Rx buffer queue for the 1st hairpin rxq */\n+\tif (logic_qid == 0) {\n+\t\tbufq1 = rte_zmalloc_socket(\"hairpin rx bufq1\",\n+\t\t\t\t\t sizeof(struct idpf_rx_queue),\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t\t SOCKET_ID_ANY);\n+\t\tif (!bufq1) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for hairpin Rx buffer queue 1.\");\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto err_alloc_bufq1;\n+\t\t}\n+\t\tqid = 2 * logic_qid;\n+\t\tret = cpfl_rx_hairpin_bufq_setup(dev, bufq1, qid, nb_desc);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to setup hairpin Rx buffer queue 1\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_setup_bufq1;\n+\t\t}\n+\t\tcpfl_vport->p2p_rx_bufq = bufq1;\n+\t}\n+\n+\trxq->bufq1 = cpfl_vport->p2p_rx_bufq;\n+\trxq->bufq2 = NULL;\n+\n+\tcpfl_vport->nb_p2p_rxq++;\n+\trxq->q_set = true;\n+\tdev->data->rx_queues[queue_idx] = cpfl_rxq;\n+\n+\treturn 0;\n+\n+err_setup_bufq1:\n+\trte_free(bufq1);\n+err_alloc_bufq1:\n+\trte_free(rxq);\n+\n+\treturn ret;\n+}\n+\n+int\n+cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc,\n+\t\t\t const struct rte_eth_hairpin_conf *conf)\n+{\n+\tstruct cpfl_vport *cpfl_vport =\n+\t (struct cpfl_vport *)dev->data->dev_private;\n+\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tstruct idpf_adapter *adapter_base = vport->adapter;\n+\tuint16_t logic_qid = cpfl_vport->nb_p2p_txq;\n+\tstruct cpfl_txq_hairpin_info *hairpin_info;\n+\tstruct idpf_hw *hw = &adapter_base->hw;\n+\tstruct cpfl_tx_queue *cpfl_txq;\n+\tstruct idpf_tx_queue *txq, *cq;\n+\tconst struct rte_memzone *mz;\n+\tuint32_t ring_size;\n+\tuint16_t peer_port, peer_q;\n+\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\tPMD_INIT_LOG(ERR, \"Only spilt queue model supports hairpin queue.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->peer_count != 1) {\n+\t\tPMD_INIT_LOG(ERR, \"Can't support Tx hairpin queue peer count %d\", conf->peer_count);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpeer_port = conf->peers[0].port;\n+\tpeer_q = conf->peers[0].queue;\n+\n+\tif (nb_desc % CPFL_ALIGN_RING_DESC != 0 ||\n+\t nb_desc > CPFL_MAX_RING_DESC ||\n+\t nb_desc < CPFL_MIN_RING_DESC) {\n+\t\tPMD_INIT_LOG(ERR, \"Number (%u) of transmit descriptors is invalid\",\n+\t\t\t nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Free memory if needed. */\n+\tif (dev->data->tx_queues[queue_idx]) {\n+\t\tcpfl_tx_queue_release(dev->data->tx_queues[queue_idx]);\n+\t\tdev->data->tx_queues[queue_idx] = NULL;\n+\t}\n+\n+\t/* Allocate the TX queue data structure. */\n+\tcpfl_txq = rte_zmalloc_socket(\"cpfl hairpin txq\",\n+\t\t\t\t sizeof(struct cpfl_tx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t SOCKET_ID_ANY);\n+\tif (!cpfl_txq) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for tx queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq = &cpfl_txq->base;\n+\thairpin_info = &cpfl_txq->hairpin_info;\n+\t/* Txq ring length should be 2 times of Tx completion queue size. */\n+\ttxq->nb_tx_desc = nb_desc * 2;\n+\ttxq->queue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.tx_start_qid, logic_qid);\n+\ttxq->port_id = dev->data->port_id;\n+\thairpin_info->hairpin_q = true;\n+\thairpin_info->peer_rxp = peer_port;\n+\thairpin_info->peer_rxq_id = peer_q;\n+\n+\tif (conf->manual_bind != 0)\n+\t\thairpin_info->manual_bind = true;\n+\telse\n+\t\thairpin_info->manual_bind = false;\n+\n+\t/* Always Tx hairpin queue allocates Tx HW ring */\n+\tring_size = RTE_ALIGN(txq->nb_tx_desc * CPFL_P2P_DESC_LEN,\n+\t\t\t CPFL_DMA_MEM_ALIGN);\n+\tmz = rte_eth_dma_zone_reserve(dev, \"hairpin_tx_ring\", logic_qid,\n+\t\t\t\t ring_size + CPFL_P2P_RING_BUF,\n+\t\t\t\t CPFL_RING_BASE_ALIGN,\n+\t\t\t\t dev->device->numa_node);\n+\tif (!mz) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to reserve DMA memory for TX\");\n+\t\trte_free(txq->sw_ring);\n+\t\trte_free(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq->tx_ring_phys_addr = mz->iova;\n+\ttxq->desc_ring = mz->addr;\n+\ttxq->mz = mz;\n+\n+\tcpfl_tx_hairpin_descq_reset(txq);\n+\ttxq->qtx_tail = hw->hw_addr +\n+\t\tcpfl_hw_qtail_get(cpfl_vport->p2p_q_chunks_info.tx_qtail_start,\n+\t\t\t\t logic_qid, cpfl_vport->p2p_q_chunks_info.tx_qtail_spacing);\n+\ttxq->ops = &def_txq_ops;\n+\n+\tif (cpfl_vport->p2p_tx_complq == NULL) {\n+\t\tcq = rte_zmalloc_socket(\"cpfl hairpin cq\",\n+\t\t\t\t\tsizeof(struct idpf_tx_queue),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\t\tdev->device->numa_node);\n+\t\tif (!cq) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for tx queue structure\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tcq->nb_tx_desc = nb_desc;\n+\t\tcq->queue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.tx_compl_start_qid, 0);\n+\t\tcq->port_id = dev->data->port_id;\n+\n+\t\t/* Tx completion queue always allocates the HW ring */\n+\t\tring_size = RTE_ALIGN(cq->nb_tx_desc * CPFL_P2P_DESC_LEN,\n+\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\tmz = rte_eth_dma_zone_reserve(dev, \"hairpin_tx_compl_ring\", logic_qid,\n+\t\t\t\t\t ring_size + CPFL_P2P_RING_BUF,\n+\t\t\t\t\t CPFL_RING_BASE_ALIGN,\n+\t\t\t\t\t dev->device->numa_node);\n+\t\tif (!mz) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to reserve DMA memory for TX completion queue\");\n+\t\t\trte_free(txq->sw_ring);\n+\t\t\trte_free(txq);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tcq->tx_ring_phys_addr = mz->iova;\n+\t\tcq->compl_ring = mz->addr;\n+\t\tcq->mz = mz;\n+\n+\t\tcpfl_tx_hairpin_complq_reset(cq);\n+\t\tcpfl_vport->p2p_tx_complq = cq;\n+\t}\n+\n+\ttxq->complq = cpfl_vport->p2p_tx_complq;\n+\n+\tcpfl_vport->nb_p2p_txq++;\n+\ttxq->q_set = true;\n+\tdev->data->tx_queues[queue_idx] = cpfl_txq;\n+\n+\treturn 0;\n+}\n+\n int\n cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n@@ -864,6 +1233,8 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)\n \t\tif (vport->rx_vec_allowed) {\n \t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\t\t\tcpfl_rxq = dev->data->rx_queues[i];\n+\t\t\t\tif (cpfl_rxq->hairpin_info.hairpin_q)\n+\t\t\t\t\tcontinue;\n \t\t\t\t(void)idpf_qc_splitq_rx_vec_setup(&cpfl_rxq->base);\n \t\t\t}\n #ifdef CC_AVX512_SUPPORT\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex 3a87a1f4b3..d844c9f057 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -13,6 +13,7 @@\n #define CPFL_MIN_RING_DESC\t32\n #define CPFL_MAX_RING_DESC\t4096\n #define CPFL_DMA_MEM_ALIGN\t4096\n+#define CPFL_P2P_DESC_LEN\t\t16\n #define CPFL_MAX_HAIRPINQ_RX_2_TX\t1\n #define CPFL_MAX_HAIRPINQ_TX_2_RX\t1\n #define CPFL_MAX_HAIRPINQ_NB_DESC\t1024\n@@ -21,6 +22,10 @@\n #define CPFL_P2P_NB_TX_COMPLQ\t\t1\n #define CPFL_P2P_NB_QUEUE_GRPS\t\t1\n #define CPFL_P2P_QUEUE_GRP_ID\t\t1\n+#define CPFL_P2P_NB_MBUF\t\t4096\n+#define CPFL_P2P_CACHE_SIZE\t\t250\n+#define CPFL_P2P_MBUF_SIZE\t\t2048\n+#define CPFL_P2P_RING_BUF\t\t128\n /* Base address of the HW descriptor ring should be 128B aligned. */\n #define CPFL_RING_BASE_ALIGN\t128\n \n@@ -31,12 +36,28 @@\n \n #define CPFL_SUPPORT_CHAIN_NUM 5\n \n+struct cpfl_rxq_hairpin_info {\n+\tbool hairpin_q;\t\t/* if rx queue is a hairpin queue */\n+\tbool manual_bind;\t/* for cross vport */\n+\tuint16_t peer_txp;\n+\tuint16_t peer_txq_id;\n+};\n+\n struct cpfl_rx_queue {\n \tstruct idpf_rx_queue base;\n+\tstruct cpfl_rxq_hairpin_info hairpin_info;\n+};\n+\n+struct cpfl_txq_hairpin_info {\n+\tbool hairpin_q;\t\t/* if tx queue is a hairpin queue */\n+\tbool manual_bind;\t/* for cross vport */\n+\tuint16_t peer_rxp;\n+\tuint16_t peer_rxq_id;\n };\n \n struct cpfl_tx_queue {\n \tstruct idpf_tx_queue base;\n+\tstruct cpfl_txq_hairpin_info hairpin_info;\n };\n \n int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n@@ -57,4 +78,11 @@ void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n void cpfl_set_rx_function(struct rte_eth_dev *dev);\n void cpfl_set_tx_function(struct rte_eth_dev *dev);\n+uint16_t cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset);\n+uint64_t cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t tail_spacing);\n+int cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t\tuint16_t nb_desc, const struct rte_eth_hairpin_conf *conf);\n+int cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t\tuint16_t nb_desc,\n+\t\t\t\tconst struct rte_eth_hairpin_conf *conf);\n #endif /* _CPFL_RXTX_H_ */\ndiff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\nindex 5690b17911..d8e9191196 100644\n--- a/drivers/net/cpfl/cpfl_rxtx_vec_common.h\n+++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\n@@ -85,6 +85,8 @@ cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev)\n \t\tcpfl_rxq = dev->data->rx_queues[i];\n \t\tdefault_ret = cpfl_rx_vec_queue_default(&cpfl_rxq->base);\n \t\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\t\tif (cpfl_rxq->hairpin_info.hairpin_q)\n+\t\t\t\tcontinue;\n \t\t\tsplitq_ret = cpfl_rx_splitq_vec_default(&cpfl_rxq->base);\n \t\t\tret = splitq_ret && default_ret;\n \t\t} else {\n@@ -106,6 +108,8 @@ cpfl_tx_vec_dev_check_default(struct rte_eth_dev *dev)\n \n \tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n \t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\tif (cpfl_txq->hairpin_info.hairpin_q)\n+\t\t\tcontinue;\n \t\tret = cpfl_tx_vec_queue_default(&cpfl_txq->base);\n \t\tif (ret == CPFL_SCALAR_PATH)\n \t\t\treturn CPFL_SCALAR_PATH;\n", "prefixes": [ "05/10" ] }