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GET /api/patches/126211/?format=api
{ "id": 126211, "url": "https://patches.dpdk.org/api/patches/126211/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com", "date": "2023-04-18T05:11:05", "name": "[1/2] net/iavf: add Tx AVX2 offload path", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "30f0325bb281caf8e4dd271b68dcf1b9a5756a30", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 27748, "url": "https://patches.dpdk.org/api/series/27748/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27748", "date": "2023-04-18T05:11:04", "name": "add offload path on iavf AVX2", "version": 1, "mbox": "https://patches.dpdk.org/series/27748/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126211/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/126211/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D1B0C42977;\n\tTue, 18 Apr 2023 07:43:08 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1A87942D16;\n\tTue, 18 Apr 2023 07:43:05 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 1F46E40EDF\n for <dev@dpdk.org>; Tue, 18 Apr 2023 07:43:02 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Apr 2023 22:43:02 -0700", "from dpdk-wenzhuo-cascadelake.sh.intel.com ([10.67.110.255])\n by fmsmga006.fm.intel.com with ESMTP; 17 Apr 2023 22:43:01 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1681796583; x=1713332583;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=a7K2k4w8bhMFWQnZGfWuzZeZE341GX1Hg1oIhfiPkOg=;\n b=GjKgLnneJH8Isa0nAvTG2hZOaUHZKZe5s1dVu4vwsqaQo52qGqBj86Vk\n ykSRb2YQtwwGwzFyfG02Jjlyr20Cd5qmDgM3wUrnT0QzXP7QfnppjuP/R\n kqR4hccgglE281P8s3PBk3xE232OG63QGNFTYlADDPkP/v0Sb0C9r07tA\n TdUgGrH/UHCt5QW2oSsLbnE9auy2NI766R14MX62q5U+w/rmFjIGM1bS5\n xzzQQbWFOsyrnmIACBV0mzvHRUiT6GsZ+jOHZlVjniIHOiJcdb742h9Yq\n qVp31s3usKDsSJFxmpSKzO42uLXe3KLgoO/w0e5uPdP6Lai3poyeIpDyp w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10683\"; a=\"347830532\"", "E=Sophos;i=\"5.99,206,1677571200\"; d=\"scan'208\";a=\"347830532\"", "E=McAfee;i=\"6600,9927,10683\"; a=\"937115687\"", "E=Sophos;i=\"5.99,206,1677571200\"; d=\"scan'208\";a=\"937115687\"" ], "X-ExtLoop1": "1", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "Subject": "[PATCH 1/2] net/iavf: add Tx AVX2 offload path", "Date": "Tue, 18 Apr 2023 13:11:05 +0800", "Message-Id": "<1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1681794666-68144-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1681794666-68144-1-git-send-email-wenzhuo.lu@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add a specific path for TX AVX2.\nIn this path, support the HW offload features, like,\nchecksum insertion, VLAN insertion.\nThis path is chosen automatically according to the\nconfiguration.\n\n'inline' is used, then the duplicate code is generated\nby the compiler.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/iavf/iavf_rxtx.c | 33 ++++++++++------\n drivers/net/iavf/iavf_rxtx.h | 2 +\n drivers/net/iavf/iavf_rxtx_vec_avx2.c | 54 +++++++++++++++++++--------\n 3 files changed, 62 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\nindex b1d0fbceb6..6cadecfad9 100644\n--- a/drivers/net/iavf/iavf_rxtx.c\n+++ b/drivers/net/iavf/iavf_rxtx.c\n@@ -3876,14 +3876,14 @@ iavf_set_tx_function(struct rte_eth_dev *dev)\n \n \tif (check_ret >= 0 &&\n \t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n-\t\t/* SSE and AVX2 not support offload path yet. */\n+\t\t/* SSE not support offload path yet. */\n \t\tif (check_ret == IAVF_VECTOR_PATH) {\n \t\t\tuse_sse = true;\n-\t\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n-\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n-\t\t\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)\n-\t\t\t\tuse_avx2 = true;\n \t\t}\n+\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n+\t\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)\n+\t\t\tuse_avx2 = true;\n #ifdef CC_AVX512_SUPPORT\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n \t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&\n@@ -3894,15 +3894,24 @@ iavf_set_tx_function(struct rte_eth_dev *dev)\n \t\tif (!use_sse && !use_avx2 && !use_avx512)\n \t\t\tgoto normal;\n \n-\t\tif (!use_avx512) {\n-\t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n-\t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n+\t\tdev->tx_pkt_prepare = NULL;\n+\t\tif (use_sse) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Using Vector Tx (port %d).\",\n \t\t\t\t dev->data->port_id);\n-\t\t\tdev->tx_pkt_burst = use_avx2 ?\n-\t\t\t\t\t iavf_xmit_pkts_vec_avx2 :\n-\t\t\t\t\t iavf_xmit_pkts_vec;\n+\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec;\n+\t\t}\n+\t\tif (use_avx2) {\n+\t\t\tif (check_ret == IAVF_VECTOR_PATH) {\n+\t\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2;\n+\t\t\t\tPMD_DRV_LOG(DEBUG, \"Using AVX2 Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t} else {\n+\t\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2_offload;\n+\t\t\t\tdev->tx_pkt_prepare = iavf_prep_pkts;\n+\t\t\t\tPMD_DRV_LOG(DEBUG, \"Using AVX2 OFFLOAD Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t}\n \t\t}\n-\t\tdev->tx_pkt_prepare = NULL;\n #ifdef CC_AVX512_SUPPORT\n \t\tif (use_avx512) {\n \t\t\tif (check_ret == IAVF_VECTOR_PATH) {\ndiff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h\nindex 09e2127db0..85801160e1 100644\n--- a/drivers/net/iavf/iavf_rxtx.h\n+++ b/drivers/net/iavf/iavf_rxtx.h\n@@ -693,6 +693,8 @@ uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t uint16_t nb_pkts);\n+uint16_t iavf_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts);\n int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);\n int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);\n int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\nindex b4ebac9d34..c17b96008b 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c\n@@ -1426,30 +1426,32 @@ iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,\n \t\t\t\trx_pkts + retval, nb_pkts);\n }\n \n-static inline void\n+static __rte_always_inline void\n iavf_vtx1(volatile struct iavf_tx_desc *txdp,\n-\t struct rte_mbuf *pkt, uint64_t flags)\n+\t struct rte_mbuf *pkt, uint64_t flags, bool offload)\n {\n \tuint64_t high_qw =\n \t\t(IAVF_TX_DESC_DTYPE_DATA |\n \t\t ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |\n \t\t ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));\n+\tif (offload)\n+\t\tiavf_txd_enable_offload(pkt, &high_qw);\n \n \t__m128i descriptor = _mm_set_epi64x(high_qw,\n \t\t\t\tpkt->buf_iova + pkt->data_off);\n \t_mm_store_si128((__m128i *)txdp, descriptor);\n }\n \n-static inline void\n+static __rte_always_inline void\n iavf_vtx(volatile struct iavf_tx_desc *txdp,\n-\t struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n+\t struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags, bool offload)\n {\n \tconst uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |\n \t\t\t((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));\n \n \t/* if unaligned on 32-bit boundary, do one to align */\n \tif (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {\n-\t\tiavf_vtx1(txdp, *pkt, flags);\n+\t\tiavf_vtx1(txdp, *pkt, flags, offload);\n \t\tnb_pkts--, txdp++, pkt++;\n \t}\n \n@@ -1459,18 +1461,26 @@ iavf_vtx(volatile struct iavf_tx_desc *txdp,\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[3]->data_len <<\n \t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[3], &hi_qw3);\n \t\tuint64_t hi_qw2 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[2]->data_len <<\n \t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[2], &hi_qw2);\n \t\tuint64_t hi_qw1 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[1]->data_len <<\n \t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[1], &hi_qw1);\n \t\tuint64_t hi_qw0 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[0]->data_len <<\n \t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[0], &hi_qw0);\n \n \t\t__m256i desc2_3 =\n \t\t\t_mm256_set_epi64x\n@@ -1490,14 +1500,14 @@ iavf_vtx(volatile struct iavf_tx_desc *txdp,\n \n \t/* do any last ones */\n \twhile (nb_pkts) {\n-\t\tiavf_vtx1(txdp, *pkt, flags);\n+\t\tiavf_vtx1(txdp, *pkt, flags, offload);\n \t\ttxdp++, pkt++, nb_pkts--;\n \t}\n }\n \n-static inline uint16_t\n+static __rte_always_inline uint16_t\n iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t nb_pkts)\n+\t\t\t uint16_t nb_pkts, bool offload)\n {\n \tstruct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;\n \tvolatile struct iavf_tx_desc *txdp;\n@@ -1524,11 +1534,11 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (nb_commit >= n) {\n \t\ttx_backlog_entry(txep, tx_pkts, n);\n \n-\t\tiavf_vtx(txdp, tx_pkts, n - 1, flags);\n+\t\tiavf_vtx(txdp, tx_pkts, n - 1, flags, offload);\n \t\ttx_pkts += (n - 1);\n \t\ttxdp += (n - 1);\n \n-\t\tiavf_vtx1(txdp, *tx_pkts++, rs);\n+\t\tiavf_vtx1(txdp, *tx_pkts++, rs, offload);\n \n \t\tnb_commit = (uint16_t)(nb_commit - n);\n \n@@ -1542,7 +1552,7 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \ttx_backlog_entry(txep, tx_pkts, nb_commit);\n \n-\tiavf_vtx(txdp, tx_pkts, nb_commit, flags);\n+\tiavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);\n \n \ttx_id = (uint16_t)(tx_id + nb_commit);\n \tif (tx_id > txq->next_rs) {\n@@ -1560,9 +1570,9 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \treturn nb_pkts;\n }\n \n-uint16_t\n-iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\tuint16_t nb_pkts)\n+static __rte_always_inline uint16_t\n+iavf_xmit_pkts_vec_avx2_common(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts, bool offload)\n {\n \tuint16_t nb_tx = 0;\n \tstruct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;\n@@ -1573,7 +1583,7 @@ iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t/* cross rs_thresh boundary is not allowed */\n \t\tnum = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);\n \t\tret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],\n-\t\t\t\t\t\t num);\n+\t\t\t\t\t\t num, offload);\n \t\tnb_tx += ret;\n \t\tnb_pkts -= ret;\n \t\tif (ret < num)\n@@ -1582,3 +1592,17 @@ iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \treturn nb_tx;\n }\n+\n+uint16_t\n+iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\treturn iavf_xmit_pkts_vec_avx2_common(tx_queue, tx_pkts, nb_pkts, false);\n+}\n+\n+uint16_t\n+iavf_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\treturn iavf_xmit_pkts_vec_avx2_common(tx_queue, tx_pkts, nb_pkts, true);\n+}\n", "prefixes": [ "1/2" ] }