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GET /api/patches/123328/?format=api
{ "id": 123328, "url": "https://patches.dpdk.org/api/patches/123328/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230207160719.1307-12-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230207160719.1307-12-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230207160719.1307-12-syalavarthi@marvell.com", "date": "2023-02-07T16:06:51", "name": "[v5,11/39] ml/cnxk: add functions to load and unload models", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5d5be786832dc86486b5bb9204b12feb2cbaf06e", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230207160719.1307-12-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26860, "url": "https://patches.dpdk.org/api/series/26860/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26860", "date": "2023-02-07T16:06:40", "name": "Implementation of ML CNXK driver", "version": 5, "mbox": "https://patches.dpdk.org/series/26860/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/123328/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/123328/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B799F41C30;\n\tTue, 7 Feb 2023 17:08:46 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BA76942D63;\n\tTue, 7 Feb 2023 17:07:39 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E36A042D0D\n for <dev@dpdk.org>; Tue, 7 Feb 2023 17:07:28 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 317BL2vh005847 for <dev@dpdk.org>; Tue, 7 Feb 2023 08:07:28 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nhqrtmsnd-5\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 07 Feb 2023 08:07:28 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Tue, 7 Feb 2023 08:07:25 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Tue, 7 Feb 2023 08:07:25 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 3A7E93F7088;\n Tue, 7 Feb 2023 08:07:25 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=I0o7HE4dEvwmgtfFpIvw6QX8bKVmXCBaCVCOnFP9nZA=;\n b=aUOvQMWyM0vnmQBLi0oJm25hR2VZsHltGFnIHVPnAXKnLFJvKyJ4EEvvCeG0O7NKYeQv\n FhYNmX17HbZ4nk9vmsK03dakvqGLt5zetGZPpNoJYw+Gv7IDk53QaABUgfAiMLHs8RS9\n pYBYaTyGz/LclMWmQOdPhmQ9okzuAcoSClRCHaOh51b7A1fI9n3XdKNrbW4nKwUDvkAD\n Yx1h6a+W6017+bjmwlnJlPGlqL0WksY52DcnDzArHEfMvs1KgUpTM4fXlXSX75tMVPR8\n C2f+z5kw3y/jVXdIEgpEVaygFLXV9MyYZKfai3CoIKRJMeHCsjdOkTQiLpeJuXRTVPX0 9Q==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>, <ptakkar@marvell.com>, <pshukla@marvell.com>", "Subject": "[PATCH v5 11/39] ml/cnxk: add functions to load and unload models", "Date": "Tue, 7 Feb 2023 08:06:51 -0800", "Message-ID": "<20230207160719.1307-12-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230207160719.1307-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230207160719.1307-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "BLLKVdeKHCmToRLDGoIF7VAiZ1NwUI8Q", "X-Proofpoint-ORIG-GUID": "BLLKVdeKHCmToRLDGoIF7VAiZ1NwUI8Q", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added cnxk driver implementations to load and unload ML models.\nEnabled support in configure stage to allocate model handles\narray. Assign model ID and allocate resources per each model\nduring load stage and release resources during model unload.\nAdded internal structures to handle ML models.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.h | 3 +\n drivers/ml/cnxk/cn10k_ml_model.c | 5 +\n drivers/ml/cnxk/cn10k_ml_model.h | 40 ++++++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 154 +++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.h | 5 +\n drivers/ml/cnxk/meson.build | 2 +\n 6 files changed, 209 insertions(+)\n create mode 100644 drivers/ml/cnxk/cn10k_ml_model.c\n create mode 100644 drivers/ml/cnxk/cn10k_ml_model.h", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 00d23eb3ca..7cf6268115 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -214,6 +214,9 @@ struct cn10k_ml_dev {\n \n \t/* Firmware */\n \tstruct cn10k_ml_fw fw;\n+\n+\t/* Number of models loaded */\n+\tuint16_t nb_models_loaded;\n };\n \n uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nnew file mode 100644\nindex 0000000000..39ed707396\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -0,0 +1,5 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#include \"cn10k_ml_model.h\"\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nnew file mode 100644\nindex 0000000000..a9f7b169de\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef _CN10K_ML_MODEL_H_\n+#define _CN10K_ML_MODEL_H_\n+\n+#include <rte_mldev.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cn10k_ml_dev.h\"\n+\n+/* Model state */\n+enum cn10k_ml_model_state {\n+\tML_CN10K_MODEL_STATE_LOADED,\n+\tML_CN10K_MODEL_STATE_JOB_ACTIVE,\n+\tML_CN10K_MODEL_STATE_STARTED,\n+\tML_CN10K_MODEL_STATE_UNKNOWN,\n+};\n+\n+/* Model Object */\n+struct cn10k_ml_model {\n+\t/* Device reference */\n+\tstruct cn10k_ml_dev *mldev;\n+\n+\t/* Name */\n+\tchar name[RTE_ML_STR_MAX];\n+\n+\t/* ID */\n+\tuint16_t model_id;\n+\n+\t/* Spinlock, used to update model state */\n+\tplt_spinlock_t lock;\n+\n+\t/* State */\n+\tenum cn10k_ml_model_state state;\n+};\n+\n+#endif /* _CN10K_ML_MODEL_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 82670330d1..0955fa0d76 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -6,8 +6,12 @@\n #include <rte_mldev_pmd.h>\n \n #include \"cn10k_ml_dev.h\"\n+#include \"cn10k_ml_model.h\"\n #include \"cn10k_ml_ops.h\"\n \n+/* ML model macros */\n+#define CN10K_ML_MODEL_MEMZONE_NAME \"ml_cn10k_model_mz\"\n+\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n@@ -120,9 +124,11 @@ static int\n cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf)\n {\n \tstruct rte_ml_dev_info dev_info;\n+\tstruct cn10k_ml_model *model;\n \tstruct cn10k_ml_dev *mldev;\n \tstruct cn10k_ml_qp *qp;\n \tuint32_t mz_size;\n+\tuint16_t model_id;\n \tuint16_t qp_id;\n \tint ret;\n \n@@ -203,6 +209,48 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \t}\n \tdev->data->nb_queue_pairs = conf->nb_queue_pairs;\n \n+\t/* Allocate ML models */\n+\tif (dev->data->models == NULL) {\n+\t\tmz_size = sizeof(dev->data->models[0]) * conf->nb_models;\n+\t\tdev->data->models = rte_zmalloc(\"cn10k_mldev_models\", mz_size, RTE_CACHE_LINE_SIZE);\n+\t\tif (dev->data->models == NULL) {\n+\t\t\tdev->data->nb_models = 0;\n+\t\t\tplt_err(\"Failed to get memory for ml_models, nb_models %u\",\n+\t\t\t\tconf->nb_models);\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t} else {\n+\t\t/* Re-configure */\n+\t\tvoid **models;\n+\n+\t\t/* Unload all models */\n+\t\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n+\t\t\tmodel = dev->data->models[model_id];\n+\t\t\tif (model != NULL) {\n+\t\t\t\tif (model->state == ML_CN10K_MODEL_STATE_LOADED) {\n+\t\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n+\t\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n+\t\t\t\t}\n+\t\t\t\tdev->data->models[model_id] = NULL;\n+\t\t\t}\n+\t\t}\n+\n+\t\tmodels = dev->data->models;\n+\t\tmodels = rte_realloc(models, sizeof(models[0]) * conf->nb_models,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (models == NULL) {\n+\t\t\tdev->data->nb_models = 0;\n+\t\t\tplt_err(\"Failed to realloc ml_models, nb_models = %u\", conf->nb_models);\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tmemset(models, 0, sizeof(models[0]) * conf->nb_models);\n+\t\tdev->data->models = models;\n+\t}\n+\tdev->data->nb_models = conf->nb_models;\n+\n+\tmldev->nb_models_loaded = 0;\n \tmldev->state = ML_CN10K_DEV_STATE_CONFIGURED;\n \n \treturn 0;\n@@ -211,14 +259,19 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \tif (dev->data->queue_pairs != NULL)\n \t\trte_free(dev->data->queue_pairs);\n \n+\tif (dev->data->models != NULL)\n+\t\trte_free(dev->data->models);\n+\n \treturn ret;\n }\n \n static int\n cn10k_ml_dev_close(struct rte_ml_dev *dev)\n {\n+\tstruct cn10k_ml_model *model;\n \tstruct cn10k_ml_dev *mldev;\n \tstruct cn10k_ml_qp *qp;\n+\tuint16_t model_id;\n \tuint16_t qp_id;\n \n \tif (dev == NULL)\n@@ -226,6 +279,21 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev)\n \n \tmldev = dev->data->dev_private;\n \n+\t/* Unload all models */\n+\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n+\t\tmodel = dev->data->models[model_id];\n+\t\tif (model != NULL) {\n+\t\t\tif (model->state == ML_CN10K_MODEL_STATE_LOADED) {\n+\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n+\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n+\t\t\t}\n+\t\t\tdev->data->models[model_id] = NULL;\n+\t\t}\n+\t}\n+\n+\tif (dev->data->models)\n+\t\trte_free(dev->data->models);\n+\n \t/* Destroy all queue pairs */\n \tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n \t\tqp = dev->data->queue_pairs[qp_id];\n@@ -337,6 +405,88 @@ cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n \treturn 0;\n }\n \n+int\n+cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, uint16_t *model_id)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\n+\tchar str[RTE_MEMZONE_NAMESIZE];\n+\tconst struct plt_memzone *mz;\n+\tuint64_t mz_size;\n+\tuint16_t idx;\n+\tbool found;\n+\n+\tPLT_SET_USED(params);\n+\n+\tmldev = dev->data->dev_private;\n+\n+\t/* Find model ID */\n+\tfound = false;\n+\tfor (idx = 0; idx < dev->data->nb_models; idx++) {\n+\t\tif (dev->data->models[idx] == NULL) {\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!found) {\n+\t\tplt_err(\"No slots available to load new model\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Compute memzone size */\n+\tmz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE);\n+\n+\t/* Allocate memzone for model object and model data */\n+\tsnprintf(str, RTE_MEMZONE_NAMESIZE, \"%s_%u\", CN10K_ML_MODEL_MEMZONE_NAME, idx);\n+\tmz = plt_memzone_reserve_aligned(str, mz_size, 0, ML_CN10K_ALIGN_SIZE);\n+\tif (!mz) {\n+\t\tplt_err(\"plt_memzone_reserve failed : %s\", str);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmodel = mz->addr;\n+\tmodel->mldev = mldev;\n+\tmodel->model_id = idx;\n+\n+\tplt_spinlock_init(&model->lock);\n+\tmodel->state = ML_CN10K_MODEL_STATE_LOADED;\n+\tdev->data->models[idx] = model;\n+\tmldev->nb_models_loaded++;\n+\n+\t*model_id = idx;\n+\n+\treturn 0;\n+}\n+\n+int\n+cn10k_ml_model_unload(struct rte_ml_dev *dev, uint16_t model_id)\n+{\n+\tchar str[RTE_MEMZONE_NAMESIZE];\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\n+\tmldev = dev->data->dev_private;\n+\tmodel = dev->data->models[model_id];\n+\n+\tif (model == NULL) {\n+\t\tplt_err(\"Invalid model_id = %u\", model_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (model->state != ML_CN10K_MODEL_STATE_LOADED) {\n+\t\tplt_err(\"Cannot unload. Model in use.\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tdev->data->models[model_id] = NULL;\n+\tmldev->nb_models_loaded--;\n+\n+\tsnprintf(str, RTE_MEMZONE_NAMESIZE, \"%s_%u\", CN10K_ML_MODEL_MEMZONE_NAME, model_id);\n+\treturn plt_memzone_free(plt_memzone_lookup(str));\n+}\n+\n struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Device control ops */\n \t.dev_info_get = cn10k_ml_dev_info_get,\n@@ -348,4 +498,8 @@ struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Queue-pair handling ops */\n \t.dev_queue_pair_setup = cn10k_ml_dev_queue_pair_setup,\n \t.dev_queue_pair_release = cn10k_ml_dev_queue_pair_release,\n+\n+\t/* Model ops */\n+\t.model_load = cn10k_ml_model_load,\n+\t.model_unload = cn10k_ml_model_unload,\n };\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 289c7c5587..d7842ecd73 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -53,4 +53,9 @@ struct cn10k_ml_qp {\n /* Device ops */\n extern struct rte_ml_dev_ops cn10k_ml_ops;\n \n+/* Slow-path ops */\n+int cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n+\t\t\tuint16_t *model_id);\n+int cn10k_ml_model_unload(struct rte_ml_dev *dev, uint16_t model_id);\n+\n #endif /* _CN10K_ML_OPS_H_ */\ndiff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build\nindex 7dc8a29a80..bf7a9c0225 100644\n--- a/drivers/ml/cnxk/meson.build\n+++ b/drivers/ml/cnxk/meson.build\n@@ -10,11 +10,13 @@ endif\n driver_sdk_headers = files(\n 'cn10k_ml_dev.h',\n 'cn10k_ml_ops.h',\n+ 'cn10k_ml_model.h',\n )\n \n sources = files(\n 'cn10k_ml_dev.c',\n 'cn10k_ml_ops.c',\n+ 'cn10k_ml_model.c',\n )\n \n deps += ['mldev', 'common_cnxk', 'kvargs']\n", "prefixes": [ "v5", "11/39" ] }