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GET /api/patches/122736/?format=api
{ "id": 122736, "url": "https://patches.dpdk.org/api/patches/122736/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-13-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-13-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-13-valex@nvidia.com", "date": "2023-01-31T09:33:41", "name": "[v1,12/16] net/mlx5/hws: add range definer creation support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6dee948797fce4fc6163d8299f3cbf89d5c91ac4", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-13-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "https://patches.dpdk.org/api/series/26709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "https://patches.dpdk.org/series/26709/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/122736/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/122736/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 56FA441B8D;\n\tTue, 31 Jan 2023 10:36:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2871E42FB6;\n\tTue, 31 Jan 2023 10:35:07 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53])\n by mails.dpdk.org (Postfix) with ESMTP id 9C1854114A\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 12/16] net/mlx5/hws: add range definer creation support", "Date": "Tue, 31 Jan 2023 11:33:41 +0200", "Message-ID": "<20230131093346.1261066-13-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT022:EE_|DM6PR12MB4546:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8680e8e1-b293-4bd6-7880-08db036e6981", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n sn7OF8SajlK1QfVW+Z8oJDPQdFTtcmg8aW91ysHfRuaUdU9gBATf0nlud4nm3knmI3KfXWmBjyd27KrB83f89tCztSlXPvAXRwQWdKmlb5svmQ1EmFnDwISp5xBX28UceDoFzGkYjPu/ANcOc0F7088DbsP67hKSYuOtCez73lhLfCuezt6A+Z6OghP88fQ0C9E2VTm197XyjI6t4pCFnpQVsoZrwYuYIu1U/pi6lnW+mWLMuReZqbVGKcjUV1p5b+yD5iRFXpFVd2nLvT7KpMBtqjSM3f5PsqRmbA41on6yBTNJ4xBhRbtZk4iPoch3m0nRm6hHsLGcSiR7kYpdOyxXkw9NI1Jvd4AwqJII/RfqJlGuOKHE7MJ3lYPsEVxCO7M34SYmvjCZcPQFjbGp8HLEHUue4hskPD6X1HuxUhrng/I3wVmIzEBGgn1s4tCkka7CIupL8bH6F4DjaUGoC5niMerbkrIAxeN20lzyEk0conI+6e6Kv02ZiuKa75cXgUvMopeBKyamJ6kAs8uSk58loZSLNX2ssNuthpZybNL08cG6ubxzzk1QfcIIGOzvvTIau/u9mTzjspP81v+xVpwOZfNIAbhUJfYaiBc2aA30ch/daZmjyF2qnGLIZf7mTHeZIg270MprsGq7sV3Vc9Omj+IxJcg65DMVjeCIptBgeDR2QZzNJO2jDOvNjbGiFUyBO+t/UUrBcqzaKPxjDQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(376002)(346002)(396003)(136003)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(86362001)(36756003)(356005)(36860700001)(82740400003)(7636003)(426003)(107886003)(336012)(83380400001)(47076005)(186003)(26005)(16526019)(6286002)(6666004)(2616005)(478600001)(1076003)(54906003)(110136005)(41300700001)(7696005)(30864003)(2906002)(70206006)(6636002)(8936002)(5660300002)(82310400005)(40480700001)(55016003)(316002)(70586007)(4326008)(8676002)(40460700003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:55.2717 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8680e8e1-b293-4bd6-7880-08db036e6981", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT022.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4546", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Calculate and create an additional definer used for range\ncheck during matcher creation. In such case two definers will\nbe created one for specific matching and a range definer.\nSince range HW GTA WQE doesn't support the needed range\nsupport rule insertion rule insertion is done using the FW\nGTA WQE command.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 255 +++++++++++++++++++++++---\n drivers/net/mlx5/hws/mlx5dr_definer.h | 16 +-\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 27 ++-\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 17 +-\n 4 files changed, 281 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 260e6c5d1d..cf84fbea71 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -1508,26 +1508,33 @@ mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,\n \t\t\t struct mlx5dr_definer_fc *fc,\n \t\t\t uint8_t *hl)\n {\n-\tuint32_t fc_sz = 0;\n+\tuint32_t fc_sz = 0, fcr_sz = 0;\n \tint i;\n \n \tfor (i = 0; i < MLX5DR_DEFINER_FNAME_MAX; i++)\n \t\tif (fc[i].tag_set)\n-\t\t\tfc_sz++;\n+\t\t\tfc[i].is_range ? fcr_sz++ : fc_sz++;\n \n-\tmt->fc = simple_calloc(fc_sz, sizeof(*mt->fc));\n+\tmt->fc = simple_calloc(fc_sz + fcr_sz, sizeof(*mt->fc));\n \tif (!mt->fc) {\n \t\trte_errno = ENOMEM;\n \t\treturn rte_errno;\n \t}\n \n+\tmt->fcr = mt->fc + fc_sz;\n+\n \tfor (i = 0; i < MLX5DR_DEFINER_FNAME_MAX; i++) {\n \t\tif (!fc[i].tag_set)\n \t\t\tcontinue;\n \n \t\tfc[i].fname = i;\n-\t\tmemcpy(&mt->fc[mt->fc_sz++], &fc[i], sizeof(*mt->fc));\n-\t\tDR_SET(hl, -1, fc[i].byte_off, fc[i].bit_off, fc[i].bit_mask);\n+\n+\t\tif (fc[i].is_range) {\n+\t\t\tmemcpy(&mt->fcr[mt->fcr_sz++], &fc[i], sizeof(*mt->fcr));\n+\t\t} else {\n+\t\t\tmemcpy(&mt->fc[mt->fc_sz++], &fc[i], sizeof(*mt->fc));\n+\t\t\tDR_SET(hl, -1, fc[i].byte_off, fc[i].bit_off, fc[i].bit_mask);\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -1686,7 +1693,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \n \tmt->item_flags = item_flags;\n \n-\t/* Fill in headers layout and allocate fc array on mt */\n+\t/* Fill in headers layout and allocate fc & fcr array on mt */\n \tret = mlx5dr_definer_mt_set_fc(mt, fc, hl);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to set field copy to match template\");\n@@ -1855,9 +1862,92 @@ mlx5dr_definer_copy_sel_ctrl(struct mlx5dr_definer_sel_ctrl *ctrl,\n }\n \n static int\n-mlx5dr_definer_find_best_hl_fit(struct mlx5dr_context *ctx,\n-\t\t\t\tstruct mlx5dr_definer *definer,\n-\t\t\t\tuint8_t *hl)\n+mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer,\n+\t\t\t\t struct mlx5dr_matcher *matcher)\n+{\n+\tuint8_t tag_byte_offset[MLX5DR_DEFINER_FNAME_MAX] = {0};\n+\tuint8_t field_select[MLX5DR_DEFINER_FNAME_MAX] = {0};\n+\tstruct mlx5dr_definer_sel_ctrl ctrl = {0};\n+\tuint32_t byte_offset, algn_byte_off;\n+\tstruct mlx5dr_definer_fc *fcr;\n+\tbool require_dw;\n+\tint idx, i, j;\n+\n+\t/* Try to create a range definer */\n+\tctrl.allowed_full_dw = DW_SELECTORS_RANGE;\n+\tctrl.allowed_bytes = BYTE_SELECTORS_RANGE;\n+\n+\t/* Multiple fields cannot share the same DW for range match.\n+\t * The HW doesn't recognize each field but compares the full dw.\n+\t * For example definer DW consists of FieldA_FieldB\n+\t * FieldA: Mask 0xFFFF range 0x1 to 0x2\n+\t * FieldB: Mask 0xFFFF range 0x3 to 0x4\n+\t * STE DW range will be 0x00010003 - 0x00020004\n+\t * This will cause invalid match for FieldB if FieldA=1 and FieldB=8\n+\t * Since 0x10003 < 0x10008 < 0x20004\n+\t */\n+\tfor (i = 0; i < matcher->num_of_mt; i++) {\n+\t\tfor (j = 0; j < matcher->mt[i].fcr_sz; j++) {\n+\t\t\tfcr = &matcher->mt[i].fcr[j];\n+\n+\t\t\t/* Found - Reuse previous mt binding */\n+\t\t\tif (field_select[fcr->fname]) {\n+\t\t\t\tfcr->byte_off = tag_byte_offset[fcr->fname];\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\t/* Not found */\n+\t\t\trequire_dw = fcr->byte_off >= (64 * DW_SIZE);\n+\t\t\tif (require_dw || ctrl.used_bytes == ctrl.allowed_bytes) {\n+\t\t\t\t/* Try to cover using DW selector */\n+\t\t\t\tif (ctrl.used_full_dw == ctrl.allowed_full_dw)\n+\t\t\t\t\tgoto not_supported;\n+\n+\t\t\t\tctrl.full_dw_selector[ctrl.used_full_dw++] =\n+\t\t\t\t\tfcr->byte_off / DW_SIZE;\n+\n+\t\t\t\t/* Bind DW */\n+\t\t\t\tidx = ctrl.used_full_dw - 1;\n+\t\t\t\tbyte_offset = fcr->byte_off % DW_SIZE;\n+\t\t\t\tbyte_offset += DW_SIZE * (DW_SELECTORS - idx - 1);\n+\t\t\t} else {\n+\t\t\t\t/* Try to cover using Bytes selectors */\n+\t\t\t\tif (ctrl.used_bytes == ctrl.allowed_bytes)\n+\t\t\t\t\tgoto not_supported;\n+\n+\t\t\t\talgn_byte_off = DW_SIZE * (fcr->byte_off / DW_SIZE);\n+\t\t\t\tctrl.byte_selector[ctrl.used_bytes++] = algn_byte_off + 3;\n+\t\t\t\tctrl.byte_selector[ctrl.used_bytes++] = algn_byte_off + 2;\n+\t\t\t\tctrl.byte_selector[ctrl.used_bytes++] = algn_byte_off + 1;\n+\t\t\t\tctrl.byte_selector[ctrl.used_bytes++] = algn_byte_off;\n+\n+\t\t\t\t/* Bind BYTE */\n+\t\t\t\tbyte_offset = DW_SIZE * DW_SELECTORS;\n+\t\t\t\tbyte_offset += BYTE_SELECTORS - ctrl.used_bytes;\n+\t\t\t\tbyte_offset += fcr->byte_off % DW_SIZE;\n+\t\t\t}\n+\n+\t\t\tfcr->byte_off = byte_offset;\n+\t\t\ttag_byte_offset[fcr->fname] = byte_offset;\n+\t\t\tfield_select[fcr->fname] = 1;\n+\t\t}\n+\t}\n+\n+\tmlx5dr_definer_copy_sel_ctrl(&ctrl, definer);\n+\tdefiner->type = MLX5DR_DEFINER_TYPE_RANGE;\n+\n+\treturn 0;\n+\n+not_supported:\n+\tDR_LOG(ERR, \"Unable to find supporting range definer combination\");\n+\trte_errno = ENOTSUP;\n+\treturn rte_errno;\n+}\n+\n+static int\n+mlx5dr_definer_find_best_match_fit(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_definer *definer,\n+\t\t\t\t uint8_t *hl)\n {\n \tstruct mlx5dr_definer_sel_ctrl ctrl = {0};\n \tbool found;\n@@ -1923,6 +2013,43 @@ void mlx5dr_definer_create_tag(const struct rte_flow_item *items,\n \t}\n }\n \n+static uint32_t mlx5dr_definer_get_range_byte_off(uint32_t match_byte_off)\n+{\n+\tuint8_t curr_dw_idx = match_byte_off / DW_SIZE;\n+\tuint8_t new_dw_idx;\n+\n+\t/* Range DW can have the following values 7,8,9,10\n+\t * -DW7 is mapped to DW9\n+\t * -DW8 is mapped to DW7\n+\t * -DW9 is mapped to DW5\n+\t * -DW10 is mapped to DW3\n+\t * To reduce calculation the following formula is used:\n+\t */\n+\tnew_dw_idx = curr_dw_idx * (-2) + 23;\n+\n+\treturn new_dw_idx * DW_SIZE + match_byte_off % DW_SIZE;\n+}\n+\n+void mlx5dr_definer_create_tag_range(const struct rte_flow_item *items,\n+\t\t\t\t struct mlx5dr_definer_fc *fc,\n+\t\t\t\t uint32_t fc_sz,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tstruct mlx5dr_definer_fc tmp_fc;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < fc_sz; i++) {\n+\t\ttmp_fc = *fc;\n+\t\t/* Set MAX value */\n+\t\ttmp_fc.byte_off = mlx5dr_definer_get_range_byte_off(fc->byte_off);\n+\t\ttmp_fc.tag_set(&tmp_fc, items[fc->item_idx].last, tag);\n+\t\t/* Set MIN value */\n+\t\ttmp_fc.byte_off += DW_SIZE;\n+\t\ttmp_fc.tag_set(&tmp_fc, items[fc->item_idx].spec, tag);\n+\t\tfc++;\n+\t}\n+}\n+\n int mlx5dr_definer_get_id(struct mlx5dr_definer *definer)\n {\n \treturn definer->obj->id;\n@@ -1951,27 +2078,26 @@ mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n \n static int\n mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n-\t\t\t struct mlx5dr_definer *match_definer)\n+\t\t\t struct mlx5dr_definer *match_definer,\n+\t\t\t struct mlx5dr_definer *range_definer)\n {\n \tstruct mlx5dr_context *ctx = matcher->tbl->ctx;\n \tstruct mlx5dr_match_template *mt = matcher->mt;\n-\tuint8_t *match_hl, *hl_buff;\n+\tuint8_t *match_hl;\n \tint i, ret;\n \n \t/* Union header-layout (hl) is used for creating a single definer\n \t * field layout used with different bitmasks for hash and match.\n \t */\n-\thl_buff = simple_calloc(1, MLX5_ST_SZ_BYTES(definer_hl));\n-\tif (!hl_buff) {\n+\tmatch_hl = simple_calloc(1, MLX5_ST_SZ_BYTES(definer_hl));\n+\tif (!match_hl) {\n \t\tDR_LOG(ERR, \"Failed to allocate memory for header layout\");\n \t\trte_errno = ENOMEM;\n \t\treturn rte_errno;\n \t}\n \n-\tmatch_hl = hl_buff;\n-\n \t/* Convert all mt items to header layout (hl)\n-\t * and allocate the match field copy array (fc).\n+\t * and allocate the match and range field copy array (fc & fcr).\n \t */\n \tfor (i = 0; i < matcher->num_of_mt; i++) {\n \t\tret = mlx5dr_definer_conv_items_to_hl(ctx, &mt[i], match_hl);\n@@ -1982,13 +2108,20 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t}\n \n \t/* Find the match definer layout for header layout match union */\n-\tret = mlx5dr_definer_find_best_hl_fit(ctx, match_definer, match_hl);\n+\tret = mlx5dr_definer_find_best_match_fit(ctx, match_definer, match_hl);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to create match definer from header layout\");\n \t\tgoto free_fc;\n \t}\n \n-\tsimple_free(hl_buff);\n+\t/* Find the range definer layout for match templates fcrs */\n+\tret = mlx5dr_definer_find_best_range_fit(range_definer, matcher);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to create range definer from header layout\");\n+\t\tgoto free_fc;\n+\t}\n+\n+\tsimple_free(match_hl);\n \treturn 0;\n \n free_fc:\n@@ -1996,7 +2129,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t\tif (mt[i].fc)\n \t\t\tsimple_free(mt[i].fc);\n \n-\tsimple_free(hl_buff);\n+\tsimple_free(match_hl);\n \treturn rte_errno;\n }\n \n@@ -2005,7 +2138,8 @@ mlx5dr_definer_alloc(struct ibv_context *ibv_ctx,\n \t\t struct mlx5dr_definer_fc *fc,\n \t\t int fc_sz,\n \t\t struct rte_flow_item *items,\n-\t\t struct mlx5dr_definer *layout)\n+\t\t struct mlx5dr_definer *layout,\n+\t\t bool bind_fc)\n {\n \tstruct mlx5dr_cmd_definer_create_attr def_attr = {0};\n \tstruct mlx5dr_definer *definer;\n@@ -2021,10 +2155,12 @@ mlx5dr_definer_alloc(struct ibv_context *ibv_ctx,\n \tmemcpy(definer, layout, sizeof(*definer));\n \n \t/* Align field copy array based on given layout */\n-\tret = mlx5dr_definer_fc_bind(definer, fc, fc_sz);\n-\tif (ret) {\n-\t\tDR_LOG(ERR, \"Failed to bind field copy to definer\");\n-\t\tgoto free_definer;\n+\tif (bind_fc) {\n+\t\tret = mlx5dr_definer_fc_bind(definer, fc, fc_sz);\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Failed to bind field copy to definer\");\n+\t\t\tgoto free_definer;\n+\t\t}\n \t}\n \n \t/* Create the tag mask used for definer creation */\n@@ -2067,7 +2203,8 @@ mlx5dr_definer_matcher_match_init(struct mlx5dr_context *ctx,\n \t\t\t\t\t\t mt[i].fc,\n \t\t\t\t\t\t mt[i].fc_sz,\n \t\t\t\t\t\t mt[i].items,\n-\t\t\t\t\t\t match_layout);\n+\t\t\t\t\t\t match_layout,\n+\t\t\t\t\t\t true);\n \t\tif (!mt[i].definer) {\n \t\t\tDR_LOG(ERR, \"Failed to create match definer\");\n \t\t\tgoto free_definers;\n@@ -2091,6 +2228,58 @@ mlx5dr_definer_matcher_match_uninit(struct mlx5dr_matcher *matcher)\n \t\tmlx5dr_definer_free(matcher->mt[i].definer);\n }\n \n+static int\n+mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_matcher *matcher,\n+\t\t\t\t struct mlx5dr_definer *range_layout)\n+{\n+\tstruct mlx5dr_match_template *mt = matcher->mt;\n+\tint i;\n+\n+\t/* Create optional range definers */\n+\tfor (i = 0; i < matcher->num_of_mt; i++) {\n+\t\tif (!mt[i].fcr_sz)\n+\t\t\tcontinue;\n+\n+\t\t/* All must use range if requested */\n+\t\tif (i && !mt[i - 1].range_definer) {\n+\t\t\tDR_LOG(ERR, \"Using range and non range templates is not allowed\");\n+\t\t\tgoto free_definers;\n+\t\t}\n+\n+\t\tmatcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;\n+\t\t/* Create definer without fcr binding, already binded */\n+\t\tmt[i].range_definer = mlx5dr_definer_alloc(ctx->ibv_ctx,\n+\t\t\t\t\t\t\t mt[i].fcr,\n+\t\t\t\t\t\t\t mt[i].fcr_sz,\n+\t\t\t\t\t\t\t mt[i].items,\n+\t\t\t\t\t\t\t range_layout,\n+\t\t\t\t\t\t\t false);\n+\t\tif (!mt[i].range_definer) {\n+\t\t\tDR_LOG(ERR, \"Failed to create match definer\");\n+\t\t\tgoto free_definers;\n+\t\t}\n+\t}\n+\treturn 0;\n+\n+free_definers:\n+\twhile (i--)\n+\t\tif (mt[i].range_definer)\n+\t\t\tmlx5dr_definer_free(mt[i].range_definer);\n+\n+\treturn rte_errno;\n+}\n+\n+static void\n+mlx5dr_definer_matcher_range_uninit(struct mlx5dr_matcher *matcher)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < matcher->num_of_mt; i++)\n+\t\tif (matcher->mt[i].range_definer)\n+\t\t\tmlx5dr_definer_free(matcher->mt[i].range_definer);\n+}\n+\n static int\n mlx5dr_definer_matcher_hash_init(struct mlx5dr_context *ctx,\n \t\t\t\t struct mlx5dr_matcher *matcher)\n@@ -2169,13 +2358,13 @@ int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_matcher *matcher)\n {\n \tstruct mlx5dr_definer match_layout = {0};\n+\tstruct mlx5dr_definer range_layout = {0};\n \tint ret, i;\n \n \tif (matcher->flags & MLX5DR_MATCHER_FLAGS_COLISION)\n \t\treturn 0;\n \n-\t/* Calculate header layout based on matcher items */\n-\tret = mlx5dr_definer_calc_layout(matcher, &match_layout);\n+\tret = mlx5dr_definer_calc_layout(matcher, &match_layout, &range_layout);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to calculate matcher definer layout\");\n \t\treturn ret;\n@@ -2188,15 +2377,24 @@ int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\n \t\tgoto free_fc;\n \t}\n \n+\t/* Calculate definers needed for range */\n+\tret = mlx5dr_definer_matcher_range_init(ctx, matcher, &range_layout);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to init range definers\");\n+\t\tgoto uninit_match_definer;\n+\t}\n+\n \t/* Calculate partial hash definer */\n \tret = mlx5dr_definer_matcher_hash_init(ctx, matcher);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to init hash definer\");\n-\t\tgoto uninit_match_definer;\n+\t\tgoto uninit_range_definer;\n \t}\n \n \treturn 0;\n \n+uninit_range_definer:\n+\tmlx5dr_definer_matcher_range_uninit(matcher);\n uninit_match_definer:\n \tmlx5dr_definer_matcher_match_uninit(matcher);\n free_fc:\n@@ -2214,6 +2412,7 @@ void mlx5dr_definer_matcher_uninit(struct mlx5dr_matcher *matcher)\n \t\treturn;\n \n \tmlx5dr_definer_matcher_hash_uninit(matcher);\n+\tmlx5dr_definer_matcher_range_uninit(matcher);\n \tmlx5dr_definer_matcher_match_uninit(matcher);\n \n \tfor (i = 0; i < matcher->num_of_mt; i++)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex a14a08838a..dd9a297007 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -5,11 +5,17 @@\n #ifndef MLX5DR_DEFINER_H_\n #define MLX5DR_DEFINER_H_\n \n+/* Max available selecotrs */\n+#define DW_SELECTORS 9\n+#define BYTE_SELECTORS 8\n+\n /* Selectors based on match TAG */\n #define DW_SELECTORS_MATCH 6\n #define DW_SELECTORS_LIMITED 3\n-#define DW_SELECTORS 9\n-#define BYTE_SELECTORS 8\n+\n+/* Selectors based on range TAG */\n+#define DW_SELECTORS_RANGE 2\n+#define BYTE_SELECTORS_RANGE 8\n \n enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_O,\n@@ -112,6 +118,7 @@ enum mlx5dr_definer_fname {\n enum mlx5dr_definer_type {\n \tMLX5DR_DEFINER_TYPE_MATCH,\n \tMLX5DR_DEFINER_TYPE_JUMBO,\n+\tMLX5DR_DEFINER_TYPE_RANGE,\n };\n \n struct mlx5dr_definer_fc {\n@@ -573,6 +580,11 @@ void mlx5dr_definer_create_tag(const struct rte_flow_item *items,\n \t\t\t uint32_t fc_sz,\n \t\t\t uint8_t *tag);\n \n+void mlx5dr_definer_create_tag_range(const struct rte_flow_item *items,\n+\t\t\t\t struct mlx5dr_definer_fc *fc,\n+\t\t\t\t uint32_t fc_sz,\n+\t\t\t\t uint8_t *tag);\n+\n int mlx5dr_definer_get_id(struct mlx5dr_definer *definer);\n \n int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex e860c274cf..de688f6873 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -360,6 +360,12 @@ static bool mlx5dr_matcher_supp_fw_wqe(struct mlx5dr_matcher *matcher)\n \t\treturn false;\n \t}\n \n+\tif ((matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER) &&\n+\t !IS_BIT_SET(caps->supp_ste_fromat_gen_wqe, MLX5_IFC_RTC_STE_FORMAT_RANGE)) {\n+\t\tDR_LOG(INFO, \"Extended match gen wqe RANGE format not supported\");\n+\t\treturn false;\n+\t}\n+\n \tif (!(caps->supp_type_gen_wqe & MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE)) {\n \t\tDR_LOG(ERR, \"Gen WQE command not supporting GTA\");\n \t\treturn false;\n@@ -460,14 +466,20 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\tste = &matcher->match_ste.ste;\n \t\tste->order = attr->table.sz_col_log + attr->table.sz_row_log;\n \n+\t\t/* Add additional rows due to additional range STE */\n+\t\tif (mlx5dr_matcher_mt_is_range(mt))\n+\t\t\tste->order++;\n+\n \t\trtc_attr.log_size = attr->table.sz_row_log;\n \t\trtc_attr.log_depth = attr->table.sz_col_log;\n \t\trtc_attr.is_frst_jumbo = mlx5dr_matcher_mt_is_jumbo(mt);\n+\t\trtc_attr.is_scnd_range = mlx5dr_matcher_mt_is_range(mt);\n \t\trtc_attr.miss_ft_id = matcher->end_ft->id;\n \n \t\tif (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) {\n \t\t\t/* The usual Hash Table */\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH;\n+\n \t\t\tif (matcher->hash_definer) {\n \t\t\t\t/* Specify definer_id_0 is used for hashing */\n \t\t\t\trtc_attr.fw_gen_wqe = true;\n@@ -477,6 +489,16 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\t\t} else {\n \t\t\t\t/* The first mt is used since all share the same definer */\n \t\t\t\trtc_attr.match_definer_0 = mlx5dr_definer_get_id(mt->definer);\n+\n+\t\t\t\t/* This is tricky, instead of passing two definers for\n+\t\t\t\t * match and range, we specify that this RTC uses a hash\n+\t\t\t\t * definer, this will allow us to use any range definer\n+\t\t\t\t * since only first STE is used for hashing anyways.\n+\t\t\t\t */\n+\t\t\t\tif (matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER) {\n+\t\t\t\t\trtc_attr.fw_gen_wqe = true;\n+\t\t\t\t\trtc_attr.num_hash_definer = 1;\n+\t\t\t\t}\n \t\t\t}\n \t\t} else if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n@@ -751,7 +773,7 @@ static int mlx5dr_matcher_bind_mt(struct mlx5dr_matcher *matcher)\n \tstruct mlx5dr_pool_attr pool_attr = {0};\n \tint ret;\n \n-\t/* Calculate match and hash definers */\n+\t/* Calculate match, range and hash definers */\n \tret = mlx5dr_definer_matcher_init(ctx, matcher);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to set matcher templates with match definers\");\n@@ -772,6 +794,9 @@ static int mlx5dr_matcher_bind_mt(struct mlx5dr_matcher *matcher)\n \tpool_attr.flags = MLX5DR_POOL_FLAGS_FOR_MATCHER_STE_POOL;\n \tpool_attr.alloc_log_sz = matcher->attr.table.sz_col_log +\n \t\t\t\t matcher->attr.table.sz_row_log;\n+\t/* Add additional rows due to additional range STE */\n+\tif (matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER)\n+\t\tpool_attr.alloc_log_sz++;\n \tmlx5dr_matcher_set_pool_attr(&pool_attr, matcher);\n \n \tmatcher->match_ste.pool = mlx5dr_pool_create(ctx, &pool_attr);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.h b/drivers/net/mlx5/hws/mlx5dr_matcher.h\nindex c012c0c193..a95cfdec6f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.h\n@@ -23,8 +23,9 @@\n #define MLX5DR_MATCHER_ASSURED_MAIN_TBL_DEPTH 2\n \n enum mlx5dr_matcher_flags {\n-\tMLX5DR_MATCHER_FLAGS_HASH_DEFINER\t= 1 << 0,\n-\tMLX5DR_MATCHER_FLAGS_COLISION\t\t= 1 << 1,\n+\tMLX5DR_MATCHER_FLAGS_RANGE_DEFINER\t= 1 << 0,\n+\tMLX5DR_MATCHER_FLAGS_HASH_DEFINER\t= 1 << 1,\n+\tMLX5DR_MATCHER_FLAGS_COLISION\t\t= 1 << 2,\n };\n \n struct mlx5dr_match_template {\n@@ -32,7 +33,9 @@ struct mlx5dr_match_template {\n \tstruct mlx5dr_definer *definer;\n \tstruct mlx5dr_definer *range_definer;\n \tstruct mlx5dr_definer_fc *fc;\n+\tstruct mlx5dr_definer_fc *fcr;\n \tuint16_t fc_sz;\n+\tuint16_t fcr_sz;\n \tuint64_t item_flags;\n \tuint8_t vport_item_id;\n \tenum mlx5dr_match_template_flags flags;\n@@ -80,10 +83,18 @@ mlx5dr_matcher_mt_is_jumbo(struct mlx5dr_match_template *mt)\n \treturn mlx5dr_definer_is_jumbo(mt->definer);\n }\n \n+static inline bool\n+mlx5dr_matcher_mt_is_range(struct mlx5dr_match_template *mt)\n+{\n+\treturn (!!mt->range_definer);\n+}\n+\n static inline bool mlx5dr_matcher_req_fw_wqe(struct mlx5dr_matcher *matcher)\n {\n \t/* Currently HWS doesn't support hash different from match or range */\n-\treturn unlikely(matcher->flags & MLX5DR_MATCHER_FLAGS_HASH_DEFINER);\n+\treturn unlikely(matcher->flags &\n+\t\t\t(MLX5DR_MATCHER_FLAGS_HASH_DEFINER |\n+\t\t\t MLX5DR_MATCHER_FLAGS_RANGE_DEFINER));\n }\n \n int mlx5dr_matcher_conv_items_to_prm(uint64_t *match_buf,\n", "prefixes": [ "v1", "12/16" ] }