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GET /api/patches/119416/?format=api
{ "id": 119416, "url": "https://patches.dpdk.org/api/patches/119416/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221102142500.1731495-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221102142500.1731495-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221102142500.1731495-1-akozyrev@nvidia.com", "date": "2022-11-02T14:25:00", "name": "net/mlx5: fix shared Rx queue config reuse", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "baa1202a087522882541344a6b0083ed9acc736f", "submitter": { "id": 1873, "url": "https://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221102142500.1731495-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 25534, "url": "https://patches.dpdk.org/api/series/25534/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25534", "date": "2022-11-02T14:25:00", "name": "net/mlx5: fix shared Rx queue config reuse", "version": 1, "mbox": "https://patches.dpdk.org/series/25534/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/119416/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/119416/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 80869A00C2;\n\tWed, 2 Nov 2022 15:25:56 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 29B884069C;\n\tWed, 2 Nov 2022 15:25:56 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2053.outbound.protection.outlook.com [40.107.237.53])\n by mails.dpdk.org (Postfix) with ESMTP id 80A9440041;\n Wed, 2 Nov 2022 15:25:54 +0100 (CET)", "from DS7PR03CA0334.namprd03.prod.outlook.com (2603:10b6:8:55::11) by\n BL1PR12MB5898.namprd12.prod.outlook.com (2603:10b6:208:396::7) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5769.15; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<stable@dpdk.org>, <rasland@nvidia.com>, <viacheslavo@nvidia.com>,\n <matan@nvidia.com>, <xuemingl@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix shared Rx queue config reuse", "Date": "Wed, 2 Nov 2022 16:25:00 +0200", "Message-ID": "<20221102142500.1731495-1-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT019:EE_|BL1PR12MB5898:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7c4d9af1-1483-4048-eff7-08dabcde2511", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n hchq+L44ewtdIixOtohbgrIMm40NpC+xplO8du5HHo8SsGHrbvnv+Kmug3NK6daOYFsNriJCLB1Qqs0w7D9inBp746pGU/Wz4Khj4btt3bU4N0WdRD5TN/Z27aUB8a/CV9E4WV0vUts5scFshrrQl/IimqMxu8v0SDLYEg9z+Eh3/vitzvikwe/F+JIxR14fMp7Z3SWHlbms7Pj20DQ1Euc8AZNcqT8bFp5u8K850r06CUqMBEfyj3T3MgdlvWQBCy8qYcjB5TlRmVvSXUH+FP+tGOTLxmD8U2hqmwJlmAZFrFN01VxDEnGYsKN8yY0nPvLHiFi/xEGMRhjZt6T8hw6R2Eo/KsQlz81vnTN6/69pm+HXOq9ETpyeCd+i8Sgmo6HnPYdNxfmb1XcX0QfpZSeyn7Ovsi7T4kjd67/7DcB0WmB7FDcrOwqZ080JVE2/20Qir+fgv6L0pT9/KU91pWEQo8yNu6JeTLePOUAZDWQVka+PxOcnD3O5FN7nkPUddRUlWZyW4Q/Z8X8JRO2CWojwkFzrQTx4OBIe4Sr8OwFLaIzfqHrtIC95dCDotX6XUWU3b8icAvF0w3iZwALbOFRCgyssQeOmhTSIyfP2G3ZAotU4jSqdnAXyc3Bd2UlcExvZQNRXrqLjo78GFzTbr0ANq9p8onStqV6T1v46kieIlnA+nrdxHs5iVm1UpDAb6vPn0+0q0Gmjg+DwQCUSETj81aP1UmKohWyH6RuYgDJcsNIEsQWcoVX7MfEMMkyb0mvKkMxbMni8FYsxm1tPBw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199015)(40470700004)(46966006)(36840700001)(36756003)(40480700001)(107886003)(47076005)(36860700001)(70586007)(5660300002)(82740400003)(7636003)(356005)(2906002)(83380400001)(426003)(86362001)(336012)(478600001)(316002)(186003)(16526019)(26005)(450100002)(54906003)(6916009)(41300700001)(40460700003)(8936002)(70206006)(2616005)(4326008)(6666004)(8676002)(82310400005)(1076003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Nov 2022 14:25:51.5478 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7c4d9af1-1483-4048-eff7-08dabcde2511", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT019.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5898", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is a check for the configuration match between\nall the Rx queues shared among multiple ports in DPDK.\nThis check ensures that the configuration is the same.\n\nThe issue is this check takes place before the queue\nis released and configured again in case of reconfiguration.\nThat leads to checking against the old configuration and\npreventing the shared Rx queue to start properly.\n\nRelease the old configuration and prepare a new Rx queue\nbefore checking that its parameters match the config.\n\nFixes: 09c2555303 (\"net/mlx5: support shared Rx queue\")\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 10 +++++++---\n 1 file changed, 7 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b7818f9598..0d9d11680b 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -902,16 +902,20 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t/* Try to reuse shared RXQ. */\n \t\trxq_ctrl = mlx5_shared_rxq_get(dev, conf->share_group,\n \t\t\t\t\t conf->share_qid);\n+\t\tres = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl);\n+\t\tif (res)\n+\t\t\treturn res;\n \t\tif (rxq_ctrl != NULL &&\n \t\t !mlx5_shared_rxq_match(rxq_ctrl, dev, idx, desc, socket,\n \t\t\t\t\t conf, mp)) {\n \t\t\trte_errno = EINVAL;\n \t\t\treturn -rte_errno;\n \t\t}\n+\t} else {\n+\t\tres = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl);\n+\t\tif (res)\n+\t\t\treturn res;\n \t}\n-\tres = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl);\n-\tif (res)\n-\t\treturn res;\n \t/* Allocate RXQ. */\n \trxq = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*rxq), 0,\n \t\t\t SOCKET_ID_ANY);\n", "prefixes": [] }