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GET /api/patches/119371/?format=api
{ "id": 119371, "url": "https://patches.dpdk.org/api/patches/119371/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-6-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221031160824.330200-6-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221031160824.330200-6-michaelba@nvidia.com", "date": "2022-10-31T16:08:24", "name": "[5/5] net/mlx5: assert for enough space in counter rings", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "980d6199b833e7564226b9d1a8e6554325eab6b5", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-6-michaelba@nvidia.com/mbox/", "series": [ { "id": 25498, "url": "https://patches.dpdk.org/api/series/25498/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25498", "date": "2022-10-31T16:08:19", "name": "net/mlx5: some counter fixes", "version": 1, "mbox": "https://patches.dpdk.org/series/25498/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/119371/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/119371/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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"Subject": "[PATCH 5/5] net/mlx5: assert for enough space in counter rings", "Date": "Mon, 31 Oct 2022 18:08:24 +0200", "Message-ID": "<20221031160824.330200-6-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221031160824.330200-1-michaelba@nvidia.com>", "References": "<20221031160824.330200-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT004:EE_|SA1PR12MB7223:EE_", "X-MS-Office365-Filtering-Correlation-Id": "33bf08db-4a27-4b26-b9d0-08dabb5a3396", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(40460700003)(2616005)(82310400005)(5660300002)(478600001)(47076005)(426003)(8936002)(7696005)(36860700001)(40480700001)(82740400003)(1076003)(6916009)(186003)(41300700001)(356005)(36756003)(7636003)(54906003)(4326008)(30864003)(2906002)(83380400001)(70586007)(6286002)(336012)(316002)(86362001)(70206006)(26005)(6666004)(107886003)(55016003)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Oct 2022 16:08:51.1438 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 33bf08db-4a27-4b26-b9d0-08dabb5a3396", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT004.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7223", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is a by-design assumption in the code that the global counter\nrings can contain all the port counters.\nSo, enqueuing to these global rings should always succeed.\n\nAdd assertions to help for debugging this assumption.\n\nIn addition, change mlx5_hws_cnt_pool_put() function to return void due\nto those assumptions.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Xiaoyu Min <jackmin@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 2 +-\n drivers/net/mlx5/mlx5_hws_cnt.c | 25 ++++----\n drivers/net/mlx5/mlx5_hws_cnt.h | 106 +++++++++++++++++---------------\n 3 files changed, 72 insertions(+), 61 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 2d275ad111..54a0afe45f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -7874,7 +7874,7 @@ flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\t * time to update the AGE.\n \t\t\t */\n \t\t\tmlx5_hws_age_nb_cnt_decrease(priv, age_idx);\n-\t\tret = mlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);\n+\t\tmlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_CT:\n \t\tret = flow_hw_conntrack_destroy(dev, act_idx, error);\ndiff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c\nindex b8ce69af57..24c01eace0 100644\n--- a/drivers/net/mlx5/mlx5_hws_cnt.c\n+++ b/drivers/net/mlx5/mlx5_hws_cnt.c\n@@ -58,13 +58,14 @@ __hws_cnt_id_load(struct mlx5_hws_cnt_pool *cpool)\n \n static void\n __mlx5_hws_cnt_svc(struct mlx5_dev_ctx_shared *sh,\n-\t\tstruct mlx5_hws_cnt_pool *cpool)\n+\t\t struct mlx5_hws_cnt_pool *cpool)\n {\n \tstruct rte_ring *reset_list = cpool->wait_reset_list;\n \tstruct rte_ring *reuse_list = cpool->reuse_list;\n \tuint32_t reset_cnt_num;\n \tstruct rte_ring_zc_data zcdr = {0};\n \tstruct rte_ring_zc_data zcdu = {0};\n+\tuint32_t ret __rte_unused;\n \n \treset_cnt_num = rte_ring_count(reset_list);\n \tdo {\n@@ -72,17 +73,19 @@ __mlx5_hws_cnt_svc(struct mlx5_dev_ctx_shared *sh,\n \t\tmlx5_aso_cnt_query(sh, cpool);\n \t\tzcdr.n1 = 0;\n \t\tzcdu.n1 = 0;\n-\t\trte_ring_enqueue_zc_burst_elem_start(reuse_list,\n-\t\t\t\tsizeof(cnt_id_t), reset_cnt_num, &zcdu,\n-\t\t\t\tNULL);\n-\t\trte_ring_dequeue_zc_burst_elem_start(reset_list,\n-\t\t\t\tsizeof(cnt_id_t), reset_cnt_num, &zcdr,\n-\t\t\t\tNULL);\n+\t\tret = rte_ring_enqueue_zc_burst_elem_start(reuse_list,\n+\t\t\t\t\t\t\t sizeof(cnt_id_t),\n+\t\t\t\t\t\t\t reset_cnt_num, &zcdu,\n+\t\t\t\t\t\t\t NULL);\n+\t\tMLX5_ASSERT(ret == reset_cnt_num);\n+\t\tret = rte_ring_dequeue_zc_burst_elem_start(reset_list,\n+\t\t\t\t\t\t\t sizeof(cnt_id_t),\n+\t\t\t\t\t\t\t reset_cnt_num, &zcdr,\n+\t\t\t\t\t\t\t NULL);\n+\t\tMLX5_ASSERT(ret == reset_cnt_num);\n \t\t__hws_cnt_r2rcpy(&zcdu, &zcdr, reset_cnt_num);\n-\t\trte_ring_dequeue_zc_elem_finish(reset_list,\n-\t\t\t\treset_cnt_num);\n-\t\trte_ring_enqueue_zc_elem_finish(reuse_list,\n-\t\t\t\treset_cnt_num);\n+\t\trte_ring_dequeue_zc_elem_finish(reset_list, reset_cnt_num);\n+\t\trte_ring_enqueue_zc_elem_finish(reuse_list, reset_cnt_num);\n \t\treset_cnt_num = rte_ring_count(reset_list);\n \t} while (reset_cnt_num > 0);\n }\ndiff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h\nindex 338ee4d688..030dcead86 100644\n--- a/drivers/net/mlx5/mlx5_hws_cnt.h\n+++ b/drivers/net/mlx5/mlx5_hws_cnt.h\n@@ -116,7 +116,7 @@ enum {\n \tHWS_AGE_CANDIDATE_INSIDE_RING,\n \t/*\n \t * AGE assigned to flows but it still in ring. It was aged-out but the\n-\t * timeout was changed, so it in ring but stiil candidate.\n+\t * timeout was changed, so it in ring but still candidate.\n \t */\n \tHWS_AGE_AGED_OUT_REPORTED,\n \t/*\n@@ -182,7 +182,7 @@ mlx5_hws_cnt_id_valid(cnt_id_t cnt_id)\n *\n * @param cpool\n * The pointer to counter pool\n- * @param index\n+ * @param iidx\n * The internal counter index.\n *\n * @return\n@@ -231,32 +231,32 @@ __hws_cnt_query_raw(struct mlx5_hws_cnt_pool *cpool, cnt_id_t cnt_id,\n }\n \n /**\n- * Copy elems from one zero-copy ring to zero-copy ring in place.\n+ * Copy elements from one zero-copy ring to zero-copy ring in place.\n *\n * The input is a rte ring zero-copy data struct, which has two pointer.\n * in case of the wrapper happened, the ptr2 will be meaningful.\n *\n- * So this rountin needs to consider the situation that the address given by\n+ * So this routine needs to consider the situation that the address given by\n * source and destination could be both wrapped.\n * First, calculate the first number of element needs to be copied until wrapped\n * address, which could be in source or destination.\n * Second, copy left number of element until second wrapped address. If in first\n * step the wrapped address is source, then this time it must be in destination.\n- * and vice-vers.\n- * Third, copy all left numbe of element.\n+ * and vice-versa.\n+ * Third, copy all left number of element.\n *\n * In worst case, we need copy three pieces of continuous memory.\n *\n * @param zcdd\n- * A pointer to zero-copy data of dest ring.\n+ * A pointer to zero-copy data of destination ring.\n * @param zcds\n * A pointer to zero-copy data of source ring.\n * @param n\n- * Number of elems to copy.\n+ * Number of elements to copy.\n */\n static __rte_always_inline void\n __hws_cnt_r2rcpy(struct rte_ring_zc_data *zcdd, struct rte_ring_zc_data *zcds,\n-\t\tunsigned int n)\n+\t\t unsigned int n)\n {\n \tunsigned int n1, n2, n3;\n \tvoid *s1, *s2, *s3;\n@@ -291,22 +291,23 @@ static __rte_always_inline int\n mlx5_hws_cnt_pool_cache_flush(struct mlx5_hws_cnt_pool *cpool,\n \t\t\t uint32_t queue_id)\n {\n-\tunsigned int ret;\n+\tunsigned int ret __rte_unused;\n \tstruct rte_ring_zc_data zcdr = {0};\n \tstruct rte_ring_zc_data zcdc = {0};\n \tstruct rte_ring *reset_list = NULL;\n \tstruct rte_ring *qcache = cpool->cache->qcache[queue_id];\n+\tuint32_t ring_size = rte_ring_count(qcache);\n \n-\tret = rte_ring_dequeue_zc_burst_elem_start(qcache,\n-\t\t\tsizeof(cnt_id_t), rte_ring_count(qcache), &zcdc,\n-\t\t\tNULL);\n-\tMLX5_ASSERT(ret);\n+\tret = rte_ring_dequeue_zc_burst_elem_start(qcache, sizeof(cnt_id_t),\n+\t\t\t\t\t\t ring_size, &zcdc, NULL);\n+\tMLX5_ASSERT(ret == ring_size);\n \treset_list = cpool->wait_reset_list;\n-\trte_ring_enqueue_zc_burst_elem_start(reset_list,\n-\t\t\tsizeof(cnt_id_t), ret, &zcdr, NULL);\n-\t__hws_cnt_r2rcpy(&zcdr, &zcdc, ret);\n-\trte_ring_enqueue_zc_elem_finish(reset_list, ret);\n-\trte_ring_dequeue_zc_elem_finish(qcache, ret);\n+\tret = rte_ring_enqueue_zc_burst_elem_start(reset_list, sizeof(cnt_id_t),\n+\t\t\t\t\t\t ring_size, &zcdr, NULL);\n+\tMLX5_ASSERT(ret == ring_size);\n+\t__hws_cnt_r2rcpy(&zcdr, &zcdc, ring_size);\n+\trte_ring_enqueue_zc_elem_finish(reset_list, ring_size);\n+\trte_ring_dequeue_zc_elem_finish(qcache, ring_size);\n \treturn 0;\n }\n \n@@ -323,7 +324,7 @@ mlx5_hws_cnt_pool_cache_fetch(struct mlx5_hws_cnt_pool *cpool,\n \tstruct rte_ring_zc_data zcdu = {0};\n \tstruct rte_ring_zc_data zcds = {0};\n \tstruct mlx5_hws_cnt_pool_caches *cache = cpool->cache;\n-\tunsigned int ret;\n+\tunsigned int ret, actual_fetch_size __rte_unused;\n \n \treuse_list = cpool->reuse_list;\n \tret = rte_ring_dequeue_zc_burst_elem_start(reuse_list,\n@@ -334,7 +335,9 @@ mlx5_hws_cnt_pool_cache_fetch(struct mlx5_hws_cnt_pool *cpool,\n \t\trte_ring_dequeue_zc_elem_finish(reuse_list, 0);\n \t\tfree_list = cpool->free_list;\n \t\tret = rte_ring_dequeue_zc_burst_elem_start(free_list,\n-\t\t\t\tsizeof(cnt_id_t), cache->fetch_sz, &zcdf, NULL);\n+\t\t\t\t\t\t\t sizeof(cnt_id_t),\n+\t\t\t\t\t\t\t cache->fetch_sz,\n+\t\t\t\t\t\t\t &zcdf, NULL);\n \t\tzcds = zcdf;\n \t\tlist = free_list;\n \t\tif (unlikely(ret == 0)) { /* no free counter. */\n@@ -344,8 +347,10 @@ mlx5_hws_cnt_pool_cache_fetch(struct mlx5_hws_cnt_pool *cpool,\n \t\t\treturn -ENOENT;\n \t\t}\n \t}\n-\trte_ring_enqueue_zc_burst_elem_start(qcache, sizeof(cnt_id_t),\n-\t\t\tret, &zcdc, NULL);\n+\tactual_fetch_size = ret;\n+\tret = rte_ring_enqueue_zc_burst_elem_start(qcache, sizeof(cnt_id_t),\n+\t\t\t\t\t\t ret, &zcdc, NULL);\n+\tMLX5_ASSERT(ret == actual_fetch_size);\n \t__hws_cnt_r2rcpy(&zcdc, &zcds, ret);\n \trte_ring_dequeue_zc_elem_finish(list, ret);\n \trte_ring_enqueue_zc_elem_finish(qcache, ret);\n@@ -378,15 +383,14 @@ __mlx5_hws_cnt_pool_enqueue_revert(struct rte_ring *r, unsigned int n,\n *\n * @param cpool\n * A pointer to the counter pool structure.\n+ * @param queue\n+ * A pointer to HWS queue. If null, it means put into common pool.\n * @param cnt_id\n * A counter id to be added.\n- * @return\n- * - 0: Success; object taken\n- * - -ENOENT: not enough entry in pool\n */\n-static __rte_always_inline int\n-mlx5_hws_cnt_pool_put(struct mlx5_hws_cnt_pool *cpool,\n-\t\tuint32_t *queue, cnt_id_t *cnt_id)\n+static __rte_always_inline void\n+mlx5_hws_cnt_pool_put(struct mlx5_hws_cnt_pool *cpool, uint32_t *queue,\n+\t\t cnt_id_t *cnt_id)\n {\n \tunsigned int ret = 0;\n \tstruct rte_ring_zc_data zcdc = {0};\n@@ -404,25 +408,29 @@ mlx5_hws_cnt_pool_put(struct mlx5_hws_cnt_pool *cpool,\n \t\tqcache = cpool->cache->qcache[*queue];\n \tif (unlikely(qcache == NULL)) {\n \t\tret = rte_ring_enqueue_elem(cpool->wait_reset_list, cnt_id,\n-\t\t\t\tsizeof(cnt_id_t));\n+\t\t\t\t\t sizeof(cnt_id_t));\n \t\tMLX5_ASSERT(ret == 0);\n-\t\treturn ret;\n+\t\treturn;\n \t}\n \tret = rte_ring_enqueue_burst_elem(qcache, cnt_id, sizeof(cnt_id_t), 1,\n \t\t\t\t\t NULL);\n \tif (unlikely(ret == 0)) { /* cache is full. */\n+\t\tstruct rte_ring *reset_list = cpool->wait_reset_list;\n+\n \t\twb_num = rte_ring_count(qcache) - cpool->cache->threshold;\n \t\tMLX5_ASSERT(wb_num < rte_ring_count(qcache));\n \t\t__mlx5_hws_cnt_pool_enqueue_revert(qcache, wb_num, &zcdc);\n-\t\trte_ring_enqueue_zc_burst_elem_start(cpool->wait_reset_list,\n-\t\t\t\tsizeof(cnt_id_t), wb_num, &zcdr, NULL);\n-\t\t__hws_cnt_r2rcpy(&zcdr, &zcdc, wb_num);\n-\t\trte_ring_enqueue_zc_elem_finish(cpool->wait_reset_list, wb_num);\n+\t\tret = rte_ring_enqueue_zc_burst_elem_start(reset_list,\n+\t\t\t\t\t\t\t sizeof(cnt_id_t),\n+\t\t\t\t\t\t\t wb_num, &zcdr, NULL);\n+\t\tMLX5_ASSERT(ret == wb_num);\n+\t\t__hws_cnt_r2rcpy(&zcdr, &zcdc, ret);\n+\t\trte_ring_enqueue_zc_elem_finish(reset_list, ret);\n \t\t/* write-back THIS counter too */\n-\t\tret = rte_ring_enqueue_burst_elem(cpool->wait_reset_list,\n-\t\t\t\tcnt_id, sizeof(cnt_id_t), 1, NULL);\n+\t\tret = rte_ring_enqueue_burst_elem(reset_list, cnt_id,\n+\t\t\t\t\t\t sizeof(cnt_id_t), 1, NULL);\n \t}\n-\treturn ret == 1 ? 0 : -ENOENT;\n+\tMLX5_ASSERT(ret == 1);\n }\n \n /**\n@@ -482,15 +490,17 @@ mlx5_hws_cnt_pool_get(struct mlx5_hws_cnt_pool *cpool, uint32_t *queue,\n \t\treturn 0;\n \t}\n \tret = rte_ring_dequeue_zc_burst_elem_start(qcache, sizeof(cnt_id_t), 1,\n-\t\t\t&zcdc, NULL);\n+\t\t\t\t\t\t &zcdc, NULL);\n \tif (unlikely(ret == 0)) { /* local cache is empty. */\n \t\trte_ring_dequeue_zc_elem_finish(qcache, 0);\n \t\t/* let's fetch from global free list. */\n \t\tret = mlx5_hws_cnt_pool_cache_fetch(cpool, *queue);\n \t\tif (unlikely(ret != 0))\n \t\t\treturn ret;\n-\t\trte_ring_dequeue_zc_burst_elem_start(qcache, sizeof(cnt_id_t),\n-\t\t\t\t1, &zcdc, NULL);\n+\t\tret = rte_ring_dequeue_zc_burst_elem_start(qcache,\n+\t\t\t\t\t\t\t sizeof(cnt_id_t), 1,\n+\t\t\t\t\t\t\t &zcdc, NULL);\n+\t\tMLX5_ASSERT(ret == 1);\n \t}\n \t/* get one from local cache. */\n \t*cnt_id = (*(cnt_id_t *)zcdc.ptr1);\n@@ -504,8 +514,10 @@ mlx5_hws_cnt_pool_get(struct mlx5_hws_cnt_pool *cpool, uint32_t *queue,\n \t\tret = mlx5_hws_cnt_pool_cache_fetch(cpool, *queue);\n \t\tif (unlikely(ret != 0))\n \t\t\treturn ret;\n-\t\trte_ring_dequeue_zc_burst_elem_start(qcache, sizeof(cnt_id_t),\n-\t\t\t\t1, &zcdc, NULL);\n+\t\tret = rte_ring_dequeue_zc_burst_elem_start(qcache,\n+\t\t\t\t\t\t\t sizeof(cnt_id_t), 1,\n+\t\t\t\t\t\t\t &zcdc, NULL);\n+\t\tMLX5_ASSERT(ret == 1);\n \t\t*cnt_id = *(cnt_id_t *)zcdc.ptr1;\n \t\tiidx = mlx5_hws_cnt_iidx(cpool, *cnt_id);\n \t}\n@@ -553,17 +565,13 @@ mlx5_hws_cnt_shared_get(struct mlx5_hws_cnt_pool *cpool, cnt_id_t *cnt_id,\n \treturn 0;\n }\n \n-static __rte_always_inline int\n+static __rte_always_inline void\n mlx5_hws_cnt_shared_put(struct mlx5_hws_cnt_pool *cpool, cnt_id_t *cnt_id)\n {\n-\tint ret;\n \tuint32_t iidx = mlx5_hws_cnt_iidx(cpool, *cnt_id);\n \n \tcpool->pool[iidx].share = 0;\n-\tret = mlx5_hws_cnt_pool_put(cpool, NULL, cnt_id);\n-\tif (unlikely(ret != 0))\n-\t\tcpool->pool[iidx].share = 1; /* fail to release, restore. */\n-\treturn ret;\n+\tmlx5_hws_cnt_pool_put(cpool, NULL, cnt_id);\n }\n \n static __rte_always_inline bool\n", "prefixes": [ "5/5" ] }