Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/119367/?format=api
{ "id": 119367, "url": "https://patches.dpdk.org/api/patches/119367/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221031160824.330200-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221031160824.330200-2-michaelba@nvidia.com", "date": "2022-10-31T16:08:20", "name": "[1/5] net/mlx5: fix race condition in counter pool resizing", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a5c5455504945ac274dd3aa3cfd53bf9a9d5d098", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 25498, "url": "https://patches.dpdk.org/api/series/25498/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25498", "date": "2022-10-31T16:08:19", "name": "net/mlx5: some counter fixes", "version": 1, "mbox": "https://patches.dpdk.org/series/25498/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/119367/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/119367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CFAAEA0540;\n\tMon, 31 Oct 2022 17:08:49 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4DE85410F2;\n\tMon, 31 Oct 2022 17:08:44 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id 3AD2040151;\n Mon, 31 Oct 2022 17:08:41 +0100 (CET)", "from BN9PR03CA0937.namprd03.prod.outlook.com (2603:10b6:408:108::12)\n by MN2PR12MB4109.namprd12.prod.outlook.com (2603:10b6:208:1d9::13)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.16; Mon, 31 Oct\n 2022 16:08:39 +0000", "from BN8NAM11FT034.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:108:cafe::7d) by BN9PR03CA0937.outlook.office365.com\n (2603:10b6:408:108::12) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19 via Frontend\n Transport; Mon, 31 Oct 2022 16:08:39 +0000", "from mail.nvidia.com (216.228.118.232) by\n BN8NAM11FT034.mail.protection.outlook.com (10.13.176.139) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5769.14 via Frontend Transport; Mon, 31 Oct 2022 16:08:38 +0000", "from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com\n (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Mon, 31 Oct\n 2022 09:08:31 -0700", "from drhqmail203.nvidia.com (10.126.190.182) by\n drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.986.29; Mon, 31 Oct 2022 09:08:31 -0700", "from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29 via Frontend\n Transport; Mon, 31 Oct 2022 09:08:29 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=N014IjoOvLI13btTcWBluZoy0c+Yqr6I2NodAS1XjG8JBQUGpg6YL9D/KtKapLey84kNHQZAIEA+EaJSrx+ob4SAYYzlBa3FSU97IAeXsYIsejfTy9c7tNibuVnsyVr5yvN/sfbaglVuXnODAze0VdFCCOOVdPYW1JrXvXAbTNa/mTviECVcfdgYNjIAwE3LT0062JMQweO/Emz6MaTcTdgXyeibmjf45lhVO5whWB2WZIJLDVxNh16qkyjuRyxJpyRGx409ydi0zfwkgTfaElyMB9nl/GCYLenErdiME8XBI4FInE4ffcdlDJVwzLi36z1FGLesGeLHCVlIupm9+Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=vCP+cQ5BkgEEk4BT0OfU5sX6nIBRKj5sPRSn5o0DvLA=;\n b=CY9oCy0nTRHR9VZuEjkdqLk5ud/0aO9rb6hbVEkp3c6APYAz1clw0Ig8ESXo4YHDsE+Hcwx0X9ooiYTWC9vqAeTRFdZ4ESfoI/jkNp/yUdiMndmT3jpUucuJ8zL3DVn5Tc3HEoSADu7iwUSHfEdOd18f6TZCyBane1Y7zEh/dHdHy/FlRfEdxF4BCVRN2cKm0cNf8Hog+AysDytdFVk4m814OPyhsF7xtkZiQ0TEXIEZFlkCIx34lUpBMhom+u9F3YaXEMOhO2jqju6mMh1Ta0YVarufcuBlmlIMBIfr42fYHexLGwY9A1CVnLMa5yaAHbquwY/COml4Q4jW5FN6xw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=vCP+cQ5BkgEEk4BT0OfU5sX6nIBRKj5sPRSn5o0DvLA=;\n b=I7sgxKwjqeGY97tnDOosxAG/35peY1Q7CQmMoBWifrTqtTfJ93/M3eEDG6pr0Z+4dhl9RAp8u3H/rfF2C8NHM9dz8/Z2HEO9STSPkJZacLBsqQmJfbeW/MRM3H+PjEfvanRhLWcUjIUXS+AyDMvy9fi8ktvNhEEF0zjwFrj7v2OAc25F9XofsTZcP0wS8+Mfn3ICVs4YKcnrGY+mQoOPn6QTkw2ybUUxbMfbr0Xw4pvkz2Hra6BChipwZ2anWRlwNENU50tqfXjMBIlbu3UcYge4uTdlZIRVbuUb38GPBbELIkDdqiNyIRZ/zCUCJU+VjD9MWV2VxbjmGpru7xHA8A==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.118.232)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.118.232 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>,\n <stable@dpdk.org>", "Subject": "[PATCH 1/5] net/mlx5: fix race condition in counter pool resizing", "Date": "Mon, 31 Oct 2022 18:08:20 +0200", "Message-ID": "<20221031160824.330200-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221031160824.330200-1-michaelba@nvidia.com>", "References": "<20221031160824.330200-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT034:EE_|MN2PR12MB4109:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6adcbac8-55dc-4b7c-e893-08dabb5a2c46", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n K/tRsyRs8hyR689km1/3e4pmO069ZSkFXiHatKU+IseTLDHSYRT7vioeMCyEmHZubpGEf/A+0mif/BqAh+OKZ4wtTyHm4b1DfgTMKb4w3juTlbFAkagn+oMqXU8rSVbJu+xI8ea0uras3AS32p8tHuFZGpqBrcQFHgaZnZ+8GyHYi+rjFafMOOFrerZ5YxRKACmBu+ymU++dDopjJPM2Nd6sycHcMO9scI6LCSHjvPGP27yemsgBbc6EvlRLUJgxWt7FSxxmnpNL0u7Kkq+qqcbMkfVMmTnWxlYOrw1TdaANETOzaiaMo1md0m5X2TKkY6+JSDdLCsh95n2lxgf0x92aYKAQg7oXKejNcO3S5whIpSOyg0CMwp4AQXOTLkff3wLwLdaRLbMF2rMGHOx/CNyxibZx5aEZXrEHjee4I36dQoaOaIYpZzGsTlG4Lu6dsjGNlf7Ia7k1YKRdjkCFmd2wGOf5rOJZ6gp6FyZZFsBN6S9c5JZGTnrh/A9FY8EJRGY8z+Ww5lXMI+WUJnDdO3cSHDf1fQoXoLTpdtNbCs1t4oXAT+MH91ZQsr8L9HOW/J4n7r+mUlOy+YRVf5+T98SjuNKT2UkZC5zxQkpIG9UA8Qao+ZgKqwxLthuQEft++S61em454+7tUP2xhMUNQT/wKvrY8OH0Lh1IS4+sOMRUCS2WgvRs9Q4jY8lNyi7LuMmJ5GwECD6qZzT74EgO92zDilMnR9qtBsrrggbk0NqDiucHW3/WD2Q0Y69aZwrhDA2dcRpfQi7tTdYdqecqDA==", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(6666004)(6286002)(478600001)(26005)(316002)(54906003)(6916009)(7696005)(82310400005)(55016003)(36860700001)(7636003)(47076005)(40460700003)(40480700001)(336012)(356005)(36756003)(2616005)(82740400003)(1076003)(186003)(83380400001)(86362001)(426003)(2906002)(4326008)(70586007)(8676002)(70206006)(41300700001)(30864003)(450100002)(8936002)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Oct 2022 16:08:38.8766 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6adcbac8-55dc-4b7c-e893-08dabb5a2c46", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT034.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4109", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Counter management structure has array of counter pools. This array is\ninvalid in management structure initialization and grows on demand.\n\nThe resizing include:\n1. Allocate memory for the new size.\n2. Copy the existing data to the new memory.\n3. Move the pointer to the new memory.\n4. Free the old memory.\n\nThe third step can be performed before for this function, and compiler\nmay do that, but another thread might read the pointer before coping and\nread invalid data or even crash.\n\nThis patch allocates memory for this array once in management structure\ninitialization and limit the counters number by 16M.\n\nFixes: 3aa279157fa0 (\"net/mlx5: synchronize flow counter pool creation\")\nCc: suanmingm@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 28 +++++++++++++---\n drivers/net/mlx5/mlx5.h | 7 ++--\n drivers/net/mlx5/mlx5_flow.c | 24 +++++++-------\n drivers/net/mlx5/mlx5_flow_dv.c | 53 +++++-------------------------\n drivers/net/mlx5/mlx5_flow_verbs.c | 23 +++----------\n 5 files changed, 52 insertions(+), 83 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 78234b116c..b85a56ec24 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -561,18 +561,34 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n *\n * @param[in] sh\n * Pointer to mlx5_dev_ctx_shared object to free\n+ *\n+ * @return\n+ * 0 on success, otherwise negative errno value and rte_errno is set.\n */\n-static void\n+static int\n mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)\n {\n \tint i, j;\n \n \tif (sh->config.dv_flow_en < 2) {\n+\t\tvoid *pools;\n+\n+\t\tpools = mlx5_malloc(MLX5_MEM_ZERO,\n+\t\t\t\t sizeof(struct mlx5_flow_counter_pool *) *\n+\t\t\t\t MLX5_COUNTER_POOLS_MAX_NUM,\n+\t\t\t\t 0, SOCKET_ID_ANY);\n+\t\tif (!pools) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Counter management allocation was failed.\");\n+\t\t\trte_errno = ENOMEM;\n+\t\t\treturn -rte_errno;\n+\t\t}\n \t\tmemset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng));\n \t\tTAILQ_INIT(&sh->sws_cmng.flow_counters);\n \t\tsh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET;\n \t\tsh->sws_cmng.max_id = -1;\n \t\tsh->sws_cmng.last_pool_idx = POOL_IDX_INVALID;\n+\t\tsh->sws_cmng.pools = pools;\n \t\trte_spinlock_init(&sh->sws_cmng.pool_update_sl);\n \t\tfor (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {\n \t\t\tTAILQ_INIT(&sh->sws_cmng.counters[i]);\n@@ -598,6 +614,7 @@ mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)\n \t\tsh->hws_max_log_bulk_sz = log_dcs;\n \t\tsh->hws_max_nb_counters = max_nb_cnts;\n \t}\n+\treturn 0;\n }\n \n /**\n@@ -655,8 +672,7 @@ mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)\n \t\t\t\t\tclaim_zero\n \t\t\t\t\t (mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t (cnt->action));\n-\t\t\t\tif (fallback && MLX5_POOL_GET_CNT\n-\t\t\t\t (pool, j)->dcs_when_free)\n+\t\t\t\tif (fallback && cnt->dcs_when_free)\n \t\t\t\t\tclaim_zero(mlx5_devx_cmd_destroy\n \t\t\t\t\t\t (cnt->dcs_when_free));\n \t\t\t}\n@@ -1572,8 +1588,12 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tif (err)\n \t\t\tgoto error;\n \t}\n+\terr = mlx5_flow_counters_mng_init(sh);\n+\tif (err) {\n+\t\tDRV_LOG(ERR, \"Fail to initialize counters manage.\");\n+\t\tgoto error;\n+\t}\n \tmlx5_flow_aging_init(sh);\n-\tmlx5_flow_counters_mng_init(sh);\n \tmlx5_flow_ipool_create(sh);\n \t/* Add context to the global device list. */\n \tLIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c9fcb71b69..cbe2d88b9e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -386,11 +386,10 @@ struct mlx5_hw_q {\n } __rte_cache_aligned;\n \n \n-\n-\n+#define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15)\n #define MLX5_COUNTERS_PER_POOL 512\n #define MLX5_MAX_PENDING_QUERIES 4\n-#define MLX5_CNT_CONTAINER_RESIZE 64\n+#define MLX5_CNT_MR_ALLOC_BULK 64\n #define MLX5_CNT_SHARED_OFFSET 0x80000000\n #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \\\n \t\t\t MLX5_CNT_BATCH_OFFSET)\n@@ -549,7 +548,6 @@ TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);\n /* Counter global management structure. */\n struct mlx5_flow_counter_mng {\n \tvolatile uint16_t n_valid; /* Number of valid pools. */\n-\tuint16_t n; /* Number of pools. */\n \tuint16_t last_pool_idx; /* Last used pool index */\n \tint min_id; /* The minimum counter ID in the pools. */\n \tint max_id; /* The maximum counter ID in the pools. */\n@@ -621,6 +619,7 @@ struct mlx5_aso_age_action {\n };\n \n #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512\n+#define MLX5_ASO_AGE_CONTAINER_RESIZE 64\n \n struct mlx5_aso_age_pool {\n \tstruct mlx5_devx_obj *flow_hit_aso_obj;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 8e7d649d15..e25154199f 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -9063,7 +9063,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_counter_stats_mem_mng *mem_mng;\n \tvolatile struct flow_counter_stats *raw_data;\n-\tint raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES;\n+\tint raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES;\n \tint size = (sizeof(struct flow_counter_stats) *\n \t\t\tMLX5_COUNTERS_PER_POOL +\n \t\t\tsizeof(struct mlx5_counter_stats_raw)) * raws_n +\n@@ -9101,7 +9101,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)\n \t}\n \tfor (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)\n \t\tLIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws,\n-\t\t\t\t mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i,\n+\t\t\t\t mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i,\n \t\t\t\t next);\n \tLIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next);\n \tsh->sws_cmng.mem_mng = mem_mng;\n@@ -9125,14 +9125,13 @@ mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh,\n {\n \tstruct mlx5_flow_counter_mng *cmng = &sh->sws_cmng;\n \t/* Resize statistic memory once used out. */\n-\tif (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) &&\n+\tif (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) &&\n \t mlx5_flow_create_counter_stat_mem_mng(sh)) {\n \t\tDRV_LOG(ERR, \"Cannot resize counter stat mem.\");\n \t\treturn -1;\n \t}\n \trte_spinlock_lock(&pool->sl);\n-\tpool->raw = cmng->mem_mng->raws + pool->index %\n-\t\t MLX5_CNT_CONTAINER_RESIZE;\n+\tpool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK;\n \trte_spinlock_unlock(&pool->sl);\n \tpool->raw_hw = NULL;\n \treturn 0;\n@@ -9174,13 +9173,13 @@ void\n mlx5_flow_query_alarm(void *arg)\n {\n \tstruct mlx5_dev_ctx_shared *sh = arg;\n-\tint ret;\n-\tuint16_t pool_index = sh->sws_cmng.pool_index;\n \tstruct mlx5_flow_counter_mng *cmng = &sh->sws_cmng;\n+\tuint16_t pool_index = cmng->pool_index;\n \tstruct mlx5_flow_counter_pool *pool;\n \tuint16_t n_valid;\n+\tint ret;\n \n-\tif (sh->sws_cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES)\n+\tif (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES)\n \t\tgoto set_alarm;\n \trte_spinlock_lock(&cmng->pool_update_sl);\n \tpool = cmng->pools[pool_index];\n@@ -9192,8 +9191,7 @@ mlx5_flow_query_alarm(void *arg)\n \tif (pool->raw_hw)\n \t\t/* There is a pool query in progress. */\n \t\tgoto set_alarm;\n-\tpool->raw_hw =\n-\t\tLIST_FIRST(&sh->sws_cmng.free_stat_raws);\n+\tpool->raw_hw = LIST_FIRST(&cmng->free_stat_raws);\n \tif (!pool->raw_hw)\n \t\t/* No free counter statistics raw memory. */\n \t\tgoto set_alarm;\n@@ -9219,12 +9217,12 @@ mlx5_flow_query_alarm(void *arg)\n \t\tgoto set_alarm;\n \t}\n \tLIST_REMOVE(pool->raw_hw, next);\n-\tsh->sws_cmng.pending_queries++;\n+\tcmng->pending_queries++;\n \tpool_index++;\n \tif (pool_index >= n_valid)\n \t\tpool_index = 0;\n set_alarm:\n-\tsh->sws_cmng.pool_index = pool_index;\n+\tcmng->pool_index = pool_index;\n \tmlx5_set_query_alarm(sh);\n }\n \n@@ -9755,7 +9753,7 @@ mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev,\n \t}\n \n \t/* get counter */\n-\tMLX5_ASSERT(cmng->n_valid <= cmng->n);\n+\tMLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM);\n \tmax = MLX5_COUNTERS_PER_POOL * cmng->n_valid;\n \tfor (j = 1; j <= max; j++) {\n \t\taction = NULL;\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 1e52278191..e77cbb862b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -6091,7 +6091,7 @@ flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,\n \n \t/* Decrease to original index and clear shared bit. */\n \tidx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);\n-\tMLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);\n+\tMLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < MLX5_COUNTER_POOLS_MAX_NUM);\n \tpool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];\n \tMLX5_ASSERT(pool);\n \tif (ppool)\n@@ -6167,39 +6167,6 @@ flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)\n \treturn pool;\n }\n \n-/**\n- * Resize a counter container.\n- *\n- * @param[in] dev\n- * Pointer to the Ethernet device structure.\n- *\n- * @return\n- * 0 on success, otherwise negative errno value and rte_errno is set.\n- */\n-static int\n-flow_dv_container_resize(struct rte_eth_dev *dev)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng;\n-\tvoid *old_pools = cmng->pools;\n-\tuint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;\n-\tuint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;\n-\tvoid *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);\n-\n-\tif (!pools) {\n-\t\trte_errno = ENOMEM;\n-\t\treturn -ENOMEM;\n-\t}\n-\tif (old_pools)\n-\t\tmemcpy(pools, old_pools, cmng->n *\n-\t\t\t\t sizeof(struct mlx5_flow_counter_pool *));\n-\tcmng->n = resize;\n-\tcmng->pools = pools;\n-\tif (old_pools)\n-\t\tmlx5_free(old_pools);\n-\treturn 0;\n-}\n-\n /**\n * Query a devx flow counter.\n *\n@@ -6251,8 +6218,6 @@ _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,\n * The devX counter handle.\n * @param[in] age\n * Whether the pool is for counter that was allocated for aging.\n- * @param[in/out] cont_cur\n- * Pointer to the container pointer, it will be update in pool resize.\n *\n * @return\n * The pool container pointer on success, NULL otherwise and rte_errno is set.\n@@ -6264,9 +6229,14 @@ flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_flow_counter_pool *pool;\n \tstruct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng;\n-\tbool fallback = priv->sh->sws_cmng.counter_fallback;\n+\tbool fallback = cmng->counter_fallback;\n \tuint32_t size = sizeof(*pool);\n \n+\tif (cmng->n_valid == MLX5_COUNTER_POOLS_MAX_NUM) {\n+\t\tDRV_LOG(ERR, \"All counter is in used, try again later.\");\n+\t\trte_errno = EAGAIN;\n+\t\treturn NULL;\n+\t}\n \tsize += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;\n \tsize += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);\n \tpool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);\n@@ -6285,11 +6255,6 @@ flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,\n \tpool->time_of_last_age_check = MLX5_CURR_TIME_SEC;\n \trte_spinlock_lock(&cmng->pool_update_sl);\n \tpool->index = cmng->n_valid;\n-\tif (pool->index == cmng->n && flow_dv_container_resize(dev)) {\n-\t\tmlx5_free(pool);\n-\t\trte_spinlock_unlock(&cmng->pool_update_sl);\n-\t\treturn NULL;\n-\t}\n \tcmng->pools[pool->index] = pool;\n \tcmng->n_valid++;\n \tif (unlikely(fallback)) {\n@@ -12511,7 +12476,7 @@ flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)\n }\n \n /**\n- * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.\n+ * Resize the ASO age pools array by MLX5_ASO_AGE_CONTAINER_RESIZE pools.\n *\n * @param[in] dev\n * Pointer to the Ethernet device structure.\n@@ -12525,7 +12490,7 @@ flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;\n \tvoid *old_pools = mng->pools;\n-\tuint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;\n+\tuint32_t resize = mng->n + MLX5_ASO_AGE_CONTAINER_RESIZE;\n \tuint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;\n \tvoid *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex 81a33ddf09..4bca685674 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -232,27 +232,14 @@ flow_verbs_counter_new(struct rte_eth_dev *dev, uint32_t id __rte_unused)\n \t\t\tbreak;\n \t}\n \tif (!cnt) {\n-\t\tstruct mlx5_flow_counter_pool **pools;\n \t\tuint32_t size;\n \n-\t\tif (n_valid == cmng->n) {\n-\t\t\t/* Resize the container pool array. */\n-\t\t\tsize = sizeof(struct mlx5_flow_counter_pool *) *\n-\t\t\t\t (n_valid + MLX5_CNT_CONTAINER_RESIZE);\n-\t\t\tpools = mlx5_malloc(MLX5_MEM_ZERO, size, 0,\n-\t\t\t\t\t SOCKET_ID_ANY);\n-\t\t\tif (!pools)\n-\t\t\t\treturn 0;\n-\t\t\tif (n_valid) {\n-\t\t\t\tmemcpy(pools, cmng->pools,\n-\t\t\t\t sizeof(struct mlx5_flow_counter_pool *) *\n-\t\t\t\t n_valid);\n-\t\t\t\tmlx5_free(cmng->pools);\n-\t\t\t}\n-\t\t\tcmng->pools = pools;\n-\t\t\tcmng->n += MLX5_CNT_CONTAINER_RESIZE;\n+\t\tif (n_valid == MLX5_COUNTER_POOLS_MAX_NUM) {\n+\t\t\tDRV_LOG(ERR, \"All counter is in used, try again later.\");\n+\t\t\trte_errno = EAGAIN;\n+\t\t\treturn 0;\n \t\t}\n-\t\t/* Allocate memory for new pool*/\n+\t\t/* Allocate memory for new pool */\n \t\tsize = sizeof(*pool) + sizeof(*cnt) * MLX5_COUNTERS_PER_POOL;\n \t\tpool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);\n \t\tif (!pool)\n", "prefixes": [ "1/5" ] }