Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/119277/?format=api
{ "id": 119277, "url": "https://patches.dpdk.org/api/patches/119277/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221029032729.22772-11-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221029032729.22772-11-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221029032729.22772-11-beilei.xing@intel.com", "date": "2022-10-29T03:27:21", "name": "[v15,10/18] net/idpf: add support for basic Rx datapath", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "98aa9069d475681b0105373efa361fe88f470c8b", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221029032729.22772-11-beilei.xing@intel.com/mbox/", "series": [ { "id": 25480, "url": "https://patches.dpdk.org/api/series/25480/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25480", "date": "2022-10-29T03:27:11", "name": "add support for idpf PMD in DPDK", "version": 15, "mbox": "https://patches.dpdk.org/series/25480/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/119277/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/119277/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6EBAA00C4;\n\tSat, 29 Oct 2022 05:58:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 92E82427F6;\n\tSat, 29 Oct 2022 05:58:11 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 1B523427F7\n for <dev@dpdk.org>; Sat, 29 Oct 2022 05:57:55 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Oct 2022 20:57:55 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by fmsmga007.fm.intel.com with ESMTP; 28 Oct 2022 20:57:53 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1667015876; x=1698551876;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=X5780iKEyX4idL1oA45PI2Ib31V4TojLXr3JkPW1CSA=;\n b=dR+IBe78No24UEUbpE0s+48s2E2nAtqEzvBbKTNqcAdmgvY9wQUi8IcI\n OdM1OIlcyflxeFiRhA7W9W7CLaYej1Y8k4OJcRksumPFZoKdJteEmgkIW\n sZqG5g8Ep1/iRudzhJQVGY/qyPBSI+O4VMjPmKdutGNMm37P+ptQrbgxf\n n/SOjeasRR9r+pgEvHQ5ODj80YhMlPnIew9pZxAVD4rO4FY+RrdbwLnpb\n PlgQVBl0IhDfT24YmGrZ7nS4E/qFv59x+YxbxinFp0U7TQRgdukmUnYU6\n AX35X38+nz40wcIArs/bI9dZgO4aPfJ0b9JbWUU1D9LkpnfZEUi32y7ka Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10514\"; a=\"296043740\"", "E=Sophos;i=\"5.95,222,1661842800\"; d=\"scan'208\";a=\"296043740\"", "E=McAfee;i=\"6500,9779,10514\"; a=\"635523898\"", "E=Sophos;i=\"5.95,222,1661842800\"; d=\"scan'208\";a=\"635523898\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "andrew.rybchenko@oktetlabs.ru, jingjing.wu@intel.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Xiaoyun Li <xiaoyun.li@intel.com>", "Subject": "[PATCH v15 10/18] net/idpf: add support for basic Rx datapath", "Date": "Sat, 29 Oct 2022 03:27:21 +0000", "Message-Id": "<20221029032729.22772-11-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20221029032729.22772-1-beilei.xing@intel.com>", "References": "<20221027074729.1494529-1-junfeng.guo@intel.com>\n <20221029032729.22772-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Junfeng Guo <junfeng.guo@intel.com>\n\nAdd basic Rx support in split queue mode and single queue mode.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/idpf/idpf_ethdev.c | 2 +\n drivers/net/idpf/idpf_rxtx.c | 273 +++++++++++++++++++++++++++++++++\n drivers/net/idpf/idpf_rxtx.h | 7 +-\n 3 files changed, 281 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex 856f3d7266..2f1f9eeee5 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -348,6 +348,8 @@ idpf_dev_start(struct rte_eth_dev *dev)\n \t\tgoto err_mtu;\n \t}\n \n+\tidpf_set_rx_function(dev);\n+\n \tret = idpf_vc_ena_dis_vport(vport, true);\n \tif (ret != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to enable vport\");\ndiff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c\nindex 053409b99a..ea499c4d37 100644\n--- a/drivers/net/idpf/idpf_rxtx.c\n+++ b/drivers/net/idpf/idpf_rxtx.c\n@@ -1208,3 +1208,276 @@ idpf_stop_queues(struct rte_eth_dev *dev)\n \t\t\tPMD_DRV_LOG(WARNING, \"Fail to stop Tx queue %d\", i);\n \t}\n }\n+\n+static void\n+idpf_split_rx_bufq_refill(struct idpf_rx_queue *rx_bufq)\n+{\n+\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_ring;\n+\tvolatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_desc;\n+\tuint16_t nb_refill = rx_bufq->rx_free_thresh;\n+\tuint16_t nb_desc = rx_bufq->nb_rx_desc;\n+\tuint16_t next_avail = rx_bufq->rx_tail;\n+\tstruct rte_mbuf *nmb[rx_bufq->rx_free_thresh];\n+\tstruct rte_eth_dev *dev;\n+\tuint64_t dma_addr;\n+\tuint16_t delta;\n+\tint i;\n+\n+\tif (rx_bufq->nb_rx_hold < rx_bufq->rx_free_thresh)\n+\t\treturn;\n+\n+\trx_buf_ring = rx_bufq->rx_ring;\n+\tdelta = nb_desc - next_avail;\n+\tif (unlikely(delta < nb_refill)) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, delta) == 0)) {\n+\t\t\tfor (i = 0; i < delta; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->hdr_addr = 0;\n+\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnb_refill -= delta;\n+\t\t\tnext_avail = 0;\n+\t\t\trx_bufq->nb_rx_hold -= delta;\n+\t\t} else {\n+\t\t\tdev = &rte_eth_devices[rx_bufq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;\n+\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tif (nb_desc - next_avail >= nb_refill) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, nb_refill) == 0)) {\n+\t\t\tfor (i = 0; i < nb_refill; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trx_bufq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->hdr_addr = 0;\n+\t\t\t\trx_buf_desc->pkt_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnext_avail += nb_refill;\n+\t\t\trx_bufq->nb_rx_hold -= nb_refill;\n+\t\t} else {\n+\t\t\tdev = &rte_eth_devices[rx_bufq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;\n+\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t\t rx_bufq->port_id, rx_bufq->queue_id);\n+\t\t}\n+\t}\n+\n+\tIDPF_PCI_REG_WRITE(rx_bufq->qrx_tail, next_avail);\n+\n+\trx_bufq->rx_tail = next_avail;\n+}\n+\n+uint16_t\n+idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tvolatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc_ring;\n+\tvolatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc;\n+\tuint16_t pktlen_gen_bufq_id;\n+\tstruct idpf_rx_queue *rxq;\n+\tstruct rte_mbuf *rxm;\n+\tuint16_t rx_id_bufq1;\n+\tuint16_t rx_id_bufq2;\n+\tuint16_t pkt_len;\n+\tuint16_t bufq_id;\n+\tuint16_t gen_id;\n+\tuint16_t rx_id;\n+\tuint16_t nb_rx;\n+\n+\tnb_rx = 0;\n+\trxq = rx_queue;\n+\n+\tif (unlikely(rxq == NULL) || unlikely(!rxq->q_started))\n+\t\treturn nb_rx;\n+\n+\trx_id = rxq->rx_tail;\n+\trx_id_bufq1 = rxq->bufq1->rx_next_avail;\n+\trx_id_bufq2 = rxq->bufq2->rx_next_avail;\n+\trx_desc_ring = rxq->rx_ring;\n+\n+\twhile (nb_rx < nb_pkts) {\n+\t\trx_desc = &rx_desc_ring[rx_id];\n+\n+\t\tpktlen_gen_bufq_id =\n+\t\t\trte_le_to_cpu_16(rx_desc->pktlen_gen_bufq_id);\n+\t\tgen_id = (pktlen_gen_bufq_id &\n+\t\t\t VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M) >>\n+\t\t\tVIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S;\n+\t\tif (gen_id != rxq->expected_gen_id)\n+\t\t\tbreak;\n+\n+\t\tpkt_len = (pktlen_gen_bufq_id &\n+\t\t\t VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M) >>\n+\t\t\tVIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S;\n+\t\tif (pkt_len == 0)\n+\t\t\tPMD_RX_LOG(ERR, \"Packet length is 0\");\n+\n+\t\trx_id++;\n+\t\tif (unlikely(rx_id == rxq->nb_rx_desc)) {\n+\t\t\trx_id = 0;\n+\t\t\trxq->expected_gen_id ^= 1;\n+\t\t}\n+\n+\t\tbufq_id = (pktlen_gen_bufq_id &\n+\t\t\t VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M) >>\n+\t\t\tVIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S;\n+\t\tif (bufq_id == 0) {\n+\t\t\trxm = rxq->bufq1->sw_ring[rx_id_bufq1];\n+\t\t\trx_id_bufq1++;\n+\t\t\tif (unlikely(rx_id_bufq1 == rxq->bufq1->nb_rx_desc))\n+\t\t\t\trx_id_bufq1 = 0;\n+\t\t\trxq->bufq1->nb_rx_hold++;\n+\t\t} else {\n+\t\t\trxm = rxq->bufq2->sw_ring[rx_id_bufq2];\n+\t\t\trx_id_bufq2++;\n+\t\t\tif (unlikely(rx_id_bufq2 == rxq->bufq2->nb_rx_desc))\n+\t\t\t\trx_id_bufq2 = 0;\n+\t\t\trxq->bufq2->nb_rx_hold++;\n+\t\t}\n+\n+\t\trxm->pkt_len = pkt_len;\n+\t\trxm->data_len = pkt_len;\n+\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\trxm->next = NULL;\n+\t\trxm->nb_segs = 1;\n+\t\trxm->port = rxq->port_id;\n+\n+\t\trx_pkts[nb_rx++] = rxm;\n+\t}\n+\n+\tif (nb_rx > 0) {\n+\t\trxq->rx_tail = rx_id;\n+\t\tif (rx_id_bufq1 != rxq->bufq1->rx_next_avail)\n+\t\t\trxq->bufq1->rx_next_avail = rx_id_bufq1;\n+\t\tif (rx_id_bufq2 != rxq->bufq2->rx_next_avail)\n+\t\t\trxq->bufq2->rx_next_avail = rx_id_bufq2;\n+\n+\t\tidpf_split_rx_bufq_refill(rxq->bufq1);\n+\t\tidpf_split_rx_bufq_refill(rxq->bufq2);\n+\t}\n+\n+\treturn nb_rx;\n+}\n+\n+static inline void\n+idpf_update_rx_tail(struct idpf_rx_queue *rxq, uint16_t nb_hold,\n+\t\t uint16_t rx_id)\n+{\n+\tnb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);\n+\n+\tif (nb_hold > rxq->rx_free_thresh) {\n+\t\tPMD_RX_LOG(DEBUG,\n+\t\t\t \"port_id=%u queue_id=%u rx_tail=%u nb_hold=%u\",\n+\t\t\t rxq->port_id, rxq->queue_id, rx_id, nb_hold);\n+\t\trx_id = (uint16_t)((rx_id == 0) ?\n+\t\t\t\t (rxq->nb_rx_desc - 1) : (rx_id - 1));\n+\t\tIDPF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n+\t\tnb_hold = 0;\n+\t}\n+\trxq->nb_rx_hold = nb_hold;\n+}\n+\n+uint16_t\n+idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tvolatile union virtchnl2_rx_desc *rx_ring;\n+\tvolatile union virtchnl2_rx_desc *rxdp;\n+\tunion virtchnl2_rx_desc rxd;\n+\tstruct idpf_rx_queue *rxq;\n+\tuint16_t rx_id, nb_hold;\n+\tstruct rte_eth_dev *dev;\n+\tuint16_t rx_packet_len;\n+\tstruct rte_mbuf *rxm;\n+\tstruct rte_mbuf *nmb;\n+\tuint16_t rx_status0;\n+\tuint64_t dma_addr;\n+\tuint16_t nb_rx;\n+\n+\tnb_rx = 0;\n+\tnb_hold = 0;\n+\trxq = rx_queue;\n+\n+\tif (unlikely(rxq == NULL) || unlikely(!rxq->q_started))\n+\t\treturn nb_rx;\n+\n+\trx_id = rxq->rx_tail;\n+\trx_ring = rxq->rx_ring;\n+\n+\twhile (nb_rx < nb_pkts) {\n+\t\trxdp = &rx_ring[rx_id];\n+\t\trx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);\n+\n+\t\t/* Check the DD bit first */\n+\t\tif ((rx_status0 & (1 << VIRTCHNL2_RX_FLEX_DESC_STATUS0_DD_S)) == 0)\n+\t\t\tbreak;\n+\n+\t\tnmb = rte_mbuf_raw_alloc(rxq->mp);\n+\t\tif (unlikely(nmb == NULL)) {\n+\t\t\tdev = &rte_eth_devices[rxq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed++;\n+\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n+\t\t\t\t \"queue_id=%u\", rxq->port_id, rxq->queue_id);\n+\t\t\tbreak;\n+\t\t}\n+\t\trxd = *rxdp; /* copy descriptor in ring to temp variable*/\n+\n+\t\tnb_hold++;\n+\t\trxm = rxq->sw_ring[rx_id];\n+\t\trxq->sw_ring[rx_id] = nmb;\n+\t\trx_id++;\n+\t\tif (unlikely(rx_id == rxq->nb_rx_desc))\n+\t\t\trx_id = 0;\n+\n+\t\t/* Prefetch next mbuf */\n+\t\trte_prefetch0(rxq->sw_ring[rx_id]);\n+\n+\t\t/* When next RX descriptor is on a cache line boundary,\n+\t\t * prefetch the next 4 RX descriptors and next 8 pointers\n+\t\t * to mbufs.\n+\t\t */\n+\t\tif ((rx_id & 0x3) == 0) {\n+\t\t\trte_prefetch0(&rx_ring[rx_id]);\n+\t\t\trte_prefetch0(rxq->sw_ring[rx_id]);\n+\t\t}\n+\t\tdma_addr =\n+\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));\n+\t\trxdp->read.hdr_addr = 0;\n+\t\trxdp->read.pkt_addr = dma_addr;\n+\n+\t\trx_packet_len = (rte_cpu_to_le_16(rxd.flex_nic_wb.pkt_len) &\n+\t\t\t\t VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M);\n+\n+\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\trte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));\n+\t\trxm->nb_segs = 1;\n+\t\trxm->next = NULL;\n+\t\trxm->pkt_len = rx_packet_len;\n+\t\trxm->data_len = rx_packet_len;\n+\t\trxm->port = rxq->port_id;\n+\n+\t\trx_pkts[nb_rx++] = rxm;\n+\t}\n+\trxq->rx_tail = rx_id;\n+\n+\tidpf_update_rx_tail(rxq, nb_hold, rx_id);\n+\n+\treturn nb_rx;\n+}\n+\n+void\n+idpf_set_rx_function(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT)\n+\t\tdev->rx_pkt_burst = idpf_splitq_recv_pkts;\n+\telse\n+\t\tdev->rx_pkt_burst = idpf_singleq_recv_pkts;\n+}\ndiff --git a/drivers/net/idpf/idpf_rxtx.h b/drivers/net/idpf/idpf_rxtx.h\nindex 37944edcac..650c6c1c3a 100644\n--- a/drivers/net/idpf/idpf_rxtx.h\n+++ b/drivers/net/idpf/idpf_rxtx.h\n@@ -133,6 +133,11 @@ int idpf_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n int idpf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n int idpf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n void idpf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);\n-\n+uint16_t idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\tuint16_t nb_pkts);\n+uint16_t idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts);\n void idpf_stop_queues(struct rte_eth_dev *dev);\n+\n+void idpf_set_rx_function(struct rte_eth_dev *dev);\n #endif /* _IDPF_RXTX_H_ */\n", "prefixes": [ "v15", "10/18" ] }