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GET /api/patches/118664/?format=api
{ "id": 118664, "url": "https://patches.dpdk.org/api/patches/118664/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221019205721.8077-9-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221019205721.8077-9-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221019205721.8077-9-valex@nvidia.com", "date": "2022-10-19T20:57:11", "name": "[v5,08/18] net/mlx5/hws: Add HWS command layer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ed8b2598e8ea7556f1a88ac4e97ac45820d28364", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221019205721.8077-9-valex@nvidia.com/mbox/", "series": [ { "id": 25322, "url": "https://patches.dpdk.org/api/series/25322/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25322", "date": "2022-10-19T20:57:03", "name": "net/mlx5: Add HW steering low level support", "version": 5, "mbox": "https://patches.dpdk.org/series/25322/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118664/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/118664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=Pe6GSq1/XbjZKFP2+UQ8AHKhymCmMaCqdVXPow0xPey/jsrnSFQt5TXtORUq2/AnSy4eoWLYM2DANE0o7WkafBKUQPal/eu1MDl/OXwaoX7V7nL43+nCk3KnFxmGp0RjUO7tht00GbVdjPwu3GWS86XqLFRu32Jeyy11xUhdY4qMKUSh+NEOJq+05LdkxM64g+ouEY14HmacpfgxcoDrL/0LhmwxBxrNRy8r8xdP/nUtiYeR4X2kLjgdQYmknmb7dEZLAFV/MCOtYopFqftdLBGyeHsOkaYUeq7YdERS7t5SCuUFsAmDbTutBbOjgHoYOg90tFRi2f9SD+6AlA9cFA==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Erez Shitrit <erezsh@nvidia.com>", "Subject": "[v5 08/18] net/mlx5/hws: Add HWS command layer", "Date": "Wed, 19 Oct 2022 23:57:11 +0300", "Message-ID": "<20221019205721.8077-9-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221019205721.8077-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221019205721.8077-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT039:EE_|SA1PR12MB5614:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e3df4be0-efd1-4596-2a36-08dab214a353", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n v6X0TWb4UKf9jreheJKreIQQiq6/ANBFznXRhNY+etwP4xZHZc6Hk1tVs/1y2hThAzz20nMSPMcZm/RGlj51tWoBMqw2e1IgoO1mgquN6yYl024WuyYRoOABC9P8FPQMDvXQo6Sz8M6kfVCa+xADpsmr9g4UgdEVa3oA+Xl436otUVJC5stdhI8zI1X4ifDK7pFvCPpylOO16SGAhOv9jjk8ikKLlvjpECMeHRC37ZU6hocOXFQPpvhgBUaZYBvsM6S8KXVW7gky+P6XogDRiIHpgrRTkcnly8Yp3QALkanbAWmPFWedC+4zyzKJxD8eyPIVPf1p/8acnqArEi2zmZ2stOZSfE9IoSzpoe4QUyolqJe/wOlKpN+N3i7u+tRLPzctxwU5LTMu78ffqzxpDOtuJeKrs1S6v2ZSti3dvs9I/9AEVEJQuhKEycpxc4YYpqDIIlgzvkhioakXNVFFS6aDLkAQnJYfTvomKcGp41ZNrj83aXsUeCAbXWV2j73SG+fRmbTblWYWhlR991ts1mVYMox+H4tLuApTSlTvf9vA5u3ssZ/3L6BYJuhE4MjG/9TkuycnzzWEg5Kl/J9AEBjlrE5qBjBCwp+fMh4/TsgHYVvHw1JzOC3vh87HQBvSze273ZmH3R+ykjdLBNp26rxNyug/nXgu3uSBrdQI4TDjB0pZvWGrdn2kal9d2OlzHbkCkH1IsgdMO3pIXsMF4aqEOpjtG5n8IK+4e4ZCyM5biP1bZZ2JQqSxZLXwf4lmRBFuy8nBwm1ULy4Oc/tdSA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(2906002)(30864003)(5660300002)(41300700001)(8936002)(82310400005)(478600001)(70586007)(316002)(55016003)(70206006)(40480700001)(82740400003)(2616005)(8676002)(107886003)(6666004)(4326008)(36756003)(54906003)(6636002)(6286002)(110136005)(7696005)(26005)(356005)(7636003)(86362001)(40460700003)(426003)(36860700001)(47076005)(1076003)(336012)(83380400001)(186003)(16526019)(579004)(559001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2022 20:58:13.4010 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e3df4be0-efd1-4596-2a36-08dab214a353", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT039.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB5614", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Erez Shitrit <erezsh@nvidia.com>\n\nThe command layer is used to communicate with the FW,\nquery capabilities and allocate FW resources needed for HWS.\n\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 607 ++++++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 948 ++++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 230 ++++++++\n 3 files changed, 1775 insertions(+), 10 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.h", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ca4763f53d..371942ae50 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -289,6 +289,8 @@\n /* The alignment needed for CQ buffer. */\n #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()\n \n+#define MAX_ACTIONS_DATA_IN_HEADER_MODIFY 512\n+\n /* Completion mode. */\n enum mlx5_completion_mode {\n \tMLX5_COMP_ONLY_ERR = 0x0,\n@@ -677,6 +679,10 @@ enum {\n \tMLX5_MODIFICATION_TYPE_SET = 0x1,\n \tMLX5_MODIFICATION_TYPE_ADD = 0x2,\n \tMLX5_MODIFICATION_TYPE_COPY = 0x3,\n+\tMLX5_MODIFICATION_TYPE_INSERT = 0x4,\n+\tMLX5_MODIFICATION_TYPE_REMOVE = 0x5,\n+\tMLX5_MODIFICATION_TYPE_NOP = 0x6,\n+\tMLX5_MODIFICATION_TYPE_REMOVE_WORDS = 0x7,\n };\n \n /* The field of packet to be modified. */\n@@ -1111,6 +1117,10 @@ enum {\n \tMLX5_CMD_OP_QUERY_TIS = 0x915,\n \tMLX5_CMD_OP_CREATE_RQT = 0x916,\n \tMLX5_CMD_OP_MODIFY_RQT = 0x917,\n+\tMLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,\n+\tMLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,\n+\tMLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,\n+\tMLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n \tMLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,\n@@ -1299,6 +1309,7 @@ enum {\n \tMLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE = 0x1B << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,\n };\n@@ -1317,6 +1328,14 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_RTC \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_RTC)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_STC \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_STC)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_STE \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_STE)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_DEFINER \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_DEFINER)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \\\n@@ -1373,6 +1392,11 @@ enum {\n #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)\n #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)\n #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)\n+#define MLX5_HCA_FLEX_GTPU_ENABLED (1UL << 11)\n+#define MLX5_HCA_FLEX_GTPU_DW_2_ENABLED (1UL << 16)\n+#define MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED (1UL << 17)\n+#define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18)\n+#define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19)\n \n /* The device steering logic format. */\n #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0\n@@ -1505,7 +1529,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 wol_u[0x1];\n \tu8 wol_p[0x1];\n \tu8 stat_rate_support[0x10];\n-\tu8 reserved_at_1f0[0xc];\n+\tu8 reserved_at_1ef[0xb];\n+\tu8 wqe_based_flow_table_update_cap[0x1];\n \tu8 cqe_version[0x4];\n \tu8 compact_address_vector[0x1];\n \tu8 striding_rq[0x1];\n@@ -1681,7 +1706,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 cqe_compression[0x1];\n \tu8 cqe_compression_timeout[0x10];\n \tu8 cqe_compression_max_num[0x10];\n-\tu8 reserved_at_5e0[0x10];\n+\tu8 reserved_at_5e0[0x8];\n+\tu8 flex_parser_id_gtpu_dw_0[0x4];\n+\tu8 reserved_at_5ec[0x4];\n \tu8 tag_matching[0x1];\n \tu8 rndv_offload_rc[0x1];\n \tu8 rndv_offload_dc[0x1];\n@@ -1691,17 +1718,38 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 affiliate_nic_vport_criteria[0x8];\n \tu8 native_port_num[0x8];\n \tu8 num_vhca_ports[0x8];\n-\tu8 reserved_at_618[0x6];\n+\tu8 flex_parser_id_gtpu_teid[0x4];\n+\tu8 reserved_at_61c[0x2];\n \tu8 sw_owner_id[0x1];\n \tu8 reserved_at_61f[0x6C];\n \tu8 wait_on_data[0x1];\n \tu8 wait_on_time[0x1];\n-\tu8 reserved_at_68d[0xBB];\n+\tu8 reserved_at_68d[0x37];\n+\tu8 flex_parser_id_geneve_opt_0[0x4];\n+\tu8 flex_parser_id_icmp_dw1[0x4];\n+\tu8 flex_parser_id_icmp_dw0[0x4];\n+\tu8 flex_parser_id_icmpv6_dw1[0x4];\n+\tu8 flex_parser_id_icmpv6_dw0[0x4];\n+\tu8 flex_parser_id_outer_first_mpls_over_gre[0x4];\n+\tu8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];\n+\tu8 reserved_at_6e0[0x20];\n+\tu8 flex_parser_id_gtpu_dw_2[0x4];\n+\tu8 flex_parser_id_gtpu_first_ext_dw_0[0x4];\n+\tu8 reserved_at_708[0x40];\n \tu8 dma_mmo_qp[0x1];\n \tu8 regexp_mmo_qp[0x1];\n \tu8 compress_mmo_qp[0x1];\n \tu8 decompress_mmo_qp[0x1];\n-\tu8 reserved_at_624[0xd4];\n+\tu8 reserved_at_74c[0x14];\n+\tu8 reserved_at_760[0x3];\n+\tu8 log_max_num_header_modify_argument[0x5];\n+\tu8 log_header_modify_argument_granularity_offset[0x4];\n+\tu8 log_header_modify_argument_granularity[0x4];\n+\tu8 reserved_at_770[0x3];\n+\tu8 log_header_modify_argument_max_alloc[0x5];\n+\tu8 reserved_at_778[0x8];\n+\tu8 reserved_at_780[0x40];\n+\tu8 match_definer_format_supported[0x40];\n };\n \n struct mlx5_ifc_qos_cap_bits {\n@@ -1876,7 +1924,9 @@ struct mlx5_ifc_flow_table_prop_layout_bits {\n \tu8 log_max_ft_sampler_num[8];\n \tu8 metadata_reg_b_width[0x8];\n \tu8 metadata_reg_a_width[0x8];\n-\tu8 reserved_at_60[0x18];\n+\tu8 reserved_at_60[0xa];\n+\tu8 reparse[0x1];\n+\tu8 reserved_at_6b[0xd];\n \tu8 log_max_ft_num[0x8];\n \tu8 reserved_at_80[0x10];\n \tu8 log_max_flow_counter[0x8];\n@@ -2061,7 +2111,17 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 hairpin_sq_wqe_bb_size[0x5];\n \tu8 hairpin_sq_wq_in_host_mem[0x1];\n \tu8 hairpin_data_buffer_locked[0x1];\n-\tu8 reserved_at_16a[0x696];\n+\tu8 reserved_at_16a[0x36];\n+\tu8 reserved_at_1a0[0xb];\n+\tu8 format_select_dw_8_6_ext[0x1];\n+\tu8 reserved_at_1ac[0x14];\n+\tu8 general_obj_types_127_64[0x40];\n+\tu8 reserved_at_200[0x80];\n+\tu8 format_select_dw_gtpu_dw_0[0x8];\n+\tu8 format_select_dw_gtpu_dw_1[0x8];\n+\tu8 format_select_dw_gtpu_dw_2[0x8];\n+\tu8 format_select_dw_gtpu_first_ext_dw_0[0x8];\n+\tu8 reserved_at_2a0[0x560];\n };\n \n struct mlx5_ifc_esw_cap_bits {\n@@ -2074,6 +2134,37 @@ struct mlx5_ifc_esw_cap_bits {\n \tu8 reserved_at_80[0x780];\n };\n \n+struct mlx5_ifc_wqe_based_flow_table_cap_bits {\n+\tu8 reserved_at_0[0x3];\n+\tu8 log_max_num_ste[0x5];\n+\tu8 reserved_at_8[0x3];\n+\tu8 log_max_num_stc[0x5];\n+\tu8 reserved_at_10[0x3];\n+\tu8 log_max_num_rtc[0x5];\n+\tu8 reserved_at_18[0x3];\n+\tu8 log_max_num_header_modify_pattern[0x5];\n+\tu8 reserved_at_20[0x3];\n+\tu8 stc_alloc_log_granularity[0x5];\n+\tu8 reserved_at_28[0x3];\n+\tu8 stc_alloc_log_max[0x5];\n+\tu8 reserved_at_30[0x3];\n+\tu8 ste_alloc_log_granularity[0x5];\n+\tu8 reserved_at_38[0x3];\n+\tu8 ste_alloc_log_max[0x5];\n+\tu8 reserved_at_40[0xb];\n+\tu8 rtc_reparse_mode[0x5];\n+\tu8 reserved_at_50[0x3];\n+\tu8 rtc_index_mode[0x5];\n+\tu8 reserved_at_58[0x3];\n+\tu8 rtc_log_depth_max[0x5];\n+\tu8 reserved_at_60[0x10];\n+\tu8 ste_format[0x10];\n+\tu8 stc_action_type[0x80];\n+\tu8 header_insert_type[0x10];\n+\tu8 header_remove_type[0x10];\n+\tu8 trivial_match_definer[0x20];\n+};\n+\n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n \tstruct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;\n@@ -2085,6 +2176,7 @@ union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap;\n \tstruct mlx5_ifc_esw_cap_bits esw_cap;\n \tstruct mlx5_ifc_roce_caps_bits roce_caps;\n+\tstruct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;\n \tu8 reserved_at_0[0x8000];\n };\n \n@@ -2098,6 +2190,20 @@ struct mlx5_ifc_set_action_in_bits {\n \tu8 data[0x20];\n };\n \n+struct mlx5_ifc_copy_action_in_bits {\n+\tu8 action_type[0x4];\n+\tu8 src_field[0xc];\n+\tu8 reserved_at_10[0x3];\n+\tu8 src_offset[0x5];\n+\tu8 reserved_at_18[0x3];\n+\tu8 length[0x5];\n+\tu8 reserved_at_20[0x4];\n+\tu8 dst_field[0xc];\n+\tu8 reserved_at_30[0x3];\n+\tu8 dst_offset[0x5];\n+\tu8 reserved_at_38[0x8];\n+};\n+\n struct mlx5_ifc_query_hca_cap_out_bits {\n \tu8 status[0x8];\n \tu8 reserved_at_8[0x18];\n@@ -2978,6 +3084,7 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,\n \tMLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n+\tMLX5_GENERAL_OBJ_TYPE_DEFINER = 0x0018,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,\n \tMLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,\n@@ -2986,6 +3093,11 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,\n \tMLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,\n+\tMLX5_GENERAL_OBJ_TYPE_ARG = 0x0023,\n+\tMLX5_GENERAL_OBJ_TYPE_STC = 0x0040,\n+\tMLX5_GENERAL_OBJ_TYPE_RTC = 0x0041,\n+\tMLX5_GENERAL_OBJ_TYPE_STE = 0x0042,\n+\tMLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN = 0x0043,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n@@ -2993,9 +3105,14 @@ struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n \tu8 reserved_at_10[0x20];\n \tu8 obj_type[0x10];\n \tu8 obj_id[0x20];\n-\tu8 reserved_at_60[0x3];\n-\tu8 log_obj_range[0x5];\n-\tu8 reserved_at_58[0x18];\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 reserved_at_60[0x3];\n+\t\t\tu8 log_obj_range[0x5];\n+\t\t\tu8 reserved_at_58[0x18];\n+\t\t};\n+\t\tu8 obj_offset[0x20];\n+\t};\n };\n \n struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n@@ -3029,6 +3146,243 @@ struct mlx5_ifc_geneve_tlv_option_bits {\n \tu8 reserved_at_80[0x180];\n };\n \n+\n+enum mlx5_ifc_rtc_update_mode {\n+\tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0,\n+\tMLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1,\n+};\n+\n+enum mlx5_ifc_rtc_ste_format {\n+\tMLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,\n+\tMLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,\n+};\n+\n+enum mlx5_ifc_rtc_reparse_mode {\n+\tMLX5_IFC_RTC_REPARSE_NEVER = 0x0,\n+\tMLX5_IFC_RTC_REPARSE_ALWAYS = 0x1,\n+};\n+\n+struct mlx5_ifc_rtc_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x40];\n+\tu8 update_index_mode[0x2];\n+\tu8 reparse_mode[0x2];\n+\tu8 reserved_at_84[0x4];\n+\tu8 pd[0x18];\n+\tu8 reserved_at_a0[0x13];\n+\tu8 log_depth[0x5];\n+\tu8 log_hash_size[0x8];\n+\tu8 ste_format[0x8];\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_d0[0x10];\n+\tu8 match_definer_id[0x20];\n+\tu8 stc_id[0x20];\n+\tu8 ste_table_base_id[0x20];\n+\tu8 ste_table_offset[0x20];\n+\tu8 reserved_at_160[0x8];\n+\tu8 miss_flow_table_id[0x18];\n+\tu8 reserved_at_180[0x280];\n+};\n+\n+enum mlx5_ifc_stc_action_type {\n+\tMLX5_IFC_STC_ACTION_TYPE_NOP = 0x00,\n+\tMLX5_IFC_STC_ACTION_TYPE_COPY = 0x05,\n+\tMLX5_IFC_STC_ACTION_TYPE_SET = 0x06,\n+\tMLX5_IFC_STC_ACTION_TYPE_ADD = 0x07,\n+\tMLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS = 0x08,\n+\tMLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE = 0x09,\n+\tMLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT = 0x0b,\n+\tMLX5_IFC_STC_ACTION_TYPE_TAG = 0x0c,\n+\tMLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST = 0x0e,\n+\tMLX5_IFC_STC_ACTION_TYPE_ASO = 0x12,\n+\tMLX5_IFC_STC_ACTION_TYPE_COUNTER = 0x14,\n+\tMLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE = 0x80,\n+\tMLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR = 0x81,\n+\tMLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT = 0x82,\n+\tMLX5_IFC_STC_ACTION_TYPE_DROP = 0x83,\n+\tMLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84,\n+\tMLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85,\n+\tMLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86,\n+};\n+\n+struct mlx5_ifc_stc_ste_param_ste_table_bits {\n+\tu8 ste_obj_id[0x20];\n+\tu8 match_definer_id[0x20];\n+\tu8 reserved_at_40[0x3];\n+\tu8 log_hash_size[0x5];\n+\tu8 reserved_at_48[0x38];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_tir_bits {\n+\tu8 reserved_at_0[0x8];\n+\tu8 tirn[0x18];\n+\tu8 reserved_at_20[0x60];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_table_bits {\n+\tu8 reserved_at_0[0x8];\n+\tu8 table_id[0x18];\n+\tu8 reserved_at_20[0x60];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_flow_counter_bits {\n+\tu8 flow_counter_id[0x20];\n+};\n+\n+enum {\n+\tMLX5_ASO_CT_NUM_PER_OBJ = 1,\n+\tMLX5_ASO_METER_NUM_PER_OBJ = 2,\n+};\n+\n+struct mlx5_ifc_stc_ste_param_execute_aso_bits {\n+\tu8 aso_object_id[0x20];\n+\tu8 return_reg_id[0x4];\n+\tu8 aso_type[0x4];\n+\tu8 reserved_at_28[0x18];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_header_modify_list_bits {\n+\tu8 header_modify_pattern_id[0x20];\n+\tu8 header_modify_argument_id[0x20];\n+};\n+\n+enum mlx5_ifc_header_anchors {\n+\tMLX5_HEADER_ANCHOR_PACKET_START = 0x0,\n+\tMLX5_HEADER_ANCHOR_FIRST_VLAN_START = 0x2,\n+\tMLX5_HEADER_ANCHOR_IPV6_IPV4 = 0x07,\n+\tMLX5_HEADER_ANCHOR_INNER_MAC = 0x13,\n+\tMLX5_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19,\n+};\n+\n+struct mlx5_ifc_stc_ste_param_remove_bits {\n+\tu8 action_type[0x4];\n+\tu8 decap[0x1];\n+\tu8 reserved_at_5[0x5];\n+\tu8 remove_start_anchor[0x6];\n+\tu8 reserved_at_10[0x2];\n+\tu8 remove_end_anchor[0x6];\n+\tu8 reserved_at_18[0x8];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_remove_words_bits {\n+\tu8 action_type[0x4];\n+\tu8 reserved_at_4[0x6];\n+\tu8 remove_start_anchor[0x6];\n+\tu8 reserved_at_10[0x1];\n+\tu8 remove_offset[0x7];\n+\tu8 reserved_at_18[0x2];\n+\tu8 remove_size[0x6];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_insert_bits {\n+\tu8 action_type[0x4];\n+\tu8 encap[0x1];\n+\tu8 inline_data[0x1];\n+\tu8 reserved_at_6[0x4];\n+\tu8 insert_anchor[0x6];\n+\tu8 reserved_at_10[0x1];\n+\tu8 insert_offset[0x7];\n+\tu8 reserved_at_18[0x1];\n+\tu8 insert_size[0x7];\n+\tu8 insert_argument[0x20];\n+};\n+\n+struct mlx5_ifc_stc_ste_param_vport_bits {\n+\tu8 eswitch_owner_vhca_id[0x10];\n+\tu8 vport_number[0x10];\n+\tu8 eswitch_owner_vhca_id_valid[0x1];\n+\tu8 reserved_at_21[0x59];\n+};\n+\n+union mlx5_ifc_stc_param_bits {\n+\tstruct mlx5_ifc_stc_ste_param_ste_table_bits ste_table;\n+\tstruct mlx5_ifc_stc_ste_param_tir_bits tir;\n+\tstruct mlx5_ifc_stc_ste_param_table_bits table;\n+\tstruct mlx5_ifc_stc_ste_param_flow_counter_bits counter;\n+\tstruct mlx5_ifc_stc_ste_param_header_modify_list_bits modify_header;\n+\tstruct mlx5_ifc_stc_ste_param_execute_aso_bits aso;\n+\tstruct mlx5_ifc_stc_ste_param_remove_bits remove_header;\n+\tstruct mlx5_ifc_stc_ste_param_insert_bits insert_header;\n+\tstruct mlx5_ifc_set_action_in_bits add;\n+\tstruct mlx5_ifc_set_action_in_bits set;\n+\tstruct mlx5_ifc_copy_action_in_bits copy;\n+\tstruct mlx5_ifc_stc_ste_param_vport_bits vport;\n+\tu8 reserved_at_0[0x80];\n+};\n+\n+enum {\n+\tMLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC = 1 << 0,\n+};\n+\n+struct mlx5_ifc_stc_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x48];\n+\tu8 table_type[0x8];\n+\tu8 ste_action_offset[0x8];\n+\tu8 action_type[0x8];\n+\tu8 reserved_at_a0[0x60];\n+\tunion mlx5_ifc_stc_param_bits stc_param;\n+\tu8 reserved_at_180[0x280];\n+};\n+\n+struct mlx5_ifc_ste_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x48];\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_90[0x370];\n+};\n+\n+enum {\n+\tMLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,\n+};\n+\n+struct mlx5_ifc_definer_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x50];\n+\tu8 format_id[0x10];\n+\tu8 reserved_at_60[0x60];\n+\tu8 format_select_dw3[0x8];\n+\tu8 format_select_dw2[0x8];\n+\tu8 format_select_dw1[0x8];\n+\tu8 format_select_dw0[0x8];\n+\tu8 format_select_dw7[0x8];\n+\tu8 format_select_dw6[0x8];\n+\tu8 format_select_dw5[0x8];\n+\tu8 format_select_dw4[0x8];\n+\tu8 reserved_at_100[0x18];\n+\tu8 format_select_dw8[0x8];\n+\tu8 reserved_at_120[0x20];\n+\tu8 format_select_byte3[0x8];\n+\tu8 format_select_byte2[0x8];\n+\tu8 format_select_byte1[0x8];\n+\tu8 format_select_byte0[0x8];\n+\tu8 format_select_byte7[0x8];\n+\tu8 format_select_byte6[0x8];\n+\tu8 format_select_byte5[0x8];\n+\tu8 format_select_byte4[0x8];\n+\tu8 reserved_at_180[0x40];\n+\tu8 ctrl[0xa0];\n+\tu8 match_mask[0x160];\n+};\n+\n+struct mlx5_ifc_arg_bits {\n+\tu8 rsvd0[0x88];\n+\tu8 access_pd[0x18];\n+};\n+\n+struct mlx5_ifc_header_modify_pattern_in_bits {\n+\tu8 modify_field_select[0x40];\n+\n+\tu8 reserved_at_40[0x40];\n+\n+\tu8 pattern_length[0x8];\n+\tu8 reserved_at_88[0x18];\n+\n+\tu8 reserved_at_a0[0x60];\n+\n+\tu8 pattern_data[MAX_ACTIONS_DATA_IN_HEADER_MODIFY * 8];\n+};\n+\n struct mlx5_ifc_create_virtio_q_counters_in_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n@@ -3044,6 +3398,36 @@ struct mlx5_ifc_create_geneve_tlv_option_in_bits {\n \tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n };\n \n+struct mlx5_ifc_create_rtc_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_rtc_bits rtc;\n+};\n+\n+struct mlx5_ifc_create_stc_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_stc_bits stc;\n+};\n+\n+struct mlx5_ifc_create_ste_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_ste_bits ste;\n+};\n+\n+struct mlx5_ifc_create_definer_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_definer_bits definer;\n+};\n+\n+struct mlx5_ifc_create_arg_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_arg_bits arg;\n+};\n+\n+struct mlx5_ifc_create_header_modify_pattern_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_header_modify_pattern_in_bits pattern;\n+};\n+\n enum {\n \tMLX5_CRYPTO_KEY_SIZE_128b = 0x0,\n \tMLX5_CRYPTO_KEY_SIZE_256b = 0x1,\n@@ -4253,6 +4637,209 @@ struct mlx5_ifc_query_q_counter_in_bits {\n \tu8 counter_set_id[0x8];\n };\n \n+enum {\n+\tFS_FT_NIC_RX = 0x0,\n+\tFS_FT_NIC_TX = 0x1,\n+\tFS_FT_FDB = 0x4,\n+\tFS_FT_FDB_RX = 0xa,\n+\tFS_FT_FDB_TX = 0xb,\n+};\n+\n+struct mlx5_ifc_flow_table_context_bits {\n+\tu8 reformat_en[0x1];\n+\tu8 decap_en[0x1];\n+\tu8 sw_owner[0x1];\n+\tu8 termination_table[0x1];\n+\tu8 table_miss_action[0x4];\n+\tu8 level[0x8];\n+\tu8 rtc_valid[0x1];\n+\tu8 reserved_at_11[0x7];\n+\tu8 log_size[0x8];\n+\n+\tu8 reserved_at_20[0x8];\n+\tu8 table_miss_id[0x18];\n+\n+\tu8 reserved_at_40[0x8];\n+\tu8 lag_master_next_table_id[0x18];\n+\n+\tu8 reserved_at_60[0x60];\n+\n+\tu8 rtc_id_0[0x20];\n+\n+\tu8 rtc_id_1[0x20];\n+\n+\tu8 reserved_at_100[0x40];\n+};\n+\n+struct mlx5_ifc_create_flow_table_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\n+\tu8 other_vport[0x1];\n+\tu8 reserved_at_41[0xf];\n+\tu8 vport_number[0x10];\n+\n+\tu8 reserved_at_60[0x20];\n+\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_88[0x18];\n+\n+\tu8 reserved_at_a0[0x20];\n+\n+\tstruct mlx5_ifc_flow_table_context_bits flow_table_context;\n+};\n+\n+struct mlx5_ifc_create_flow_table_out_bits {\n+\tu8 status[0x8];\n+\tu8 icm_address_63_40[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 icm_address_39_32[0x8];\n+\tu8 table_id[0x18];\n+\tu8 icm_address_31_0[0x20];\n+};\n+\n+enum mlx5_flow_destination_type {\n+\tMLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,\n+};\n+\n+enum {\n+\tMLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,\n+};\n+\n+struct mlx5_ifc_set_fte_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_dest_format_bits {\n+\tu8 destination_type[0x8];\n+\tu8 destination_id[0x18];\n+\tu8 destination_eswitch_owner_vhca_id_valid[0x1];\n+\tu8 packet_reformat[0x1];\n+\tu8 reserved_at_22[0xe];\n+\tu8 destination_eswitch_owner_vhca_id[0x10];\n+};\n+\n+struct mlx5_ifc_flow_counter_list_bits {\n+\tu8 flow_counter_id[0x20];\n+\tu8 reserved_at_20[0x20];\n+};\n+\n+union mlx5_ifc_dest_format_flow_counter_list_auto_bits {\n+\tstruct mlx5_ifc_dest_format_bits dest_format;\n+\tstruct mlx5_ifc_flow_counter_list_bits flow_counter_list;\n+\tu8 reserved_at_0[0x40];\n+};\n+\n+struct mlx5_ifc_flow_context_bits {\n+\tu8 reserved_at_00[0x20];\n+\tu8 group_id[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 flow_tag[0x18];\n+\tu8 reserved_at_60[0x10];\n+\tu8 action[0x10];\n+\tu8 extended_destination[0x1];\n+\tu8 reserved_at_81[0x7];\n+\tu8 destination_list_size[0x18];\n+\tu8 reserved_at_a0[0x8];\n+\tu8 flow_counter_list_size[0x18];\n+\tu8 reserved_at_c0[0x1740];\n+\t/* Currently only one destnation */\n+\tunion mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[1];\n+};\n+\n+struct mlx5_ifc_set_fte_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 other_vport[0x1];\n+\tu8 reserved_at_41[0xf];\n+\tu8 vport_number[0x10];\n+\tu8 reserved_at_60[0x20];\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_88[0x18];\n+\tu8 reserved_at_a0[0x8];\n+\tu8 table_id[0x18];\n+\tu8 ignore_flow_level[0x1];\n+\tu8 reserved_at_c1[0x17];\n+\tu8 modify_enable_mask[0x8];\n+\tu8 reserved_at_e0[0x20];\n+\tu8 flow_index[0x20];\n+\tu8 reserved_at_120[0xe0];\n+\tstruct mlx5_ifc_flow_context_bits flow_context;\n+};\n+\n+struct mlx5_ifc_create_flow_group_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x20];\n+\tu8 other_vport[0x1];\n+\tu8 reserved_at_41[0xf];\n+\tu8 vport_number[0x10];\n+\tu8 reserved_at_60[0x20];\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_88[0x18];\n+\tu8 reserved_at_a0[0x8];\n+\tu8 table_id[0x18];\n+\tu8 reserved_at_c0[0x1f40];\n+};\n+\n+struct mlx5_ifc_create_flow_group_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 group_id[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+enum {\n+\tMLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION = 1 << 0,\n+\tMLX5_IFC_MODIFY_FLOW_TABLE_RTC_ID = 1 << 1,\n+};\n+\n+enum {\n+\tMLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_DEFAULT = 0,\n+\tMLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1,\n+};\n+\n+struct mlx5_ifc_modify_flow_table_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\n+\tu8 reserved_at_40[0x10];\n+\tu8 vport_number[0x10];\n+\n+\tu8 reserved_at_60[0x10];\n+\tu8 modify_field_select[0x10];\n+\n+\tu8 table_type[0x8];\n+\tu8 reserved_at_88[0x18];\n+\n+\tu8 reserved_at_a0[0x8];\n+\tu8 table_id[0x18];\n+\n+\tstruct mlx5_ifc_flow_table_context_bits flow_table_context;\n+};\n+\n+struct mlx5_ifc_modify_flow_table_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\n+\tu8 syndrome[0x20];\n+\n+\tu8 reserved_at_40[0x60];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nnew file mode 100644\nindex 0000000000..da8cc3d265\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -0,0 +1,948 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj)\n+{\n+\tint ret;\n+\n+\tret = mlx5_glue->devx_obj_destroy(devx_obj->obj);\n+\tsimple_free(devx_obj);\n+\n+\treturn ret;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_flow_table_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_ft_create_attr *ft_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *ft_ctx;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for flow table object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(create_flow_table_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_TABLE);\n+\tMLX5_SET(create_flow_table_in, in, table_type, ft_attr->type);\n+\n+\tft_ctx = MLX5_ADDR_OF(create_flow_table_in, in, flow_table_context);\n+\tMLX5_SET(flow_table_context, ft_ctx, level, ft_attr->level);\n+\tMLX5_SET(flow_table_context, ft_ctx, rtc_valid, ft_attr->rtc_valid);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create FT\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(create_flow_table_out, out, table_id);\n+\n+\treturn devx_obj;\n+}\n+\n+int\n+mlx5dr_cmd_flow_table_modify(struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t struct mlx5dr_cmd_ft_modify_attr *ft_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(modify_flow_table_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {0};\n+\tvoid *ft_ctx;\n+\tint ret;\n+\n+\tMLX5_SET(modify_flow_table_in, in, opcode, MLX5_CMD_OP_MODIFY_FLOW_TABLE);\n+\tMLX5_SET(modify_flow_table_in, in, table_type, ft_attr->type);\n+\tMLX5_SET(modify_flow_table_in, in, modify_field_select, ft_attr->modify_fs);\n+\tMLX5_SET(modify_flow_table_in, in, table_id, devx_obj->id);\n+\n+\tft_ctx = MLX5_ADDR_OF(modify_flow_table_in, in, flow_table_context);\n+\n+\tMLX5_SET(flow_table_context, ft_ctx, table_miss_action, ft_attr->table_miss_action);\n+\tMLX5_SET(flow_table_context, ft_ctx, table_miss_id, ft_attr->table_miss_id);\n+\tMLX5_SET(flow_table_context, ft_ctx, rtc_id_0, ft_attr->rtc_id_0);\n+\tMLX5_SET(flow_table_context, ft_ctx, rtc_id_1, ft_attr->rtc_id_1);\n+\n+\tret = mlx5_glue->devx_obj_modify(devx_obj->obj, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to modify FT\");\n+\t\trte_errno = errno;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static struct mlx5dr_devx_obj *\n+mlx5dr_cmd_flow_group_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_fg_attr *fg_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_flow_group_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for flow group object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(create_flow_group_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_GROUP);\n+\tMLX5_SET(create_flow_group_in, in, table_type, fg_attr->table_type);\n+\tMLX5_SET(create_flow_group_in, in, table_id, fg_attr->table_id);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create Flow group\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(create_flow_group_out, out, group_id);\n+\n+\treturn devx_obj;\n+}\n+\n+static struct mlx5dr_devx_obj *\n+mlx5dr_cmd_set_vport_fte(struct ibv_context *ctx,\n+\t\t\t uint32_t table_type,\n+\t\t\t uint32_t table_id,\n+\t\t\t uint32_t group_id,\n+\t\t\t uint32_t vport_id)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(set_fte_in) + MLX5_ST_SZ_DW(dest_format)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(set_fte_out)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *in_flow_context;\n+\tvoid *in_dests;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for fte object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(set_fte_in, in, opcode, MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY);\n+\tMLX5_SET(set_fte_in, in, table_type, table_type);\n+\tMLX5_SET(set_fte_in, in, table_id, table_id);\n+\n+\tin_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);\n+\tMLX5_SET(flow_context, in_flow_context, group_id, group_id);\n+\tMLX5_SET(flow_context, in_flow_context, destination_list_size, 1);\n+\tMLX5_SET(flow_context, in_flow_context, action, MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);\n+\n+\tin_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);\n+\tMLX5_SET(dest_format, in_dests, destination_type,\n+\t\t MLX5_FLOW_DESTINATION_TYPE_VPORT);\n+\tMLX5_SET(dest_format, in_dests, destination_id, vport_id);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create FTE\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\treturn devx_obj;\n+}\n+\n+void mlx5dr_cmd_miss_ft_destroy(struct mlx5dr_cmd_forward_tbl *tbl)\n+{\n+\tmlx5dr_cmd_destroy_obj(tbl->fte);\n+\tmlx5dr_cmd_destroy_obj(tbl->fg);\n+\tmlx5dr_cmd_destroy_obj(tbl->ft);\n+}\n+\n+struct mlx5dr_cmd_forward_tbl *\n+mlx5dr_cmd_miss_ft_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_ft_create_attr *ft_attr,\n+\t\t\t uint32_t vport)\n+{\n+\tstruct mlx5dr_cmd_fg_attr fg_attr = {0};\n+\tstruct mlx5dr_cmd_forward_tbl *tbl;\n+\n+\ttbl = simple_calloc(1, sizeof(*tbl));\n+\tif (!tbl) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for forward default\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\ttbl->ft = mlx5dr_cmd_flow_table_create(ctx, ft_attr);\n+\tif (!tbl->ft) {\n+\t\tDR_LOG(ERR, \"Failed to create FT for miss-table\");\n+\t\tgoto free_tbl;\n+\t}\n+\n+\tfg_attr.table_id = tbl->ft->id;\n+\tfg_attr.table_type = ft_attr->type;\n+\n+\ttbl->fg = mlx5dr_cmd_flow_group_create(ctx, &fg_attr);\n+\tif (!tbl->fg) {\n+\t\tDR_LOG(ERR, \"Failed to create FG for miss-table\");\n+\t\tgoto free_ft;\n+\t}\n+\n+\ttbl->fte = mlx5dr_cmd_set_vport_fte(ctx, ft_attr->type, tbl->ft->id, tbl->fg->id, vport);\n+\tif (!tbl->fte) {\n+\t\tDR_LOG(ERR, \"Failed to create FTE for miss-table\");\n+\t\tgoto free_fg;\n+\t}\n+\treturn tbl;\n+\n+free_fg:\n+\tmlx5dr_cmd_destroy_obj(tbl->fg);\n+free_ft:\n+\tmlx5dr_cmd_destroy_obj(tbl->ft);\n+free_tbl:\n+\tsimple_free(tbl);\n+\treturn NULL;\n+}\n+\n+void mlx5dr_cmd_set_attr_connect_miss_tbl(struct mlx5dr_context *ctx,\n+\t\t\t\t\t uint32_t fw_ft_type,\n+\t\t\t\t\t enum mlx5dr_table_type type,\n+\t\t\t\t\t struct mlx5dr_cmd_ft_modify_attr *ft_attr)\n+{\n+\tstruct mlx5dr_devx_obj *default_miss_tbl;\n+\n+\tif (type != MLX5DR_TABLE_TYPE_FDB)\n+\t\treturn;\n+\n+\tdefault_miss_tbl = ctx->common_res[type].default_miss->ft;\n+\tif (!default_miss_tbl) {\n+\t\tassert(false);\n+\t\treturn;\n+\t}\n+\tft_attr->modify_fs = MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION;\n+\tft_attr->type = fw_ft_type;\n+\tft_attr->table_miss_action = MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL;\n+\tft_attr->table_miss_id = default_miss_tbl->id;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_rtc_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_rtc_create_attr *rtc_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_rtc_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *attr;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for RTC object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tattr = MLX5_ADDR_OF(create_rtc_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC);\n+\n+\tattr = MLX5_ADDR_OF(create_rtc_in, in, rtc);\n+\tMLX5_SET(rtc, attr, ste_format, rtc_attr->is_jumbo ?\n+\t\tMLX5_IFC_RTC_STE_FORMAT_11DW :\n+\t\tMLX5_IFC_RTC_STE_FORMAT_8DW);\n+\tMLX5_SET(rtc, attr, pd, rtc_attr->pd);\n+\tMLX5_SET(rtc, attr, update_index_mode, rtc_attr->update_index_mode);\n+\tMLX5_SET(rtc, attr, log_depth, rtc_attr->log_depth);\n+\tMLX5_SET(rtc, attr, log_hash_size, rtc_attr->log_size);\n+\tMLX5_SET(rtc, attr, table_type, rtc_attr->table_type);\n+\tMLX5_SET(rtc, attr, match_definer_id, rtc_attr->definer_id);\n+\tMLX5_SET(rtc, attr, stc_id, rtc_attr->stc_base);\n+\tMLX5_SET(rtc, attr, ste_table_base_id, rtc_attr->ste_base);\n+\tMLX5_SET(rtc, attr, ste_table_offset, rtc_attr->ste_offset);\n+\tMLX5_SET(rtc, attr, miss_flow_table_id, rtc_attr->miss_ft_id);\n+\tMLX5_SET(rtc, attr, reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create RTC\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_stc_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_stc_create_attr *stc_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_stc_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *attr;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for STC object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tattr = MLX5_ADDR_OF(create_stc_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_STC);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, log_obj_range, stc_attr->log_obj_range);\n+\n+\tattr = MLX5_ADDR_OF(create_stc_in, in, stc);\n+\tMLX5_SET(stc, attr, table_type, stc_attr->table_type);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create STC\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+}\n+\n+static int\n+mlx5dr_cmd_stc_modify_set_stc_param(struct mlx5dr_cmd_stc_modify_attr *stc_attr,\n+\t\t\t\t void *stc_parm)\n+{\n+\tswitch (stc_attr->action_type) {\n+\tcase MLX5_IFC_STC_ACTION_TYPE_COUNTER:\n+\t\tMLX5_SET(stc_ste_param_flow_counter, stc_parm, flow_counter_id, stc_attr->id);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR:\n+\t\tMLX5_SET(stc_ste_param_tir, stc_parm, tirn, stc_attr->dest_tir_num);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT:\n+\t\tMLX5_SET(stc_ste_param_table, stc_parm, table_id, stc_attr->dest_table_id);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST:\n+\t\tMLX5_SET(stc_ste_param_header_modify_list, stc_parm,\n+\t\t\t header_modify_pattern_id, stc_attr->modify_header.pattern_id);\n+\t\tMLX5_SET(stc_ste_param_header_modify_list, stc_parm,\n+\t\t\t header_modify_argument_id, stc_attr->modify_header.arg_id);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE:\n+\t\tMLX5_SET(stc_ste_param_remove, stc_parm, action_type,\n+\t\t\t MLX5_MODIFICATION_TYPE_REMOVE);\n+\t\tMLX5_SET(stc_ste_param_remove, stc_parm, decap,\n+\t\t\t stc_attr->remove_header.decap);\n+\t\tMLX5_SET(stc_ste_param_remove, stc_parm, remove_start_anchor,\n+\t\t\t stc_attr->remove_header.start_anchor);\n+\t\tMLX5_SET(stc_ste_param_remove, stc_parm, remove_end_anchor,\n+\t\t\t stc_attr->remove_header.end_anchor);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT:\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, action_type,\n+\t\t\t MLX5_MODIFICATION_TYPE_INSERT);\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, encap,\n+\t\t\t stc_attr->insert_header.encap);\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, inline_data,\n+\t\t\t stc_attr->insert_header.is_inline);\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, insert_anchor,\n+\t\t\t stc_attr->insert_header.insert_anchor);\n+\t\t/* HW gets the next 2 sizes in words */\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, insert_size,\n+\t\t\t stc_attr->insert_header.header_size / 2);\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, insert_offset,\n+\t\t\t stc_attr->insert_header.insert_offset / 2);\n+\t\tMLX5_SET(stc_ste_param_insert, stc_parm, insert_argument,\n+\t\t\t stc_attr->insert_header.arg_id);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_COPY:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_SET:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_ADD:\n+\t\t*(__be64 *)stc_parm = stc_attr->modify_action.data;\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK:\n+\t\tMLX5_SET(stc_ste_param_vport, stc_parm, vport_number,\n+\t\t\t stc_attr->vport.vport_num);\n+\t\tMLX5_SET(stc_ste_param_vport, stc_parm, eswitch_owner_vhca_id,\n+\t\t\t stc_attr->vport.esw_owner_vhca_id);\n+\t\tMLX5_SET(stc_ste_param_vport, stc_parm, eswitch_owner_vhca_id_valid, 1);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_DROP:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_NOP:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_TAG:\n+\tcase MLX5_IFC_STC_ACTION_TYPE_ALLOW:\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_ASO:\n+\t\tMLX5_SET(stc_ste_param_execute_aso, stc_parm, aso_object_id,\n+\t\t\t stc_attr->aso.devx_obj_id);\n+\t\tMLX5_SET(stc_ste_param_execute_aso, stc_parm, return_reg_id,\n+\t\t\t stc_attr->aso.return_reg_id);\n+\t\tMLX5_SET(stc_ste_param_execute_aso, stc_parm, aso_type,\n+\t\t\t stc_attr->aso.aso_type);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE:\n+\t\tMLX5_SET(stc_ste_param_ste_table, stc_parm, ste_obj_id,\n+\t\t\t stc_attr->ste_table.ste_obj_id);\n+\t\tMLX5_SET(stc_ste_param_ste_table, stc_parm, match_definer_id,\n+\t\t\t stc_attr->ste_table.match_definer_id);\n+\t\tMLX5_SET(stc_ste_param_ste_table, stc_parm, log_hash_size,\n+\t\t\t stc_attr->ste_table.log_hash_size);\n+\t\tbreak;\n+\tcase MLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS:\n+\t\tMLX5_SET(stc_ste_param_remove_words, stc_parm, action_type,\n+\t\t\t MLX5_MODIFICATION_TYPE_REMOVE_WORDS);\n+\t\tMLX5_SET(stc_ste_param_remove_words, stc_parm, remove_start_anchor,\n+\t\t\t stc_attr->remove_words.start_anchor);\n+\t\tMLX5_SET(stc_ste_param_remove_words, stc_parm,\n+\t\t\t remove_size, stc_attr->remove_words.num_of_words);\n+\t\tbreak;\n+\tdefault:\n+\t\tDR_LOG(ERR, \"Not supported type %d\", stc_attr->action_type);\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+mlx5dr_cmd_stc_modify(struct mlx5dr_devx_obj *devx_obj,\n+\t\t struct mlx5dr_cmd_stc_modify_attr *stc_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_stc_in)] = {0};\n+\tvoid *stc_parm;\n+\tvoid *attr;\n+\tint ret;\n+\n+\tattr = MLX5_ADDR_OF(create_stc_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_STC);\n+\tMLX5_SET(general_obj_in_cmd_hdr, in, obj_id, devx_obj->id);\n+\tMLX5_SET(general_obj_in_cmd_hdr, in, obj_offset, stc_attr->stc_offset);\n+\n+\tattr = MLX5_ADDR_OF(create_stc_in, in, stc);\n+\tMLX5_SET(stc, attr, ste_action_offset, stc_attr->action_offset);\n+\tMLX5_SET(stc, attr, action_type, stc_attr->action_type);\n+\tMLX5_SET64(stc, attr, modify_field_select,\n+\t\t MLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC);\n+\n+\t/* Set destination TIRN, TAG, FT ID, STE ID */\n+\tstc_parm = MLX5_ADDR_OF(stc, attr, stc_param);\n+\tret = mlx5dr_cmd_stc_modify_set_stc_param(stc_attr, stc_parm);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5_glue->devx_obj_modify(devx_obj->obj, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to modify STC FW action_type %d\", stc_attr->action_type);\n+\t\trte_errno = errno;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_arg_create(struct ibv_context *ctx,\n+\t\t uint16_t log_obj_range,\n+\t\t uint32_t pd)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_arg_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *attr;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for ARG object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tattr = MLX5_ADDR_OF(create_arg_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_ARG);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, log_obj_range, log_obj_range);\n+\n+\tattr = MLX5_ADDR_OF(create_arg_in, in, arg);\n+\tMLX5_SET(arg, attr, access_pd, pd);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create ARG\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_header_modify_pattern_create(struct ibv_context *ctx,\n+\t\t\t\t\tuint32_t pattern_length,\n+\t\t\t\t\tuint8_t *actions)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_header_modify_pattern_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *pattern_data;\n+\tvoid *pattern;\n+\tvoid *attr;\n+\n+\tif (pattern_length > MAX_ACTIONS_DATA_IN_HEADER_MODIFY) {\n+\t\tDR_LOG(ERR, \"Pattern length %d exceeds limit %d\",\n+\t\t\tpattern_length, MAX_ACTIONS_DATA_IN_HEADER_MODIFY);\n+\t\trte_errno = EINVAL;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for header_modify_pattern object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tattr = MLX5_ADDR_OF(create_header_modify_pattern_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN);\n+\n+\tpattern = MLX5_ADDR_OF(create_header_modify_pattern_in, in, pattern);\n+\t/* Pattern_length is in ddwords */\n+\tMLX5_SET(header_modify_pattern_in, pattern, pattern_length, pattern_length / (2 * DW_SIZE));\n+\n+\tpattern_data = MLX5_ADDR_OF(header_modify_pattern_in, pattern, pattern_data);\n+\tmemcpy(pattern_data, actions, pattern_length);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create header_modify_pattern\");\n+\t\trte_errno = errno;\n+\t\tgoto free_obj;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+\n+free_obj:\n+\tsimple_free(devx_obj);\n+\treturn NULL;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_ste_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_ste_create_attr *ste_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_ste_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *attr;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for STE object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tattr = MLX5_ADDR_OF(create_ste_in, in, hdr);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_STE);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t attr, log_obj_range, ste_attr->log_obj_range);\n+\n+\tattr = MLX5_ADDR_OF(create_ste_in, in, ste);\n+\tMLX5_SET(ste, attr, table_type, ste_attr->table_type);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create STE\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_definer_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_definer_create_attr *def_attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_definer_in)] = {0};\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\tvoid *ptr;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for definer object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t in, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr,\n+\t\t in, obj_type, MLX5_GENERAL_OBJ_TYPE_DEFINER);\n+\n+\tptr = MLX5_ADDR_OF(create_definer_in, in, definer);\n+\tMLX5_SET(definer, ptr, format_id, MLX5_IFC_DEFINER_FORMAT_ID_SELECT);\n+\n+\tMLX5_SET(definer, ptr, format_select_dw0, def_attr->dw_selector[0]);\n+\tMLX5_SET(definer, ptr, format_select_dw1, def_attr->dw_selector[1]);\n+\tMLX5_SET(definer, ptr, format_select_dw2, def_attr->dw_selector[2]);\n+\tMLX5_SET(definer, ptr, format_select_dw3, def_attr->dw_selector[3]);\n+\tMLX5_SET(definer, ptr, format_select_dw4, def_attr->dw_selector[4]);\n+\tMLX5_SET(definer, ptr, format_select_dw5, def_attr->dw_selector[5]);\n+\tMLX5_SET(definer, ptr, format_select_dw6, def_attr->dw_selector[6]);\n+\tMLX5_SET(definer, ptr, format_select_dw7, def_attr->dw_selector[7]);\n+\tMLX5_SET(definer, ptr, format_select_dw8, def_attr->dw_selector[8]);\n+\n+\tMLX5_SET(definer, ptr, format_select_byte0, def_attr->byte_selector[0]);\n+\tMLX5_SET(definer, ptr, format_select_byte1, def_attr->byte_selector[1]);\n+\tMLX5_SET(definer, ptr, format_select_byte2, def_attr->byte_selector[2]);\n+\tMLX5_SET(definer, ptr, format_select_byte3, def_attr->byte_selector[3]);\n+\tMLX5_SET(definer, ptr, format_select_byte4, def_attr->byte_selector[4]);\n+\tMLX5_SET(definer, ptr, format_select_byte5, def_attr->byte_selector[5]);\n+\tMLX5_SET(definer, ptr, format_select_byte6, def_attr->byte_selector[6]);\n+\tMLX5_SET(definer, ptr, format_select_byte7, def_attr->byte_selector[7]);\n+\n+\tptr = MLX5_ADDR_OF(definer, ptr, match_mask);\n+\tmemcpy(ptr, def_attr->match_mask, MLX5_FLD_SZ_BYTES(definer, match_mask));\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create Definer\");\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\n+\treturn devx_obj;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_sq_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_sq_create_attr *attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};\n+\tvoid *sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);\n+\tvoid *wqc = MLX5_ADDR_OF(sqc, sqc, wq);\n+\tstruct mlx5dr_devx_obj *devx_obj;\n+\n+\tdevx_obj = simple_malloc(sizeof(*devx_obj));\n+\tif (!devx_obj) {\n+\t\tDR_LOG(ERR, \"Failed to create SQ\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tMLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);\n+\tMLX5_SET(sqc, sqc, cqn, attr->cqn);\n+\tMLX5_SET(sqc, sqc, flush_in_error_en, 1);\n+\tMLX5_SET(sqc, sqc, non_wire, 1);\n+\tMLX5_SET(wq, wqc, wq_type, MLX5_WQ_TYPE_CYCLIC);\n+\tMLX5_SET(wq, wqc, pd, attr->pdn);\n+\tMLX5_SET(wq, wqc, uar_page, attr->page_id);\n+\tMLX5_SET(wq, wqc, log_wq_stride, log2above(MLX5_SEND_WQE_BB));\n+\tMLX5_SET(wq, wqc, log_wq_sz, attr->log_wq_sz);\n+\tMLX5_SET(wq, wqc, dbr_umem_id, attr->dbr_id);\n+\tMLX5_SET(wq, wqc, wq_umem_id, attr->wq_id);\n+\n+\tdevx_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (!devx_obj->obj) {\n+\t\tsimple_free(devx_obj);\n+\t\trte_errno = errno;\n+\t\treturn NULL;\n+\t}\n+\n+\tdevx_obj->id = MLX5_GET(create_sq_out, out, sqn);\n+\n+\treturn devx_obj;\n+}\n+\n+int mlx5dr_cmd_sq_modify_rdy(struct mlx5dr_devx_obj *devx_obj)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};\n+\tvoid *sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);\n+\tint ret;\n+\n+\tMLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);\n+\tMLX5_SET(modify_sq_in, in, sqn, devx_obj->id);\n+\tMLX5_SET(modify_sq_in, in, sq_state, MLX5_SQC_STATE_RST);\n+\tMLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RDY);\n+\n+\tret = mlx5_glue->devx_obj_modify(devx_obj->obj, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to modify SQ\");\n+\t\trte_errno = errno;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int mlx5dr_cmd_query_caps(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_query_caps *caps)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};\n+\tconst struct flow_hw_port_info *port_info;\n+\tstruct ibv_device_attr_ex attr_ex;\n+\tint ret;\n+\n+\tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to query device caps\");\n+\t\trte_errno = errno;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tcaps->wqe_based_update =\n+\t\tMLX5_GET(query_hca_cap_out, out,\n+\t\t\t capability.cmd_hca_cap.wqe_based_flow_table_update_cap);\n+\n+\tcaps->eswitch_manager = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.cmd_hca_cap.eswitch_manager);\n+\n+\tcaps->flex_protocols = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\tcapability.cmd_hca_cap.flex_parser_protocols);\n+\n+\tcaps->log_header_modify_argument_granularity =\n+\t\tMLX5_GET(query_hca_cap_out, out,\n+\t\t\t capability.cmd_hca_cap.log_header_modify_argument_granularity);\n+\n+\tcaps->log_header_modify_argument_granularity -=\n+\t\t\tMLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t capability.cmd_hca_cap.\n+\t\t\t\t log_header_modify_argument_granularity_offset);\n+\n+\tcaps->log_header_modify_argument_max_alloc =\n+\t\tMLX5_GET(query_hca_cap_out, out,\n+\t\t\t capability.cmd_hca_cap.log_header_modify_argument_max_alloc);\n+\n+\tcaps->definer_format_sup =\n+\t\tMLX5_GET64(query_hca_cap_out, out,\n+\t\t\t capability.cmd_hca_cap.match_definer_format_supported);\n+\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to query device caps\");\n+\t\trte_errno = errno;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tcaps->full_dw_jumbo_support = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.cmd_hca_cap_2.\n+\t\t\t\t\t format_select_dw_8_6_ext);\n+\n+\tcaps->format_select_gtpu_dw_0 = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.cmd_hca_cap_2.\n+\t\t\t\t\t\t format_select_dw_gtpu_dw_0);\n+\n+\tcaps->format_select_gtpu_dw_1 = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.cmd_hca_cap_2.\n+\t\t\t\t\t\t format_select_dw_gtpu_dw_1);\n+\n+\tcaps->format_select_gtpu_dw_2 = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.cmd_hca_cap_2.\n+\t\t\t\t\t\t format_select_dw_gtpu_dw_2);\n+\n+\tcaps->format_select_gtpu_ext_dw_0 = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.cmd_hca_cap_2.\n+\t\t\t\t\t\t format_select_dw_gtpu_first_ext_dw_0);\n+\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to query flow table caps\");\n+\t\trte_errno = errno;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tcaps->nic_ft.max_level = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.flow_table_nic_cap.\n+\t\t\t\t\t flow_table_properties_nic_receive.max_ft_level);\n+\n+\tcaps->nic_ft.reparse = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\tcapability.flow_table_nic_cap.\n+\t\t\t\t\tflow_table_properties_nic_receive.reparse);\n+\n+\tif (caps->wqe_based_update) {\n+\t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t\t MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE |\n+\t\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\t\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Failed to query WQE based FT caps\");\n+\t\t\trte_errno = errno;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tcaps->rtc_reparse_mode = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t rtc_reparse_mode);\n+\n+\t\tcaps->ste_format = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t ste_format);\n+\n+\t\tcaps->rtc_index_mode = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\tcapability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\trtc_index_mode);\n+\n+\t\tcaps->rtc_log_depth_max = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t rtc_log_depth_max);\n+\n+\t\tcaps->ste_alloc_log_max = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t ste_alloc_log_max);\n+\n+\t\tcaps->ste_alloc_log_gran = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t ste_alloc_log_granularity);\n+\n+\t\tcaps->trivial_match_definer = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t trivial_match_definer);\n+\n+\t\tcaps->stc_alloc_log_max = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t stc_alloc_log_max);\n+\n+\t\tcaps->stc_alloc_log_gran = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.wqe_based_flow_table_cap.\n+\t\t\t\t\t\t stc_alloc_log_granularity);\n+\t}\n+\n+\tif (caps->eswitch_manager) {\n+\t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t\t MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |\n+\t\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\t\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Failed to query flow table esw caps\");\n+\t\t\trte_errno = errno;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tcaps->fdb_ft.max_level = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\t capability.flow_table_nic_cap.\n+\t\t\t\t\t\t flow_table_properties_nic_receive.max_ft_level);\n+\n+\t\tcaps->fdb_ft.reparse = MLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t\t\tcapability.flow_table_nic_cap.\n+\t\t\t\t\t\tflow_table_properties_nic_receive.reparse);\n+\n+\t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t\t MLX5_SET_HCA_CAP_OP_MOD_ESW | MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\t\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Query eswitch capabilities failed %d\\n\", ret);\n+\t\t\trte_errno = errno;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tif (MLX5_GET(query_hca_cap_out, out,\n+\t\t\t capability.esw_cap.esw_manager_vport_number_valid))\n+\t\t\tcaps->eswitch_manager_vport_number =\n+\t\t\tMLX5_GET(query_hca_cap_out, out,\n+\t\t\t\t capability.esw_cap.esw_manager_vport_number);\n+\t}\n+\n+\tret = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to query device attributes\");\n+\t\trte_errno = ret;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tstrlcpy(caps->fw_ver, attr_ex.orig_attr.fw_ver, sizeof(caps->fw_ver));\n+\n+\tport_info = flow_hw_get_wire_port(ctx);\n+\tif (port_info) {\n+\t\tcaps->wire_regc = port_info->regc_value;\n+\t\tcaps->wire_regc_mask = port_info->regc_mask;\n+\t} else {\n+\t\tDR_LOG(INFO, \"Failed to query wire port regc value\");\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int mlx5dr_cmd_query_ib_port(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_query_vport_caps *vport_caps,\n+\t\t\t uint32_t port_num)\n+{\n+\tstruct mlx5_port_info port_info = {0};\n+\tuint32_t flags;\n+\tint ret;\n+\n+\tflags = MLX5_PORT_QUERY_VPORT | MLX5_PORT_QUERY_ESW_OWNER_VHCA_ID;\n+\n+\tret = mlx5_glue->devx_port_query(ctx, port_num, &port_info);\n+\t/* Check if query succeed and vport is enabled */\n+\tif (ret || (port_info.query_flags & flags) != flags) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tvport_caps->vport_num = port_info.vport_id;\n+\tvport_caps->esw_owner_vhca_id = port_info.esw_owner_vhca_id;\n+\n+\tif (port_info.query_flags & MLX5_PORT_QUERY_REG_C0) {\n+\t\tvport_caps->metadata_c = port_info.vport_meta_tag;\n+\t\tvport_caps->metadata_c_mask = port_info.vport_meta_mask;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nnew file mode 100644\nindex 0000000000..2548b2b238\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -0,0 +1,230 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_CMD_H_\n+#define MLX5DR_CMD_H_\n+\n+struct mlx5dr_cmd_ft_create_attr {\n+\tuint8_t type;\n+\tuint8_t level;\n+\tbool rtc_valid;\n+};\n+\n+struct mlx5dr_cmd_ft_modify_attr {\n+\tuint8_t type;\n+\tuint32_t rtc_id_0;\n+\tuint32_t rtc_id_1;\n+\tuint32_t table_miss_id;\n+\tuint8_t table_miss_action;\n+\tuint64_t modify_fs;\n+};\n+\n+struct mlx5dr_cmd_fg_attr {\n+\tuint32_t\ttable_id;\n+\tuint32_t\ttable_type;\n+};\n+\n+struct mlx5dr_cmd_forward_tbl {\n+\tstruct mlx5dr_devx_obj\t*ft;\n+\tstruct mlx5dr_devx_obj\t*fg;\n+\tstruct mlx5dr_devx_obj\t*fte;\n+\tuint32_t refcount;\n+};\n+\n+struct mlx5dr_cmd_rtc_create_attr {\n+\tuint32_t pd;\n+\tuint32_t stc_base;\n+\tuint32_t ste_base;\n+\tuint32_t ste_offset;\n+\tuint32_t miss_ft_id;\n+\tuint8_t update_index_mode;\n+\tuint8_t log_depth;\n+\tuint8_t log_size;\n+\tuint8_t table_type;\n+\tuint8_t definer_id;\n+\tbool is_jumbo;\n+};\n+\n+struct mlx5dr_cmd_stc_create_attr {\n+\tuint8_t log_obj_range;\n+\tuint8_t table_type;\n+};\n+\n+struct mlx5dr_cmd_stc_modify_attr {\n+\tuint32_t stc_offset;\n+\tuint8_t action_offset;\n+\tenum mlx5_ifc_stc_action_type action_type;\n+\tunion {\n+\t\tuint32_t id; /* TIRN, TAG, FT ID, STE ID */\n+\t\tstruct {\n+\t\t\tuint8_t decap;\n+\t\t\tuint16_t start_anchor;\n+\t\t\tuint16_t end_anchor;\n+\t\t} remove_header;\n+\t\tstruct {\n+\t\t\tuint32_t arg_id;\n+\t\t\tuint32_t pattern_id;\n+\t\t} modify_header;\n+\t\tstruct {\n+\t\t\t__be64 data;\n+\t\t} modify_action;\n+\t\tstruct {\n+\t\t\tuint32_t arg_id;\n+\t\t\tuint32_t header_size;\n+\t\t\tuint8_t is_inline;\n+\t\t\tuint8_t encap;\n+\t\t\tuint16_t insert_anchor;\n+\t\t\tuint16_t insert_offset;\n+\t\t} insert_header;\n+\t\tstruct {\n+\t\t\tuint8_t aso_type;\n+\t\t\tuint32_t devx_obj_id;\n+\t\t\tuint8_t return_reg_id;\n+\t\t} aso;\n+\t\tstruct {\n+\t\t\tuint16_t vport_num;\n+\t\t\tuint16_t esw_owner_vhca_id;\n+\t\t} vport;\n+\t\tstruct {\n+\t\t\tstruct mlx5dr_pool_chunk ste;\n+\t\t\tstruct mlx5dr_pool *ste_pool;\n+\t\t\tuint32_t ste_obj_id; /* Internal */\n+\t\t\tuint32_t match_definer_id;\n+\t\t\tuint8_t log_hash_size;\n+\t\t} ste_table;\n+\t\tstruct {\n+\t\t\tuint16_t start_anchor;\n+\t\t\tuint16_t num_of_words;\n+\t\t} remove_words;\n+\n+\t\tuint32_t dest_table_id;\n+\t\tuint32_t dest_tir_num;\n+\t};\n+};\n+\n+struct mlx5dr_cmd_ste_create_attr {\n+\tuint8_t log_obj_range;\n+\tuint8_t table_type;\n+};\n+\n+struct mlx5dr_cmd_definer_create_attr {\n+\tuint8_t *dw_selector;\n+\tuint8_t *byte_selector;\n+\tuint8_t *match_mask;\n+};\n+\n+struct mlx5dr_cmd_sq_create_attr {\n+\tuint32_t cqn;\n+\tuint32_t pdn;\n+\tuint32_t page_id;\n+\tuint32_t dbr_id;\n+\tuint32_t wq_id;\n+\tuint32_t log_wq_sz;\n+};\n+\n+struct mlx5dr_cmd_query_ft_caps {\n+\tuint8_t max_level;\n+\tuint8_t reparse;\n+};\n+\n+struct mlx5dr_cmd_query_vport_caps {\n+\tuint16_t vport_num;\n+\tuint16_t esw_owner_vhca_id;\n+\tuint32_t metadata_c;\n+\tuint32_t metadata_c_mask;\n+};\n+\n+struct mlx5dr_cmd_query_caps {\n+\tuint32_t wire_regc;\n+\tuint32_t wire_regc_mask;\n+\tuint32_t flex_protocols;\n+\tuint8_t wqe_based_update;\n+\tuint8_t rtc_reparse_mode;\n+\tuint16_t ste_format;\n+\tuint8_t rtc_index_mode;\n+\tuint8_t ste_alloc_log_max;\n+\tuint8_t ste_alloc_log_gran;\n+\tuint8_t stc_alloc_log_max;\n+\tuint8_t stc_alloc_log_gran;\n+\tuint8_t rtc_log_depth_max;\n+\tuint8_t format_select_gtpu_dw_0;\n+\tuint8_t format_select_gtpu_dw_1;\n+\tuint8_t format_select_gtpu_dw_2;\n+\tuint8_t format_select_gtpu_ext_dw_0;\n+\tbool full_dw_jumbo_support;\n+\tstruct mlx5dr_cmd_query_ft_caps nic_ft;\n+\tstruct mlx5dr_cmd_query_ft_caps fdb_ft;\n+\tbool eswitch_manager;\n+\tuint32_t eswitch_manager_vport_number;\n+\tuint8_t log_header_modify_argument_granularity;\n+\tuint8_t log_header_modify_argument_max_alloc;\n+\tuint64_t definer_format_sup;\n+\tuint32_t trivial_match_definer;\n+\tchar fw_ver[64];\n+};\n+\n+int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_flow_table_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_ft_create_attr *ft_attr);\n+\n+int\n+mlx5dr_cmd_flow_table_modify(struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t struct mlx5dr_cmd_ft_modify_attr *ft_attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_rtc_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_rtc_create_attr *rtc_attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_stc_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_stc_create_attr *stc_attr);\n+\n+int\n+mlx5dr_cmd_stc_modify(struct mlx5dr_devx_obj *devx_obj,\n+\t\t struct mlx5dr_cmd_stc_modify_attr *stc_attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_ste_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_ste_create_attr *ste_attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_definer_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_definer_create_attr *def_attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_sq_create(struct ibv_context *ctx,\n+\t\t struct mlx5dr_cmd_sq_create_attr *attr);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_arg_create(struct ibv_context *ctx,\n+\t\t uint16_t log_obj_range,\n+\t\t uint32_t pd);\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_cmd_header_modify_pattern_create(struct ibv_context *ctx,\n+\t\t\t\t\tuint32_t pattern_length,\n+\t\t\t\t\tuint8_t *actions);\n+\n+int mlx5dr_cmd_sq_modify_rdy(struct mlx5dr_devx_obj *devx_obj);\n+\n+int mlx5dr_cmd_query_ib_port(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_query_vport_caps *vport_caps,\n+\t\t\t uint32_t port_num);\n+int mlx5dr_cmd_query_caps(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_query_caps *caps);\n+\n+void mlx5dr_cmd_miss_ft_destroy(struct mlx5dr_cmd_forward_tbl *tbl);\n+\n+struct mlx5dr_cmd_forward_tbl *\n+mlx5dr_cmd_miss_ft_create(struct ibv_context *ctx,\n+\t\t\t struct mlx5dr_cmd_ft_create_attr *ft_attr,\n+\t\t\t uint32_t vport);\n+\n+void mlx5dr_cmd_set_attr_connect_miss_tbl(struct mlx5dr_context *ctx,\n+\t\t\t\t\t uint32_t fw_ft_type,\n+\t\t\t\t\t enum mlx5dr_table_type type,\n+\t\t\t\t\t struct mlx5dr_cmd_ft_modify_attr *ft_attr);\n+#endif /* MLX5DR_CMD_H_ */\n", "prefixes": [ "v5", "08/18" ] }