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GET /api/patches/116602/?format=api
{ "id": 116602, "url": "https://patches.dpdk.org/api/patches/116602/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1663806460-45162-8-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1663806460-45162-8-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1663806460-45162-8-git-send-email-nicolas.chautru@intel.com", "date": "2022-09-22T00:27:33", "name": "[v4,07/14] baseband/acc: add queue configuration for ACC200", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3fe64588e6e16a791ca419be688325097b3f0147", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1663806460-45162-8-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 24763, "url": "https://patches.dpdk.org/api/series/24763/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24763", "date": "2022-09-22T00:27:27", "name": "[v4,01/14] baseband/acc100: remove unused registers", "version": 4, "mbox": "https://patches.dpdk.org/series/24763/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/116602/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/116602/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C3391A0540;\n\tThu, 22 Sep 2022 02:28:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A0E9542B7A;\n\tThu, 22 Sep 2022 02:28:19 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 868664067C\n for <dev@dpdk.org>; Thu, 22 Sep 2022 02:28:14 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2022 17:28:12 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by orsmga007.jf.intel.com with ESMTP; 21 Sep 2022 17:28:11 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1663806494; x=1695342494;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=q5iZWNHS6GCjd50p30LdUvBYvjDvDQtEV9vpWCGUGd0=;\n b=kl+SI1Z1Bp6POfmLrB0hhS+3ttItSpoAwtQa5NBDiVq+SY/bpnb9kMlZ\n 7P0LWoIWTcuYJ9gAewrClbIOO0jOpxZpUvCA1Oy46fIuiYZRm6VZUSD7Z\n E9XVwDzERnjAXd9oXd+yPW8oFvFrs13cvXKOz/7877iX2ICdn7XNNvcTp\n g2gMbPo3r4/lc24U0a2om8g2Cp4Bi5rJS4TjWAcaWAbue1vABGXgSdvQI\n lIzxIQuJgijCQalZcO8096N3CeCJ+vOWiQe14K/AQw63ucYdq16vWqI66\n mZfgk42JKMWj+wVy2iFldFWQzkdcNQtxjHg38NF/zosI6zWMifbdvrZAR A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10477\"; a=\"279883408\"", "E=Sophos;i=\"5.93,334,1654585200\"; d=\"scan'208\";a=\"279883408\"", "E=Sophos;i=\"5.93,334,1654585200\"; d=\"scan'208\";a=\"615010966\"" ], "X-ExtLoop1": "1", "From": "Nic Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tthomas@monjalon.net", "Cc": "maxime.coquelin@redhat.com, trix@redhat.com, mdr@ashroe.eu,\n bruce.richardson@intel.com, hemant.agrawal@nxp.com,\n david.marchand@redhat.com, stephen@networkplumber.org,\n hernan.vargas@intel.com, Nic Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v4 07/14] baseband/acc: add queue configuration for ACC200", "Date": "Wed, 21 Sep 2022 17:27:33 -0700", "Message-Id": "<1663806460-45162-8-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1663806460-45162-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1663806460-45162-1-git-send-email-nicolas.chautru@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding function to create and configure queues for the\ndevice.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/rte_acc200_pmd.c | 373 +++++++++++++++++++++++++++++++++-\n 1 file changed, 372 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c\nindex 43415eb..355cf8e 100644\n--- a/drivers/baseband/acc/rte_acc200_pmd.c\n+++ b/drivers/baseband/acc/rte_acc200_pmd.c\n@@ -220,16 +220,383 @@\n \t\t\tacc_conf->q_fft.aq_depth_log2);\n }\n \n+/* Allocate 64MB memory used for all software rings */\n+static int\n+acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n+{\n+\tuint32_t phys_low, phys_high, value;\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tconst struct acc200_registry_addr *reg_addr;\n+\n+\tif (d->pf_device && !d->acc_conf.pf_mode_en) {\n+\t\trte_bbdev_log(NOTICE,\n+\t\t\t\t\"%s has PF mode disabled. This PF can't be used.\",\n+\t\t\t\tdev->data->name);\n+\t\treturn -ENODEV;\n+\t}\n+\tif (!d->pf_device && d->acc_conf.pf_mode_en) {\n+\t\trte_bbdev_log(NOTICE,\n+\t\t\t\t\"%s has PF mode enabled. This VF can't be used.\",\n+\t\t\t\tdev->data->name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\talloc_sw_rings_min_mem(dev, d, num_queues, socket_id);\n+\n+\t/* If minimal memory space approach failed, then allocate\n+\t * the 2 * 64MB block for the sw rings\n+\t */\n+\tif (d->sw_rings == NULL)\n+\t\talloc_2x64mb_sw_rings_mem(dev, d, socket_id);\n+\n+\tif (d->sw_rings == NULL) {\n+\t\trte_bbdev_log(NOTICE,\n+\t\t\t\t\"Failure allocating sw_rings memory\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* Configure ACC200 with the base address for DMA descriptor rings\n+\t * Same descriptor rings used for UL and DL DMA Engines\n+\t * Note : Assuming only VF0 bundle is used for PF mode\n+\t */\n+\tphys_high = (uint32_t)(d->sw_rings_iova >> 32);\n+\tphys_low = (uint32_t)(d->sw_rings_iova & ~(ACC_SIZE_64MBYTE-1));\n+\n+\t/* Choose correct registry addresses for the device type */\n+\tif (d->pf_device)\n+\t\treg_addr = &pf_reg_addr;\n+\telse\n+\t\treg_addr = &vf_reg_addr;\n+\n+\t/* Read the populated cfg from ACC200 registers */\n+\tfetch_acc200_config(dev);\n+\n+\t/* Start Pmon */\n+\tfor (value = 0; value <= 2; value++) {\n+\t\tacc_reg_write(d, reg_addr->pmon_ctrl_a, value);\n+\t\tacc_reg_write(d, reg_addr->pmon_ctrl_b, value);\n+\t\tacc_reg_write(d, reg_addr->pmon_ctrl_c, value);\n+\t}\n+\n+\t/* Release AXI from PF */\n+\tif (d->pf_device)\n+\t\tacc_reg_write(d, HWPfDmaAxiControl, 1);\n+\n+\tacc_reg_write(d, reg_addr->dma_ring_ul5g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->dma_ring_ul5g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->dma_ring_dl5g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->dma_ring_dl5g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->dma_ring_ul4g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->dma_ring_ul4g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->dma_ring_dl4g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->dma_ring_dl4g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->dma_ring_fft_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->dma_ring_fft_lo, phys_low);\n+\t/*\n+\t * Configure Ring Size to the max queue ring size\n+\t * (used for wrapping purpose)\n+\t */\n+\tvalue = log2_basic(d->sw_ring_size / 64);\n+\tacc_reg_write(d, reg_addr->ring_size, value);\n+\n+\t/* Configure tail pointer for use when SDONE enabled */\n+\tif (d->tail_ptrs == NULL)\n+\t\td->tail_ptrs = rte_zmalloc_socket(\n+\t\t\t\tdev->device->driver->name,\n+\t\t\t\tACC200_NUM_QGRPS * ACC200_NUM_AQS * sizeof(uint32_t),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (d->tail_ptrs == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate tail ptr for %s:%u\",\n+\t\t\t\tdev->device->driver->name,\n+\t\t\t\tdev->data->dev_id);\n+\t\trte_free(d->sw_rings);\n+\t\treturn -ENOMEM;\n+\t}\n+\td->tail_ptr_iova = rte_malloc_virt2iova(d->tail_ptrs);\n+\n+\tphys_high = (uint32_t)(d->tail_ptr_iova >> 32);\n+\tphys_low = (uint32_t)(d->tail_ptr_iova);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_ul5g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_ul5g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_dl5g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_dl5g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_ul4g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_ul4g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_dl4g_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_dl4g_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_fft_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->tail_ptrs_fft_lo, phys_low);\n+\n+\tif (d->harq_layout == NULL)\n+\t\td->harq_layout = rte_zmalloc_socket(\"HARQ Layout\",\n+\t\t\t\tACC_HARQ_LAYOUT * sizeof(*d->harq_layout),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, dev->data->socket_id);\n+\tif (d->harq_layout == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate harq_layout for %s:%u\",\n+\t\t\t\tdev->device->driver->name,\n+\t\t\t\tdev->data->dev_id);\n+\t\trte_free(d->sw_rings);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Mark as configured properly */\n+\td->configured = true;\n+\n+\trte_bbdev_log_debug(\n+\t\t\t\"ACC200 (%s) configured sw_rings = %p, sw_rings_iova = %#\"\n+\t\t\tPRIx64, dev->data->name, d->sw_rings, d->sw_rings_iova);\n+\n+\treturn 0;\n+}\n+\n /* Free memory used for software rings */\n static int\n acc200_dev_close(struct rte_bbdev *dev)\n {\n-\tRTE_SET_USED(dev);\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tif (d->sw_rings_base != NULL) {\n+\t\trte_free(d->tail_ptrs);\n+\t\trte_free(d->sw_rings_base);\n+\t\trte_free(d->harq_layout);\n+\t\td->sw_rings_base = NULL;\n+\t\td->tail_ptrs = NULL;\n+\t\td->harq_layout = NULL;\n+\t}\n \t/* Ensure all in flight HW transactions are completed */\n \tusleep(ACC_LONG_WAIT);\n \treturn 0;\n }\n \n+/**\n+ * Report a ACC200 queue index which is free\n+ * Return 0 to 16k for a valid queue_idx or -1 when no queue is available\n+ * Note : Only supporting VF0 Bundle for PF mode\n+ */\n+static int\n+acc200_find_free_queue_idx(struct rte_bbdev *dev,\n+\t\tconst struct rte_bbdev_queue_conf *conf)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tint op_2_acc[6] = {0, UL_4G, DL_4G, UL_5G, DL_5G, FFT};\n+\tint acc = op_2_acc[conf->op_type];\n+\tstruct rte_acc_queue_topology *qtop = NULL;\n+\n+\tqtopFromAcc(&qtop, acc, &(d->acc_conf));\n+\tif (qtop == NULL)\n+\t\treturn -1;\n+\t/* Identify matching QGroup Index which are sorted in priority order */\n+\tuint16_t group_idx = qtop->first_qgroup_index;\n+\tgroup_idx += conf->priority;\n+\tif (group_idx >= ACC200_NUM_QGRPS ||\n+\t\t\tconf->priority >= qtop->num_qgroups) {\n+\t\trte_bbdev_log(INFO, \"Invalid Priority on %s, priority %u\",\n+\t\t\t\tdev->data->name, conf->priority);\n+\t\treturn -1;\n+\t}\n+\t/* Find a free AQ_idx */\n+\tuint64_t aq_idx;\n+\tfor (aq_idx = 0; aq_idx < qtop->num_aqs_per_groups; aq_idx++) {\n+\t\tif (((d->q_assigned_bit_map[group_idx] >> aq_idx) & 0x1) == 0) {\n+\t\t\t/* Mark the Queue as assigned */\n+\t\t\td->q_assigned_bit_map[group_idx] |= (1 << aq_idx);\n+\t\t\t/* Report the AQ Index */\n+\t\t\treturn (group_idx << ACC200_GRP_ID_SHIFT) + aq_idx;\n+\t\t}\n+\t}\n+\trte_bbdev_log(INFO, \"Failed to find free queue on %s, priority %u\",\n+\t\t\tdev->data->name, conf->priority);\n+\treturn -1;\n+}\n+\n+/* Setup ACC200 queue */\n+static int\n+acc200_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n+\t\tconst struct rte_bbdev_queue_conf *conf)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tstruct acc_queue *q;\n+\tint16_t q_idx;\n+\n+\tif (d == NULL) {\n+\t\trte_bbdev_log(ERR, \"Undefined device\");\n+\t\treturn -ENODEV;\n+\t}\n+\t/* Allocate the queue data structure. */\n+\tq = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),\n+\t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n+\tif (q == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate queue memory\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tq->d = d;\n+\tq->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));\n+\tq->ring_addr_iova = d->sw_rings_iova + (d->sw_ring_size * queue_id);\n+\n+\t/* Prepare the Ring with default descriptor format */\n+\tunion acc_dma_desc *desc = NULL;\n+\tunsigned int desc_idx, b_idx;\n+\tint fcw_len = (conf->op_type == RTE_BBDEV_OP_LDPC_ENC ?\n+\t\tACC_FCW_LE_BLEN : (conf->op_type == RTE_BBDEV_OP_TURBO_DEC ?\n+\t\tACC_FCW_TD_BLEN : (conf->op_type == RTE_BBDEV_OP_LDPC_DEC ?\n+\t\tACC_FCW_LD_BLEN : ACC_FCW_FFT_BLEN)));\n+\n+\tfor (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) {\n+\t\tdesc = q->ring_addr + desc_idx;\n+\t\tdesc->req.word0 = ACC_DMA_DESC_TYPE;\n+\t\tdesc->req.word1 = 0; /**< Timestamp */\n+\t\tdesc->req.word2 = 0;\n+\t\tdesc->req.word3 = 0;\n+\t\tuint64_t fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET;\n+\t\tdesc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;\n+\t\tdesc->req.data_ptrs[0].blen = fcw_len;\n+\t\tdesc->req.data_ptrs[0].blkid = ACC_DMA_BLKID_FCW;\n+\t\tdesc->req.data_ptrs[0].last = 0;\n+\t\tdesc->req.data_ptrs[0].dma_ext = 0;\n+\t\tfor (b_idx = 1; b_idx < ACC_DMA_MAX_NUM_POINTERS - 1;\n+\t\t\t\tb_idx++) {\n+\t\t\tdesc->req.data_ptrs[b_idx].blkid = ACC_DMA_BLKID_IN;\n+\t\t\tdesc->req.data_ptrs[b_idx].last = 1;\n+\t\t\tdesc->req.data_ptrs[b_idx].dma_ext = 0;\n+\t\t\tb_idx++;\n+\t\t\tdesc->req.data_ptrs[b_idx].blkid =\n+\t\t\t\t\tACC_DMA_BLKID_OUT_ENC;\n+\t\t\tdesc->req.data_ptrs[b_idx].last = 1;\n+\t\t\tdesc->req.data_ptrs[b_idx].dma_ext = 0;\n+\t\t}\n+\t\t/* Preset some fields of LDPC FCW */\n+\t\tdesc->req.fcw_ld.FCWversion = ACC_FCW_VER;\n+\t\tdesc->req.fcw_ld.gain_i = 1;\n+\t\tdesc->req.fcw_ld.gain_h = 1;\n+\t}\n+\n+\tq->lb_in = rte_zmalloc_socket(dev->device->driver->name,\n+\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n+\tif (q->lb_in == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate lb_in memory\");\n+\t\trte_free(q);\n+\t\treturn -ENOMEM;\n+\t}\n+\tq->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in);\n+\tq->lb_out = rte_zmalloc_socket(dev->device->driver->name,\n+\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n+\tif (q->lb_out == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate lb_out memory\");\n+\t\trte_free(q->lb_in);\n+\t\trte_free(q);\n+\t\treturn -ENOMEM;\n+\t}\n+\tq->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out);\n+\tq->companion_ring_addr = rte_zmalloc_socket(dev->device->driver->name,\n+\t\t\td->sw_ring_max_depth * sizeof(*q->companion_ring_addr),\n+\t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n+\tif (q->companion_ring_addr == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate companion_ring memory\");\n+\t\trte_free(q->lb_in);\n+\t\trte_free(q->lb_out);\n+\t\trte_free(q);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/*\n+\t * Software queue ring wraps synchronously with the HW when it reaches\n+\t * the boundary of the maximum allocated queue size, no matter what the\n+\t * sw queue size is. This wrapping is guarded by setting the wrap_mask\n+\t * to represent the maximum queue size as allocated at the time when\n+\t * the device has been setup (in configure()).\n+\t *\n+\t * The queue depth is set to the queue size value (conf->queue_size).\n+\t * This limits the occupancy of the queue at any point of time, so that\n+\t * the queue does not get swamped with enqueue requests.\n+\t */\n+\tq->sw_ring_depth = conf->queue_size;\n+\tq->sw_ring_wrap_mask = d->sw_ring_max_depth - 1;\n+\n+\tq->op_type = conf->op_type;\n+\n+\tq_idx = acc200_find_free_queue_idx(dev, conf);\n+\tif (q_idx == -1) {\n+\t\trte_free(q->companion_ring_addr);\n+\t\trte_free(q->lb_in);\n+\t\trte_free(q->lb_out);\n+\t\trte_free(q);\n+\t\treturn -1;\n+\t}\n+\n+\tq->qgrp_id = (q_idx >> ACC200_GRP_ID_SHIFT) & 0xF;\n+\tq->vf_id = (q_idx >> ACC200_VF_ID_SHIFT) & 0x3F;\n+\tq->aq_id = q_idx & 0xF;\n+\tq->aq_depth = 0;\n+\tif (conf->op_type == RTE_BBDEV_OP_TURBO_DEC)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_ul_4g.aq_depth_log2);\n+\telse if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_dl_4g.aq_depth_log2);\n+\telse if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_ul_5g.aq_depth_log2);\n+\telse if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2);\n+\telse if (conf->op_type == RTE_BBDEV_OP_FFT)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_fft.aq_depth_log2);\n+\n+\tq->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base,\n+\t\t\tqueue_offset(d->pf_device,\n+\t\t\t\t\tq->vf_id, q->qgrp_id, q->aq_id));\n+\n+\trte_bbdev_log_debug(\n+\t\t\t\"Setup dev%u q%u: qgrp_id=%u, vf_id=%u, aq_id=%u, aq_depth=%u, mmio_reg_enqueue=%p base %p\\n\",\n+\t\t\tdev->data->dev_id, queue_id, q->qgrp_id, q->vf_id,\n+\t\t\tq->aq_id, q->aq_depth, q->mmio_reg_enqueue,\n+\t\t\td->mmio_base);\n+\n+\tdev->data->queues[queue_id].queue_private = q;\n+\treturn 0;\n+}\n+\n+\n+static int\n+acc_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)\n+{\n+\tstruct acc_queue *q;\n+\tq = dev->data->queues[queue_id].queue_private;\n+\trte_bbdev_log(INFO, \"Queue Stop %d H/T/D %d %d %x OpType %d\",\n+\t\t\tqueue_id, q->sw_ring_head, q->sw_ring_tail,\n+\t\t\tq->sw_ring_depth, q->op_type);\n+\t/* ignore all operations in flight and clear counters */\n+\tq->sw_ring_tail = q->sw_ring_head;\n+\tq->aq_enqueued = 0;\n+\tq->aq_dequeued = 0;\n+\tdev->data->queues[queue_id].queue_stats.enqueued_count = 0;\n+\tdev->data->queues[queue_id].queue_stats.dequeued_count = 0;\n+\tdev->data->queues[queue_id].queue_stats.enqueue_err_count = 0;\n+\tdev->data->queues[queue_id].queue_stats.dequeue_err_count = 0;\n+\tdev->data->queues[queue_id].queue_stats.enqueue_warn_count = 0;\n+\tdev->data->queues[queue_id].queue_stats.dequeue_warn_count = 0;\n+\treturn 0;\n+}\n+\n+/* Release ACC200 queue */\n+static int\n+acc200_queue_release(struct rte_bbdev *dev, uint16_t q_id)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tstruct acc_queue *q = dev->data->queues[q_id].queue_private;\n+\n+\tif (q != NULL) {\n+\t\t/* Mark the Queue as un-assigned */\n+\t\td->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF -\n+\t\t\t\t(uint64_t) (1 << q->aq_id));\n+\t\trte_free(q->companion_ring_addr);\n+\t\trte_free(q->lb_in);\n+\t\trte_free(q->lb_out);\n+\t\trte_free(q);\n+\t\tdev->data->queues[q_id].queue_private = NULL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Get ACC200 device info */\n static void\n acc200_dev_info_get(struct rte_bbdev *dev,\n@@ -279,8 +646,12 @@\n }\n \n static const struct rte_bbdev_ops acc200_bbdev_ops = {\n+\t.setup_queues = acc200_setup_queues,\n \t.close = acc200_dev_close,\n \t.info_get = acc200_dev_info_get,\n+\t.queue_setup = acc200_queue_setup,\n+\t.queue_release = acc200_queue_release,\n+\t.queue_stop = acc_queue_stop,\n };\n \n /* ACC200 PCI PF address map */\n", "prefixes": [ "v4", "07/14" ] }