Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/115566/?format=api
{ "id": 115566, "url": "https://patches.dpdk.org/api/patches/115566/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/BL3PR11MB64355C235C730E6B6E2C5AABC6759@BL3PR11MB6435.namprd11.prod.outlook.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<BL3PR11MB64355C235C730E6B6E2C5AABC6759@BL3PR11MB6435.namprd11.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/BL3PR11MB64355C235C730E6B6E2C5AABC6759@BL3PR11MB6435.namprd11.prod.outlook.com", "date": "2022-08-26T14:37:16", "name": "[1/2] net/iavf: enable TSO offloading for tunnel cases", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3dff80d45cacc950b748d500367cb07c4ca3a1e8", "submitter": { "id": 2548, "url": "https://patches.dpdk.org/api/people/2548/?format=api", "name": "Buckley, Daniel M", "email": "daniel.m.buckley@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/BL3PR11MB64355C235C730E6B6E2C5AABC6759@BL3PR11MB6435.namprd11.prod.outlook.com/mbox/", "series": [ { "id": 24436, "url": "https://patches.dpdk.org/api/series/24436/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24436", "date": "2022-08-26T14:37:16", "name": "[1/2] net/iavf: enable TSO offloading for tunnel cases", "version": 1, "mbox": "https://patches.dpdk.org/series/24436/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/115566/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/115566/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBB97A0542;\n\tMon, 29 Aug 2022 09:02:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2815E4281B;\n\tMon, 29 Aug 2022 09:02:03 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 27AFC40143\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;\n dkim=pass header.d=intel.com; arc=none", "From": "\"Buckley, Daniel M\" <daniel.m.buckley@intel.com>", "To": "\"Jiang, YuX\" <yux.jiang@intel.com>, \"dev@dpdk.org\" <dev@dpdk.org>", "Subject": "[PATCH 1/2] net/iavf: enable TSO offloading for tunnel cases", "Thread-Topic": "[PATCH 1/2] net/iavf: enable TSO offloading for tunnel cases", "Thread-Index": "AQHYuViZ4EurakFSWUW1jKeNObjH5Q==", "Date": "Fri, 26 Aug 2022 14:37:16 +0000", "Message-ID": "\n <BL3PR11MB64355C235C730E6B6E2C5AABC6759@BL3PR11MB6435.namprd11.prod.outlook.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "msip_labels": "", "authentication-results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=intel.com;", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "5ff34425-7e23-48e3-a8ce-08da8770793c", "x-ms-traffictypediagnostic": "BN9PR11MB5433:EE_", "x-ms-exchange-senderadcheck": "1", "x-ms-exchange-antispam-relay": "0", "x-microsoft-antispam": "BCL:0;", "x-microsoft-antispam-message-info": "\n zD6b6wQHIEFQEhcDvbGSewTYMcSv5CVEAurG3JA5EolackNMiiEjE2q7MTMyapU1pEeXczfq4qIZOhe6XOMv4WbXJmYCKnADoPBeeNe/ug6CceZUrKZg8IXsv+7Y9cZ4ycKNQZYMsR8F8rJ4fzAOxd2oBZG33gYlI2rJVnpw1Yt+X5sZ7mETc5jC+lxZ35bdcXAR1bOM/1zrOPLv37YCTpXIg/BCxru76f5l8P9moVAGglueCRCaiy3wjyfKwTMtVr0efsB/n5SUU0+muMJzowudJ6bFYgECgDWBtpyAFTCnnxRCw0ACiNRB/P/4aulrXI8kqKS0jhhEogLJecEesry/BeAldoPW/wJ+mplUIbqq/+1Lv+qS7IF2r5fnLbp/mvODocqWKgbVqn61ceDkddmtWNyjd0Bvnc9Q0yeM3quRv1tbTHPOcve8c5QpeFb05BlaWQ0B+LWwOw1K1mS56R2dESPog8lYzyI68DUILUer+UMJLICEh+moBavp4n7eLxJa4psGDO/Z5C97j2p75GAvJ7EH5TyeGu6fMZrBVAataZ636MIikOsxmd8ysQDDZKyUItNt8UvAcPULo/Gs9wWXNJMJZW/d0VI3zxNvpiXGbFYOCfg9CoUVkg2/0z7AC0JaAPu6Cd56eRpwUtEGSvjU05k9MahYJW7W9MYAhaym45c7s7N7nJYpJIZC1LoXusJNUGA2DWGWYG1rQo0WoJb56qTr0Kap1tz2wE/CUro+HxjtbHvtSlFMnFthq/JrZn1zCScvrGpHV/RT2QAwx6XcRPOGgf7Tupb4zYgbgyWMD6jBr07A+QkRRQKhbRco3C7+XWTPhdVJnCJmyEBRKQ==", "x-forefront-antispam-report": "CIP:255.255.255.255; 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charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: \"Zhang, Peng1X\" <peng1x.zhang@intel.com>\nX-Patchwork-Id: 114858\nX-Patchwork-Delegate: qi.z.zhang@intel.com\nReturn-Path: <dev-bounces@dpdk.org>\nX-Original-To: patchwork@inbox.dpdk.org\nDelivered-To: patchwork@inbox.dpdk.org\nReceived: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n by inbox.dpdk.org (Postfix) with ESMTP id F30E1A0543;\n Fri, 12 Aug 2022 11:02:17 +0200 (CEST)\nReceived: from [217.70.189.124] (localhost [127.0.0.1])\n by mails.dpdk.org (Postfix) with ESMTP id A76A040A7D;\n Fri, 12 Aug 2022 11:02:17 +0200 (CEST)\nReceived: from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id AA3CB406A2\n for <dev@dpdk.org>; Fri, 12 Aug 2022 11:02:15 +0200 (CEST)\nDKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660294935; x=1691830935;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=QjzGaVZvnEkF2FllVFU+xR8Y5DYCqb7NHx81eAGH2xU=;\n b=nvX/giSyIEaEGzx/ohuqZY1N0eibgtx/4jxW1rUSWVasoU/e7fGz2iw2\n KJwvpm8fGWrGF4p8joSgBP7UM++xo/D/ogAsc9W2HLRYgbFd2ckvvQxsq\n gnD1LsI3zO5+J5AKJTzu5Kohlcwmkb3kurwZI56MHThZIVnFFYD9RTQ+c\n mUTgBaiWvKNGAvnM4BEj2OXxHPwgy0TadKLMKX9fssQUQZ/95V1wAXCyS\n kPwqzX5wNQeb4nEHGrw6H3jc5my/E5bOwga+A3K/cGd1Kv2MvZqL1u2l4\n BfrZGZWkbejkuM0i8WfIPiMFXC/7GdTuBwVf/oe7S1hh0qSFarxYo0Ll6 g==;\nX-IronPort-AV: E=McAfee;i=\"6400,9594,10436\"; a=\"289127450\"\nX-IronPort-AV: E=Sophos;i=\"5.93,231,1654585200\"; d=\"scan'208\";a=\"289127450\"\nReceived: from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Aug 2022 02:02:14 -0700\nX-IronPort-AV: E=Sophos;i=\"5.93,231,1654585200\"; d=\"scan'208\";a=\"665750825\"\nReceived: from unknown (HELO localhost.localdomain) ([10.239.252.253])\n by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Aug 2022 02:02:13 -0700\nFrom: peng1x.zhang@intel.com\nTo: dev@dpdk.org\nCc: beilei.xing@intel.com, jingjing.wu@intel.com,\n Peng Zhang <peng1x.zhang@intel.com>\nSubject: [PATCH 1/2] net/iavf: enable TSO offloading for tunnel cases\nDate: Sat, 13 Aug 2022 00:52:22 +0800\nMessage-Id: <20220812165223.470777-1-peng1x.zhang@intel.com>\nX-Mailer: git-send-email 2.25.1\nMIME-Version: 1.0\nX-BeenThere: dev@dpdk.org\nX-Mailman-Version: 2.1.29\nPrecedence: list\nList-Id: DPDK patches and discussions <dev.dpdk.org>\nList-Unsubscribe: <https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>\nList-Archive: <http://mails.dpdk.org/archives/dev/>\nList-Post: <mailto:dev@dpdk.org>\nList-Help: <mailto:dev-request@dpdk.org?subject=help>\nList-Subscribe: <https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>\nErrors-To: dev-bounces@dpdk.org\n\nFrom: Peng Zhang <peng1x.zhang@intel.com>\n\nHardware limits that max buffer size per Tx descriptor should be (16K-1)B.\nSo when TSO enabled under unencrypt scenario, the mbuf data size may exceed\nthe limit and cause malicious behavior to the NIC.\n\nThis patch supports Tx descriptors for this kind of large buffer.\n\nSigned-off-by: Peng Zhang <peng1x.zhang@intel.com>\n---\nTested-by: Daniel M Buckley <daniel.m.buckley@intel.com>\n\n drivers/net/iavf/iavf_rxtx.c | 66 ++++++++++++++++++++++++++++++++----\n 1 file changed, 60 insertions(+), 6 deletions(-)\n\n\n--------------------------------------------------------------\nIntel Research and Development Ireland Limited\nRegistered in Ireland\nRegistered Office: Collinstown Industrial Park, Leixlip, County Kildare\nRegistered Number: 308263\n\n\nThis e-mail and any attachments may contain confidential material for the sole\nuse of the intended recipient(s). Any review or distribution by others is\nstrictly prohibited. If you are not the intended recipient, please contact the\nsender and delete all copies.", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\r\nindex dfd021889e..adec58e90a 100644\r\n--- a/drivers/net/iavf/iavf_rxtx.c\r\n+++ b/drivers/net/iavf/iavf_rxtx.c\r\n@@ -2642,6 +2642,47 @@ iavf_ipsec_crypto_get_pkt_metadata(const struct iavf_tx_queue *txq,\r\n return NULL;\r\n }\r\n\r\n+/* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */\r\n+#define IAVF_MAX_DATA_PER_TXD \\\r\n+ (IAVF_TXD_QW1_TX_BUF_SZ_MASK >> IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)\r\n+\r\n+static inline void\r\n+iavf_fill_unencrypt_desc(volatile struct iavf_tx_desc *txd, struct rte_mbuf *m,\r\n+ volatile uint64_t desc_template, struct iavf_tx_entry *txe,\r\n+ volatile struct iavf_tx_desc *txr, struct iavf_tx_entry *txe_ring,\r\n+ int desc_idx_last)\r\n+{\r\n+ /* Setup TX Descriptor */\r\n+ int desc_idx;\r\n+ uint16_t slen = m->data_len;\r\n+ uint64_t buf_dma_addr = rte_mbuf_data_iova(m);\r\n+ struct iavf_tx_entry *txn = &txe_ring[txe->next_id];\r\n+\r\n+ while ((m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&\r\n+ unlikely(slen > IAVF_MAX_DATA_PER_TXD)) {\r\n+ txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\r\n+\r\n+ txd->cmd_type_offset_bsz =\r\n+ rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |\r\n+ (uint64_t)IAVF_MAX_DATA_PER_TXD <<\r\n+ IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) | desc_template;\r\n+\r\n+ buf_dma_addr += IAVF_MAX_DATA_PER_TXD;\r\n+ slen -= IAVF_MAX_DATA_PER_TXD;\r\n+\r\n+ txe->last_id = desc_idx_last;\r\n+ desc_idx = txe->next_id;\r\n+ txe = txn;\r\n+ txd = &txr[desc_idx];\r\n+ txn = &txe_ring[txe->next_id];\r\n+ }\r\n+\r\n+ txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\r\n+ txd->cmd_type_offset_bsz =\r\n+ rte_cpu_to_le_64((uint64_t)slen << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT) |\r\n+ desc_template;\r\n+}\r\n+\r\n /* TX function */\r\n uint16_t\r\n iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\r\n@@ -2650,6 +2691,7 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\r\n volatile struct iavf_tx_desc *txr = txq->tx_ring;\r\n struct iavf_tx_entry *txe_ring = txq->sw_ring;\r\n struct iavf_tx_entry *txe, *txn;\r\n+ volatile struct iavf_tx_desc *txd;\r\n struct rte_mbuf *mb, *mb_seg;\r\n uint16_t desc_idx, desc_idx_last;\r\n uint16_t idx;\r\n@@ -2781,6 +2823,7 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\r\n ddesc = (volatile struct iavf_tx_desc *)\r\n &txr[desc_idx];\r\n\r\n+ txd = &txr[desc_idx];\r\n txn = &txe_ring[txe->next_id];\r\n RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);\r\n\r\n@@ -2788,10 +2831,16 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\r\n rte_pktmbuf_free_seg(txe->mbuf);\r\n\r\n txe->mbuf = mb_seg;\r\n- iavf_fill_data_desc(ddesc, mb_seg,\r\n- ddesc_template, tlen, ipseclen);\r\n\r\n- IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);\r\n+ if (nb_desc_ipsec) {\r\n+ iavf_fill_data_desc(ddesc, mb_seg,\r\n+ ddesc_template, tlen, ipseclen);\r\n+ IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx);\r\n+ } else {\r\n+ iavf_fill_unencrypt_desc(txd, mb_seg,\r\n+ ddesc_template, txe, txr, txe_ring, desc_idx_last);\r\n+ IAVF_DUMP_TX_DESC(txq, txd, desc_idx);\r\n+ }\r\n\r\n txe->last_id = desc_idx_last;\r\n desc_idx = txe->next_id;\r\n@@ -2816,10 +2865,15 @@ iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\r\n txq->nb_used = 0;\r\n }\r\n\r\n- ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<\r\n+ if (nb_desc_ipsec) {\r\n+ ddesc->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<\r\n IAVF_TXD_DATA_QW1_CMD_SHIFT);\r\n-\r\n- IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);\r\n+ IAVF_DUMP_TX_DESC(txq, ddesc, desc_idx - 1);\r\n+ } else {\r\n+ txd->cmd_type_offset_bsz |= rte_cpu_to_le_64(ddesc_cmd <<\r\n+ IAVF_TXD_DATA_QW1_CMD_SHIFT);\r\n+ IAVF_DUMP_TX_DESC(txq, txd, desc_idx - 1);\r\n+ }\r\n }\r\n\r\n end_of_tx:\r\n", "prefixes": [ "1/2" ] }