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GET /api/patches/114621/?format=api
{ "id": 114621, "url": "https://patches.dpdk.org/api/patches/114621/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220804134430.6192-6-adwivedi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220804134430.6192-6-adwivedi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220804134430.6192-6-adwivedi@marvell.com", "date": "2022-08-04T13:44:29", "name": "[5/6] ethdev: add trace points for driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e30e9a5180a667aecc1fe90966c345ae07555457", "submitter": { "id": 1561, "url": "https://patches.dpdk.org/api/people/1561/?format=api", "name": "Ankur Dwivedi", "email": "adwivedi@marvell.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220804134430.6192-6-adwivedi@marvell.com/mbox/", "series": [ { "id": 24204, "url": "https://patches.dpdk.org/api/series/24204/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24204", "date": "2022-08-04T13:44:24", "name": "add trace points in ethdev library", "version": 1, "mbox": "https://patches.dpdk.org/series/24204/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/114621/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/114621/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D6A67A00C4;\n\tThu, 4 Aug 2022 15:50:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C3A3642BE0;\n\tThu, 4 Aug 2022 15:50:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CF87042BD9\n for <dev@dpdk.org>; Thu, 4 Aug 2022 15:50:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 274CHYfI020978;\n Thu, 4 Aug 2022 06:47:36 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hqgf1xr7k-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 04 Aug 2022 06:47:36 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 4 Aug 2022 06:47:34 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 4 Aug 2022 06:47:34 -0700", "from hyd1349.t110.caveonetworks.com.com (unknown [10.29.45.13])\n by maili.marvell.com (Postfix) with ESMTP id 791043F705C;\n Thu, 4 Aug 2022 06:47:13 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=W0xEx8RZo+rU+q0PKcBQ061/4mG9OzfImRa64uyA1n4=;\n b=AzosckasoxGLPeu0WUuU1vofj63QYw/lDenHD8fyH5qhcewKmJurKY/a6oxiGpxzIj3V\n 4xT7XrYcgozq2f0KRpsiWPO6c4+4hZkPa2OQMhsPt2/0eP5fvYYNE3/xoMMZ82tCeYek\n e1lM725OT+okqrI14H4thvPr46gc1wLHjITbSJOYgznNas23l+e1j7uDNyN4ZSIvgFXj\n GwNZRCO/Yy5beDwdGhmtksB/V4yxDQMKcN2rp0oftpx9UERnUjNKYf+Rj2AlYyINJYsU\n U+j0yaKEvE2sUPK2Ek0E7KZqmIH2b74z6JheyiKbEop4ep91m+D+RraUmb47Udgwr4lW YQ==", "From": "Ankur Dwivedi <adwivedi@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <mdr@ashroe.eu>, <orika@nvidia.com>,\n <ferruh.yigit@xilinx.com>, <chas3@att.com>, <humin29@huawei.com>,\n <linville@tuxdriver.com>, <ciara.loftus@intel.com>,\n <qi.z.zhang@intel.com>, <mw@semihalf.com>, <mk@semihalf.com>,\n <shaibran@amazon.com>, <evgenys@amazon.com>, <igorch@amazon.com>,\n <chandu@amd.com>, <irusskikh@marvell.com>,\n <shepard.siegel@atomicrules.com>, <ed.czeck@atomicrules.com>,\n <john.miller@atomicrules.com>, <ajit.khaparde@broadcom.com>,\n <somnath.kotur@broadcom.com>, <jerinj@marvell.com>,\n <mczekaj@marvell.com>, <sthotton@marvell.com>,\n <srinivasan@marvell.com>, <hkalra@marvell.com>,\n <rahul.lakkireddy@chelsio.com>, <johndale@cisco.com>,\n <hyonkim@cisco.com>, <liudongdong3@huawei.com>,\n <yisen.zhuang@huawei.com>, <xuanziyang2@huawei.com>,\n <cloud.wangxiaoyun@huawei.com>, <zhouguoyang@huawei.com>,\n <simei.su@intel.com>, <wenjun1.wu@intel.com>, <qiming.yang@intel.com>,\n <Yuying.Zhang@intel.com>, <beilei.xing@intel.com>,\n <xiao.w.wang@intel.com>, <jingjing.wu@intel.com>,\n <junfeng.guo@intel.com>, <rosen.xu@intel.com>,\n <ndabilpuram@marvell.com>, <kirankumark@marvell.com>,\n <skori@marvell.com>, <skoteshwar@marvell.com>, <lironh@marvell.com>,\n <zr@semihalf.com>, <radhac@marvell.com>, <vburru@marvell.com>,\n <sedara@marvell.com>, <matan@nvidia.com>, <viacheslavo@nvidia.com>,\n <sthemmin@microsoft.com>, <longli@microsoft.com>, <spinler@cesnet.cz>,\n <chaoyong.he@corigine.com>, <niklas.soderlund@corigine.com>,\n <hemant.agrawal@nxp.com>, <sachin.saxena@oss.nxp.com>,\n <g.singh@nxp.com>, <apeksha.gupta@nxp.com>, <sachin.saxena@nxp.com>,\n <aboyer@pensando.io>, <rmody@marvell.com>, <shshaikh@marvell.com>,\n <dsinghrawat@marvell.com>, <andrew.rybchenko@oktetlabs.ru>,\n <jiawenwu@trustnetic.com>, <jianwang@trustnetic.com>,\n <jbehrens@vmware.com>, <maxime.coquelin@redhat.com>,\n <chenbo.xia@intel.com>, <steven.webster@windriver.com>,\n <matt.peters@windriver.com>, <bruce.richardson@intel.com>,\n <mtetsuyah@gmail.com>, <grive@u256.net>, <jasvinder.singh@intel.com>,\n <cristian.dumitrescu@intel.com>, <jgrajcia@cisco.com>,\n Ankur Dwivedi <adwivedi@marvell.com>", "Subject": "[PATCH 5/6] ethdev: add trace points for driver", "Date": "Thu, 4 Aug 2022 19:14:29 +0530", "Message-ID": "<20220804134430.6192-6-adwivedi@marvell.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20220804134430.6192-1-adwivedi@marvell.com>", "References": "<20220804134430.6192-1-adwivedi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "gFZ-iJH2smNziLRFb2-vRoIrk5nUWXcK", "X-Proofpoint-ORIG-GUID": "gFZ-iJH2smNziLRFb2-vRoIrk5nUWXcK", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-04_03,2022-08-04_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds trace points for ethdev driver specific functions in\nethdev lib.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\n---\n lib/ethdev/ethdev_driver.c | 29 +++++\n lib/ethdev/ethdev_trace_points.c | 66 ++++++++++\n lib/ethdev/rte_ethdev_trace.h | 200 +++++++++++++++++++++++++++++++\n lib/ethdev/version.map | 22 ++++\n 4 files changed, 317 insertions(+)", "diff": "diff --git a/lib/ethdev/ethdev_driver.c b/lib/ethdev/ethdev_driver.c\nindex a285f213f0..74ec57f5fe 100644\n--- a/lib/ethdev/ethdev_driver.c\n+++ b/lib/ethdev/ethdev_driver.c\n@@ -5,6 +5,7 @@\n #include <rte_kvargs.h>\n #include <rte_malloc.h>\n \n+#include \"rte_ethdev_trace.h\"\n #include \"ethdev_driver.h\"\n #include \"ethdev_private.h\"\n \n@@ -113,6 +114,7 @@ rte_eth_dev_allocate(const char *name)\n unlock:\n \trte_spinlock_unlock(ð_dev_shared_data->ownership_lock);\n \n+\trte_ethdev_trace_allocate(name, eth_dev);\n \treturn eth_dev;\n }\n \n@@ -121,6 +123,7 @@ rte_eth_dev_allocated(const char *name)\n {\n \tstruct rte_eth_dev *ethdev;\n \n+\trte_ethdev_trace_allocated(name);\n \teth_dev_shared_data_prepare();\n \n \trte_spinlock_lock(ð_dev_shared_data->ownership_lock);\n@@ -162,6 +165,7 @@ rte_eth_dev_attach_secondary(const char *name)\n \t}\n \n \trte_spinlock_unlock(ð_dev_shared_data->ownership_lock);\n+\trte_ethdev_trace_attach_secondary(name, eth_dev);\n \treturn eth_dev;\n }\n \n@@ -173,6 +177,7 @@ rte_eth_dev_callback_process(struct rte_eth_dev *dev,\n \tstruct rte_eth_dev_callback dev_cb;\n \tint rc = 0;\n \n+\trte_ethdev_trace_callback_process(dev, event, ret_param);\n \trte_spinlock_lock(ð_dev_cb_lock);\n \tTAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {\n \t\tif (cb_lst->cb_fn == NULL || cb_lst->event != event)\n@@ -195,6 +200,7 @@ rte_eth_dev_callback_process(struct rte_eth_dev *dev,\n void\n rte_eth_dev_probing_finish(struct rte_eth_dev *dev)\n {\n+\trte_ethdev_trace_probing_finish(dev);\n \tif (dev == NULL)\n \t\treturn;\n \n@@ -214,6 +220,7 @@ rte_eth_dev_probing_finish(struct rte_eth_dev *dev)\n int\n rte_eth_dev_release_port(struct rte_eth_dev *eth_dev)\n {\n+\trte_ethdev_trace_release_port(eth_dev);\n \tif (eth_dev == NULL)\n \t\treturn -EINVAL;\n \n@@ -264,6 +271,9 @@ rte_eth_dev_create(struct rte_device *device, const char *name,\n \tstruct rte_eth_dev *ethdev;\n \tint retval;\n \n+\trte_ethdev_trace_create(device, name, priv_data_size,\n+\t\t\t\tethdev_bus_specific_init, bus_init_params,\n+\t\t\t\tethdev_init, init_params);\n \tRTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL);\n \n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n@@ -324,6 +334,7 @@ rte_eth_dev_destroy(struct rte_eth_dev *ethdev,\n {\n \tint ret;\n \n+\trte_ethdev_trace_destroy(ethdev, ethdev_uninit);\n \tethdev = rte_eth_dev_allocated(ethdev->data->name);\n \tif (!ethdev)\n \t\treturn -ENODEV;\n@@ -342,6 +353,7 @@ rte_eth_dev_get_by_name(const char *name)\n {\n \tuint16_t pid;\n \n+\trte_ethdev_trace_get_by_name(name);\n \tif (rte_eth_dev_get_port_by_name(name, &pid))\n \t\treturn NULL;\n \n@@ -351,6 +363,7 @@ rte_eth_dev_get_by_name(const char *name)\n int\n rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n+\trte_ethdev_trace_is_rx_hairpin_queue(dev, queue_id);\n \tif (dev->data->rx_queue_state[queue_id] == RTE_ETH_QUEUE_STATE_HAIRPIN)\n \t\treturn 1;\n \treturn 0;\n@@ -359,6 +372,7 @@ rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)\n int\n rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n+\trte_ethdev_trace_is_tx_hairpin_queue(dev, queue_id);\n \tif (dev->data->tx_queue_state[queue_id] == RTE_ETH_QUEUE_STATE_HAIRPIN)\n \t\treturn 1;\n \treturn 0;\n@@ -367,6 +381,7 @@ rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)\n void\n rte_eth_dev_internal_reset(struct rte_eth_dev *dev)\n {\n+\trte_ethdev_trace_internal_reset(dev, dev->data->dev_started);\n \tif (dev->data->dev_started) {\n \t\tRTE_ETHDEV_LOG(ERR, \"Port %u must be stopped to allow reset\\n\",\n \t\t\tdev->data->port_id);\n@@ -451,6 +466,7 @@ rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da)\n \tunsigned int i;\n \tint result = 0;\n \n+\trte_eth_trace_devargs_parse(dargs, eth_da);\n \tmemset(eth_da, 0, sizeof(*eth_da));\n \n \tresult = eth_dev_devargs_tokenise(&args, dargs);\n@@ -495,6 +511,7 @@ rte_eth_dma_zone_free(const struct rte_eth_dev *dev, const char *ring_name,\n \tconst struct rte_memzone *mz;\n \tint rc = 0;\n \n+\trte_eth_trace_dma_zone_free(dev, ring_name, queue_id);\n \trc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,\n \t\t\tqueue_id, ring_name);\n \tif (rc >= RTE_MEMZONE_NAMESIZE) {\n@@ -520,6 +537,7 @@ rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name,\n \tconst struct rte_memzone *mz;\n \tint rc;\n \n+\trte_eth_trace_dma_zone_reserve(dev, ring_name, queue_id, size, align, socket_id);\n \trc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id,\n \t\t\tqueue_id, ring_name);\n \tif (rc >= RTE_MEMZONE_NAMESIZE) {\n@@ -553,6 +571,8 @@ rte_eth_hairpin_queue_peer_bind(uint16_t cur_port, uint16_t cur_queue,\n {\n \tstruct rte_eth_dev *dev;\n \n+\trte_eth_trace_hairpin_queue_peer_bind(cur_port, cur_queue, peer_info,\n+\t\t\t\t\t direction);\n \tif (peer_info == NULL)\n \t\treturn -EINVAL;\n \n@@ -571,6 +591,7 @@ rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue,\n {\n \tstruct rte_eth_dev *dev;\n \n+\trte_eth_trace_hairpin_queue_peer_unbind(cur_port, cur_queue, direction);\n \t/* No need to check the validity again. */\n \tdev = &rte_eth_devices[cur_port];\n \tRTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_unbind,\n@@ -588,6 +609,8 @@ rte_eth_hairpin_queue_peer_update(uint16_t peer_port, uint16_t peer_queue,\n {\n \tstruct rte_eth_dev *dev;\n \n+\trte_eth_trace_hairpin_queue_peer_update(peer_port, peer_queue, cur_info,\n+\t\t\t\t\t\tpeer_info, direction);\n \t/* Current queue information is not mandatory. */\n \tif (peer_info == NULL)\n \t\treturn -EINVAL;\n@@ -626,6 +649,8 @@ rte_eth_ip_reassembly_dynfield_register(int *field_offset, int *flag_offset)\n \tif (flag_offset != NULL)\n \t\t*flag_offset = offset;\n \n+\trte_eth_trace_ip_reassembly_dynfield_register(*field_offset,\n+\t\t\t\t\t\t *flag_offset);\n \treturn 0;\n }\n \n@@ -729,6 +754,8 @@ rte_eth_representor_id_get(uint16_t port_id,\n \t}\n out:\n \tfree(info);\n+\trte_eth_trace_representor_id_get(port_id, type, controller, pf,\n+\t\t\t\t\t representor_port, *repr_id);\n \treturn ret;\n }\n \n@@ -745,6 +772,7 @@ rte_eth_switch_domain_alloc(uint16_t *domain_id)\n \t\t\teth_dev_switch_domains[i].state =\n \t\t\t\tRTE_ETH_SWITCH_DOMAIN_ALLOCATED;\n \t\t\t*domain_id = i;\n+\t\t\trte_eth_trace_switch_domain_alloc(*domain_id);\n \t\t\treturn 0;\n \t\t}\n \t}\n@@ -755,6 +783,7 @@ rte_eth_switch_domain_alloc(uint16_t *domain_id)\n int\n rte_eth_switch_domain_free(uint16_t domain_id)\n {\n+\trte_eth_trace_switch_domain_free(domain_id);\n \tif (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||\n \t\tdomain_id >= RTE_MAX_ETHPORTS)\n \t\treturn -EINVAL;\ndiff --git a/lib/ethdev/ethdev_trace_points.c b/lib/ethdev/ethdev_trace_points.c\nindex 341901d031..61539f379c 100644\n--- a/lib/ethdev/ethdev_trace_points.c\n+++ b/lib/ethdev/ethdev_trace_points.c\n@@ -731,3 +731,69 @@ RTE_TRACE_POINT_REGISTER(rte_tm_trace_wred_profile_add,\n \n RTE_TRACE_POINT_REGISTER(rte_tm_trace_wred_profile_delete,\n \tlib.ethdev.tm.wred_profile_delete)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_allocate,\n+\tlib.ethdev.allocate)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_allocated,\n+\tlib.ethdev.allocated)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_attach_secondary,\n+\tlib.ethdev.attach_secondary)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_callback_process,\n+\tlib.ethdev.callback_process)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_create,\n+\tlib.ethdev_create)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_destroy,\n+\tlib.ethdev.destroy)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_get_by_name,\n+\tlib.ethdev.get_by_name)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_is_rx_hairpin_queue,\n+\tlib.ethdev.is_rx_hairpin_queue)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_is_tx_hairpin_queue,\n+\tlib.ethdev.is_tx_hairpin_queue)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_probing_finish,\n+\tlib.ethdev.probing_finish)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_release_port,\n+\tlib.ethdev.release_port)\n+\n+RTE_TRACE_POINT_REGISTER(rte_ethdev_trace_internal_reset,\n+\tlib.ethdev.internal_reset)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_devargs_parse,\n+\tlib.ethdev.devargs_parse)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_dma_zone_free,\n+\tlib.ethdev.dma_zone_free)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_dma_zone_reserve,\n+\tlib.ethdev.dma_zone_reserve)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_hairpin_queue_peer_bind,\n+\tlib.ethdev.hairpin_queue_peer_bind)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_hairpin_queue_peer_unbind,\n+\tlib.ethdev.hairpin_queue_peer_unbind)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_hairpin_queue_peer_update,\n+\tlib.ethdev.hairpin_queue_peer_update)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_ip_reassembly_dynfield_register,\n+\tlib.ethdev.ip_reassembly_dynfield_register)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_representor_id_get,\n+\tlib.ethdev.representor_id_get)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_switch_domain_alloc,\n+\tlib.ethdev.switch_domain_alloc)\n+\n+RTE_TRACE_POINT_REGISTER(rte_eth_trace_switch_domain_free,\n+\tlib.ethdev.switch_domain_free)\ndiff --git a/lib/ethdev/rte_ethdev_trace.h b/lib/ethdev/rte_ethdev_trace.h\nindex aa34a6a5e9..a3c0b6fa76 100644\n--- a/lib/ethdev/rte_ethdev_trace.h\n+++ b/lib/ethdev/rte_ethdev_trace.h\n@@ -17,6 +17,7 @@ extern \"C\" {\n \n #include <rte_trace_point.h>\n \n+#include \"ethdev_driver.h\"\n #include \"rte_ethdev.h\"\n #include \"rte_mtr.h\"\n #include \"rte_tm.h\"\n@@ -2134,6 +2135,205 @@ RTE_TRACE_POINT(\n \trte_trace_point_emit_u32(wred_profile_id);\n )\n \n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_allocate,\n+\tRTE_TRACE_POINT_ARGS(const char *name, struct rte_eth_dev *eth_dev),\n+\trte_trace_point_emit_string(name);\n+\trte_trace_point_emit_u16(eth_dev->data->nb_rx_queues);\n+\trte_trace_point_emit_u16(eth_dev->data->nb_tx_queues);\n+\trte_trace_point_emit_u16(eth_dev->data->mtu);\n+\trte_trace_point_emit_u16(eth_dev->data->port_id);\n+\trte_trace_point_emit_int(eth_dev->state);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_allocated,\n+\tRTE_TRACE_POINT_ARGS(const char *name),\n+\trte_trace_point_emit_string(name);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_attach_secondary,\n+\tRTE_TRACE_POINT_ARGS(const char *name, struct rte_eth_dev *eth_dev),\n+\trte_trace_point_emit_string(name);\n+\trte_trace_point_emit_u16(eth_dev->data->nb_rx_queues);\n+\trte_trace_point_emit_u16(eth_dev->data->nb_tx_queues);\n+\trte_trace_point_emit_u16(eth_dev->data->mtu);\n+\trte_trace_point_emit_u16(eth_dev->data->port_id);\n+\trte_trace_point_emit_int(eth_dev->state);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_callback_process,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *dev,\n+\t\tenum rte_eth_event_type event,\n+\t\tvoid *ret_param),\n+\trte_trace_point_emit_ptr(dev);\n+\trte_trace_point_emit_int(event);\n+\trte_trace_point_emit_ptr(ret_param);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_create,\n+\tRTE_TRACE_POINT_ARGS(struct rte_device *device, const char *name,\n+\t\tsize_t priv_data_size,\n+\t\tethdev_bus_specific_init bus_specific_init,\n+\t\tvoid *bus_init_params, ethdev_init_t ethdev_init,\n+\t\tvoid *init_params),\n+\trte_trace_point_emit_ptr(device);\n+\trte_trace_point_emit_string(name);\n+\trte_trace_point_emit_size_t(priv_data_size);\n+\trte_trace_point_emit_ptr(bus_specific_init);\n+\trte_trace_point_emit_ptr(bus_init_params);\n+\trte_trace_point_emit_ptr(ethdev_init);\n+\trte_trace_point_emit_ptr(init_params);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_destroy,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *ethdev, ethdev_uninit_t ethdev_uninit),\n+\trte_trace_point_emit_ptr(ethdev);\n+\trte_trace_point_emit_ptr(ethdev_uninit);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_get_by_name,\n+\tRTE_TRACE_POINT_ARGS(const char *name),\n+\trte_trace_point_emit_string(name);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_is_rx_hairpin_queue,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *dev, uint16_t queue_id),\n+\trte_trace_point_emit_ptr(dev);\n+\trte_trace_point_emit_u16(queue_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_is_tx_hairpin_queue,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *dev, uint16_t queue_id),\n+\trte_trace_point_emit_ptr(dev);\n+\trte_trace_point_emit_u16(queue_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_probing_finish,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *dev),\n+\trte_trace_point_emit_ptr(dev);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_release_port,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *eth_dev),\n+\trte_trace_point_emit_ptr(eth_dev);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_ethdev_trace_internal_reset,\n+\tRTE_TRACE_POINT_ARGS(struct rte_eth_dev *dev,\n+\t\tuint8_t dev_started),\n+\trte_trace_point_emit_ptr(dev);\n+\trte_trace_point_emit_u8(dev_started);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_devargs_parse,\n+\tRTE_TRACE_POINT_ARGS(const char *devargs, struct rte_eth_devargs *eth_devargs),\n+\trte_trace_point_emit_string(devargs);\n+\trte_trace_point_emit_ptr(eth_devargs);\n+\trte_trace_point_emit_u16(eth_devargs->nb_mh_controllers);\n+\trte_trace_point_emit_u16(eth_devargs->nb_ports);\n+\trte_trace_point_emit_u16(eth_devargs->nb_representor_ports);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_dma_zone_free,\n+\tRTE_TRACE_POINT_ARGS(const struct rte_eth_dev *eth_dev, const char *name,\n+\t\tuint16_t queue_id),\n+\trte_trace_point_emit_ptr(eth_dev);\n+\trte_trace_point_emit_string(name);\n+\trte_trace_point_emit_u16(queue_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_dma_zone_reserve,\n+\tRTE_TRACE_POINT_ARGS(const struct rte_eth_dev *eth_dev, const char *name,\n+\t\tuint16_t queue_id, size_t size, unsigned int align,\n+\t\tint socket_id),\n+\trte_trace_point_emit_ptr(eth_dev);\n+\trte_trace_point_emit_string(name);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_size_t(size);\n+\trte_trace_point_emit_u32(align);\n+\trte_trace_point_emit_int(socket_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_hairpin_queue_peer_bind,\n+\tRTE_TRACE_POINT_ARGS(uint16_t cur_port, uint16_t cur_queue,\n+\t\tstruct rte_hairpin_peer_info *peer_info,\n+\t\tuint32_t direction),\n+\trte_trace_point_emit_u16(cur_port);\n+\trte_trace_point_emit_u16(cur_queue);\n+\trte_trace_point_emit_ptr(peer_info);\n+\trte_trace_point_emit_u32(direction);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_hairpin_queue_peer_unbind,\n+\tRTE_TRACE_POINT_ARGS(uint16_t cur_port, uint16_t cur_queue,\n+\t\tuint32_t direction),\n+\trte_trace_point_emit_u16(cur_port);\n+\trte_trace_point_emit_u16(cur_queue);\n+\trte_trace_point_emit_u32(direction);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_hairpin_queue_peer_update,\n+\tRTE_TRACE_POINT_ARGS(uint16_t peer_port, uint16_t peer_queue,\n+\t\tstruct rte_hairpin_peer_info *cur_info,\n+\t\tstruct rte_hairpin_peer_info *peer_info,\n+\t\tuint32_t direction),\n+\trte_trace_point_emit_u16(peer_port);\n+\trte_trace_point_emit_u16(peer_queue);\n+\trte_trace_point_emit_ptr(cur_info);\n+\trte_trace_point_emit_ptr(peer_info);\n+\trte_trace_point_emit_u32(direction);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_ip_reassembly_dynfield_register,\n+\tRTE_TRACE_POINT_ARGS(int field_offset, int flag_offset),\n+\trte_trace_point_emit_int(field_offset);\n+\trte_trace_point_emit_int(flag_offset);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_representor_id_get,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id,\n+\t\tenum rte_eth_representor_type type,\n+\t\tint controller, int pf, int representor_port,\n+\t\tuint16_t repr_id),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_int(type);\n+\trte_trace_point_emit_int(controller);\n+\trte_trace_point_emit_int(pf);\n+\trte_trace_point_emit_int(representor_port);\n+\trte_trace_point_emit_u16(repr_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_switch_domain_alloc,\n+\tRTE_TRACE_POINT_ARGS(uint16_t domain_id),\n+\trte_trace_point_emit_u16(domain_id);\n+)\n+\n+RTE_TRACE_POINT(\n+\trte_eth_trace_switch_domain_free,\n+\tRTE_TRACE_POINT_ARGS(uint16_t domain_id),\n+\trte_trace_point_emit_u16(domain_id);\n+)\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/ethdev/version.map b/lib/ethdev/version.map\nindex ee4012789f..ee3ff4793d 100644\n--- a/lib/ethdev/version.map\n+++ b/lib/ethdev/version.map\n@@ -520,6 +520,28 @@ EXPERIMENTAL {\n \t__rte_tm_trace_shared_wred_context_delete;\n \t__rte_tm_trace_wred_profile_add;\n \t__rte_tm_trace_wred_profile_delete;\n+\t__rte_ethdev_trace_allocate;\n+\t__rte_ethdev_trace_allocated;\n+\t__rte_ethdev_trace_attach_secondary;\n+\t__rte_ethdev_trace_callback_process;\n+\t__rte_ethdev_trace_create;\n+\t__rte_ethdev_trace_destroy;\n+\t__rte_ethdev_trace_get_by_name;\n+\t__rte_ethdev_trace_is_rx_hairpin_queue;\n+\t__rte_ethdev_trace_is_tx_hairpin_queue;\n+\t__rte_ethdev_trace_probing_finish;\n+\t__rte_ethdev_trace_release_port;\n+\t__rte_ethdev_trace_internal_reset;\n+\t__rte_eth_trace_devargs_parse;\n+\t__rte_eth_trace_dma_zone_free;\n+\t__rte_eth_trace_dma_zone_reserve;\n+\t__rte_eth_trace_hairpin_queue_peer_bind;\n+\t__rte_eth_trace_hairpin_queue_peer_unbind;\n+\t__rte_eth_trace_hairpin_queue_peer_update;\n+\t__rte_eth_trace_ip_reassembly_dynfield_register;\n+\t__rte_eth_trace_representor_id_get;\n+\t__rte_eth_trace_switch_domain_alloc;\n+\t__rte_eth_trace_switch_domain_free;\n };\n \n INTERNAL {\n", "prefixes": [ "5/6" ] }