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GET /api/patches/114459/?format=api
{ "id": 114459, "url": "https://patches.dpdk.org/api/patches/114459/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220729193042.2764633-10-xiaoyun.li@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220729193042.2764633-10-xiaoyun.li@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220729193042.2764633-10-xiaoyun.li@intel.com", "date": "2022-07-29T19:30:41", "name": "[09/10] net/gve: add stats support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "442a72238381d85d61d890066cd2f4d8c6bae297", "submitter": { "id": 798, "url": "https://patches.dpdk.org/api/people/798/?format=api", "name": "Li, Xiaoyun", "email": "xiaoyun.li@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220729193042.2764633-10-xiaoyun.li@intel.com/mbox/", "series": [ { "id": 24137, "url": "https://patches.dpdk.org/api/series/24137/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24137", "date": "2022-07-29T19:30:32", "name": "introduce GVE PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/24137/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/114459/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/114459/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5723FA00C4;\n\tFri, 29 Jul 2022 21:32:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E793242C63;\n\tFri, 29 Jul 2022 21:31:21 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 1F5DA42C82\n for <dev@dpdk.org>; Fri, 29 Jul 2022 21:31:18 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Jul 2022 12:31:18 -0700", "from silpixa00399779.ir.intel.com (HELO\n silpixa00399779.ger.corp.intel.com) ([10.237.223.111])\n by orsmga006.jf.intel.com with ESMTP; 29 Jul 2022 12:31:17 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1659123079; x=1690659079;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=3RDISPL1o5kz+ElcTc5DAWFZLKp2mKIlBw6Yo9Wfqzw=;\n b=bEz9U7D9+kdgervftmlJ2WC91EULOFO8GjZ90SRU30LLOPxNsilXIv5h\n n28vtA0JuC1Yo25/mMZQEp4AFS2F6HwMlIWOYmLa27YgugQ63wgVbv5OI\n wo0oC+syyZfNUx7FUpjUOArA6Vr2RONO0czF85OJ+geu7druDvJ5CMShr\n IWoSYmGHwTE48u6CKO7Au4HkFwo1wx6iAdm8ylIbi20btjv5HkYrejC83\n blXyiSSHbqPnRlBA9jwQO/X/pgJiZKc5tqg6tAREukWx7O/X90QIopM1T\n l0qC7RF06kGaRocp5YmY7YTiy6BqFUWZ+JtvVr4cNnwCwEQ4YxyCHv9sj w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10423\"; a=\"268602972\"", "E=Sophos;i=\"5.93,201,1654585200\"; d=\"scan'208\";a=\"268602972\"", "E=Sophos;i=\"5.93,201,1654585200\"; d=\"scan'208\";a=\"577059599\"" ], "X-ExtLoop1": "1", "From": "Xiaoyun Li <xiaoyun.li@intel.com>", "To": "junfeng.guo@intel.com, qi.z.zhang@intel.com, awogbemila@google.com,\n bruce.richardson@intel.com", "Cc": "dev@dpdk.org,\n\tXiaoyun Li <xiaoyun.li@intel.com>", "Subject": "[PATCH 09/10] net/gve: add stats support", "Date": "Fri, 29 Jul 2022 19:30:41 +0000", "Message-Id": "<20220729193042.2764633-10-xiaoyun.li@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220729193042.2764633-1-xiaoyun.li@intel.com>", "References": "<20220729193042.2764633-1-xiaoyun.li@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update stats add support of dev_ops stats_get/reset.\n\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\n---\n drivers/net/gve/gve.h | 10 ++++++\n drivers/net/gve/gve_ethdev.c | 69 ++++++++++++++++++++++++++++++++++++\n drivers/net/gve/gve_rx.c | 15 ++++++--\n drivers/net/gve/gve_tx.c | 12 +++++++\n 4 files changed, 104 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/gve/gve.h b/drivers/net/gve/gve.h\nindex 004e0a75ca..e256a2bec2 100644\n--- a/drivers/net/gve/gve.h\n+++ b/drivers/net/gve/gve.h\n@@ -91,6 +91,10 @@ struct gve_tx_queue {\n \tstruct gve_queue_page_list *qpl;\n \tstruct gve_tx_iovec *iov_ring;\n \n+\t/* Stats */\n+\tuint64_t packets;\n+\tuint64_t bytes;\n+\n \tuint16_t port_id;\n \tuint16_t queue_id;\n \n@@ -129,6 +133,12 @@ struct gve_rx_queue {\n \t/* only valid for GQI_QPL queue format */\n \tstruct gve_queue_page_list *qpl;\n \n+\t/* stats */\n+\tuint64_t no_mbufs;\n+\tuint64_t errors;\n+\tuint64_t packets;\n+\tuint64_t bytes;\n+\n \tstruct gve_priv *hw;\n \tconst struct rte_memzone *qres_mz;\n \tstruct gve_queue_resources *qres;\ndiff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 6bc7bf4519..2977df01f1 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -326,6 +326,73 @@ gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \treturn 0;\n }\n \n+static int\n+gve_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tstruct gve_tx_queue *txq = dev->data->tx_queues[i];\n+\t\tif (txq == NULL)\n+\t\t\tcontinue;\n+\n+\t\tstats->opackets += txq->packets;\n+\t\tstats->obytes += txq->bytes;\n+\n+\t\tif (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n+\t\t\tstats->q_opackets[i] = txq->packets;\n+\t\t\tstats->q_obytes[i] = txq->bytes;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tstruct gve_rx_queue *rxq = dev->data->rx_queues[i];\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\n+\t\tstats->ipackets += rxq->packets;\n+\t\tstats->ibytes += rxq->bytes;\n+\t\tstats->ierrors += rxq->errors;\n+\t\tstats->rx_nombuf += rxq->no_mbufs;\n+\n+\t\tif (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n+\t\t\tstats->q_ipackets[i] = rxq->packets;\n+\t\t\tstats->q_ibytes[i] = rxq->bytes;\n+\t\t\tstats->q_errors[i] = rxq->errors;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+gve_dev_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tstruct gve_tx_queue *txq = dev->data->tx_queues[i];\n+\t\tif (txq == NULL)\n+\t\t\tcontinue;\n+\n+\t\ttxq->packets = 0;\n+\t\ttxq->bytes = 0;\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tstruct gve_rx_queue *rxq = dev->data->rx_queues[i];\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\n+\t\trxq->packets = 0;\n+\t\trxq->bytes = 0;\n+\t\trxq->no_mbufs = 0;\n+\t\trxq->errors = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n gve_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n {\n@@ -363,6 +430,8 @@ static const struct eth_dev_ops gve_eth_dev_ops = {\n \t.rx_queue_setup = gve_rx_queue_setup,\n \t.tx_queue_setup = gve_tx_queue_setup,\n \t.link_update = gve_link_update,\n+\t.stats_get = gve_dev_stats_get,\n+\t.stats_reset = gve_dev_stats_reset,\n \t.mtu_set = gve_dev_mtu_set,\n };\n \ndiff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c\nindex 8f560ae592..3a8a869980 100644\n--- a/drivers/net/gve/gve_rx.c\n+++ b/drivers/net/gve/gve_rx.c\n@@ -26,8 +26,10 @@ gve_rx_refill(struct gve_rx_queue *rxq)\n \t\t\t\t\tbreak;\n \t\t\t\trxq->sw_ring[idx + i] = nmb;\n \t\t\t}\n-\t\t\tif (i != nb_alloc)\n+\t\t\tif (i != nb_alloc) {\n+\t\t\t\trxq->no_mbufs += nb_alloc - i;\n \t\t\t\tnb_alloc = i;\n+\t\t\t}\n \t\t}\n \t\trxq->nb_avail -= nb_alloc;\n \t\tnext_avail += nb_alloc;\n@@ -88,6 +90,7 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tuint16_t rx_id = rxq->rx_tail;\n \tstruct rte_mbuf *rxe;\n \tuint16_t nb_rx, len;\n+\tuint64_t bytes = 0;\n \tuint64_t addr;\n \n \trxr = rxq->rx_desc_ring;\n@@ -97,8 +100,10 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\tif (GVE_SEQNO(rxd->flags_seq) != rxq->expected_seqno)\n \t\t\tbreak;\n \n-\t\tif (rxd->flags_seq & GVE_RXF_ERR)\n+\t\tif (rxd->flags_seq & GVE_RXF_ERR) {\n+\t\t\trxq->errors++;\n \t\t\tcontinue;\n+\t\t}\n \n \t\tlen = rte_be_to_cpu_16(rxd->len) - GVE_RX_PAD;\n \t\trxe = rxq->sw_ring[rx_id];\n@@ -137,6 +142,7 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t\trx_id = 0;\n \n \t\trx_pkts[nb_rx] = rxe;\n+\t\tbytes += len;\n \t}\n \n \trxq->nb_avail += nb_rx;\n@@ -145,6 +151,11 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tif (rxq->nb_avail > rxq->free_thresh)\n \t\tgve_rx_refill(rxq);\n \n+\tif (nb_rx) {\n+\t\trxq->packets += nb_rx;\n+\t\trxq->bytes += bytes;\n+\t}\n+\n \treturn nb_rx;\n }\n \ndiff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c\nindex 2dc3411672..d99e6eb009 100644\n--- a/drivers/net/gve/gve_tx.c\n+++ b/drivers/net/gve/gve_tx.c\n@@ -260,6 +260,7 @@ gve_tx_burst_qpl(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tstruct rte_mbuf *tx_pkt, *first;\n \tuint16_t sw_id = txq->sw_tail;\n \tuint16_t nb_used, i;\n+\tuint64_t bytes = 0;\n \tuint16_t nb_tx = 0;\n \tuint32_t hlen;\n \n@@ -352,6 +353,8 @@ gve_tx_burst_qpl(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\ttxq->nb_free -= nb_used;\n \t\ttxq->sw_nb_free -= first->nb_segs;\n \t\ttx_tail += nb_used;\n+\n+\t\tbytes += first->pkt_len;\n \t}\n \n end_of_tx:\n@@ -359,6 +362,9 @@ gve_tx_burst_qpl(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\trte_write32(rte_cpu_to_be_32(tx_tail), txq->qtx_tail);\n \t\ttxq->tx_tail = tx_tail;\n \t\ttxq->sw_tail = sw_id;\n+\n+\t\ttxq->packets += nb_tx;\n+\t\ttxq->bytes += bytes;\n \t}\n \n \treturn nb_tx;\n@@ -377,6 +383,7 @@ gve_tx_burst_ra(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tstruct rte_mbuf *tx_pkt, *first;\n \tuint16_t nb_used, hlen, i;\n \tuint64_t ol_flags, addr;\n+\tuint64_t bytes = 0;\n \tuint16_t nb_tx = 0;\n \n \ttxr = txq->tx_desc_ring;\n@@ -435,12 +442,17 @@ gve_tx_burst_ra(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \n \t\ttxq->nb_free -= nb_used;\n \t\ttx_tail += nb_used;\n+\n+\t\tbytes += first->pkt_len;\n \t}\n \n end_of_tx:\n \tif (nb_tx) {\n \t\trte_write32(rte_cpu_to_be_32(tx_tail), txq->qtx_tail);\n \t\ttxq->tx_tail = tx_tail;\n+\n+\t\ttxq->packets += nb_tx;\n+\t\ttxq->bytes += bytes;\n \t}\n \n \treturn nb_tx;\n", "prefixes": [ "09/10" ] }