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{
    "id": 11401,
    "url": "https://patches.dpdk.org/api/patches/11401/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1457617548-26252-10-git-send-email-rasesh.mody@qlogic.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1457617548-26252-10-git-send-email-rasesh.mody@qlogic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1457617548-26252-10-git-send-email-rasesh.mody@qlogic.com",
    "date": "2016-03-10T13:45:47",
    "name": "[dpdk-dev,v2,09/10] qede: Add DCBX support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c0637e169b8d2c107f18304a9b9151e7d0512c85",
    "submitter": {
        "id": 325,
        "url": "https://patches.dpdk.org/api/people/325/?format=api",
        "name": "Rasesh Mody",
        "email": "rasesh.mody@qlogic.com"
    },
    "delegate": {
        "id": 10,
        "url": "https://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1457617548-26252-10-git-send-email-rasesh.mody@qlogic.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/11401/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/11401/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 32ADD530F;\n\tThu, 10 Mar 2016 14:46:53 +0100 (CET)",
            "from mx0b-0016ce01.pphosted.com (mx0b-0016ce01.pphosted.com\n\t[67.231.156.153]) by dpdk.org (Postfix) with ESMTP id 518EF4CE7\n\tfor <dev@dpdk.org>; Thu, 10 Mar 2016 14:46:51 +0100 (CET)",
            "from pps.filterd (m0085408.ppops.net [127.0.0.1])\n\tby mx0b-0016ce01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id\n\tu2ADdH2W021831 for <dev@dpdk.org>; Thu, 10 Mar 2016 05:46:50 -0800",
            "from avcashub1.qlogic.com ([198.186.0.115])\n\tby mx0b-0016ce01.pphosted.com with ESMTP id 21fyat9bg7-1\n\t(version=TLSv1 cipher=AES128-SHA bits=128 verify=NOT)\n\tfor <dev@dpdk.org>; Thu, 10 Mar 2016 05:46:50 -0800",
            "from avluser05.qlc.com (10.1.113.115) by qlc.com (10.1.4.190) with\n\tMicrosoft SMTP Server id 14.3.235.1;\n\tThu, 10 Mar 2016 05:46:48 -0800",
            "(from rmody@localhost)\tby avluser05.qlc.com (8.14.4/8.14.4/Submit)\n\tid u2ADkntd026381;\tThu, 10 Mar 2016 05:46:49 -0800"
        ],
        "X-Authentication-Warning": "avluser05.qlc.com: rmody set sender to\n\trasesh.mody@qlogic.com using -f",
        "From": "Rasesh Mody <rasesh.mody@qlogic.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Thu, 10 Mar 2016 05:45:47 -0800",
        "Message-ID": "<1457617548-26252-10-git-send-email-rasesh.mody@qlogic.com>",
        "X-Mailer": "git-send-email 1.7.10.3",
        "In-Reply-To": "<1457617548-26252-1-git-send-email-rasesh.mody@qlogic.com>",
        "References": "<1457617548-26252-1-git-send-email-rasesh.mody@qlogic.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "disclaimer": "bypass",
        "X-Proofpoint-Virus-Version": "vendor=nai engine=5800 definitions=8099\n\tsignatures=670697",
        "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 suspectscore=4\n\tmalwarescore=0\n\tphishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0\n\tadultscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1601100000 definitions=main-1603100224",
        "Cc": "sony.chacko@qlogic.com",
        "Subject": "[dpdk-dev] [PATCH v2 09/10] qede: Add DCBX support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Signed-off-by: Harish Patil <harish.patil@qlogic.com>\nSigned-off-by: Rasesh Mody <rasesh.mody@qlogic.com>\nSigned-off-by: Sony Chacko <sony.chacko@qlogic.com>\n---\n drivers/net/qede/Makefile                 |    1 +\n drivers/net/qede/base/bcm_osal.h          |  100 ++--\n drivers/net/qede/base/ecore.h             |    2 +\n drivers/net/qede/base/ecore_dcbx.c        |  887 +++++++++++++++++++++++++++++\n drivers/net/qede/base/ecore_dcbx.h        |   55 ++\n drivers/net/qede/base/ecore_dcbx_api.h    |  160 ++++++\n drivers/net/qede/base/ecore_dev.c         |   27 +\n drivers/net/qede/base/ecore_l2.c          |    3 -\n drivers/net/qede/base/ecore_mcp.c         |   16 +\n drivers/net/qede/base/ecore_sp_commands.c |    4 +\n drivers/net/qede/base/mcp_public.h        |  200 +++++++\n drivers/net/qede/base/nvm_cfg.h           |    6 +\n drivers/net/qede/qede_main.c              |    6 +-\n drivers/net/qede/qede_rxtx.c              |    2 +-\n 14 files changed, 1406 insertions(+), 63 deletions(-)\n create mode 100644 drivers/net/qede/base/ecore_dcbx.c\n create mode 100644 drivers/net/qede/base/ecore_dcbx.h\n create mode 100644 drivers/net/qede/base/ecore_dcbx_api.h",
    "diff": "diff --git a/drivers/net/qede/Makefile b/drivers/net/qede/Makefile\nindex 8970921..cb59bbe 100644\n--- a/drivers/net/qede/Makefile\n+++ b/drivers/net/qede/Makefile\n@@ -77,6 +77,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_spq.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_init_ops.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_mcp.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_int.c\n+SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_dcbx.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/bcm_osal.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_sriov.c\n SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += base/ecore_vf.c\ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 4d81101..26221e5 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -22,6 +22,8 @@\n /* Forward declaration */\n struct ecore_dev;\n struct ecore_hwfn;\n+struct ecore_vf_acquire_sw_info;\n+struct vf_pf_resc_request;\n \n #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n #undef __BIG_ENDIAN\n@@ -270,60 +272,43 @@ typedef struct osal_list_t {\n \n /* Barriers */\n \n-#define OSAL_MMIOWB(dev) rte_wmb()\t/* No user space equivalent */\n-#define OSAL_BARRIER(dev) rte_compiler_barrier()\n-#define OSAL_SMP_RMB(dev) rte_rmb()\n-#define OSAL_SMP_WMB(dev) rte_wmb()\n-#define OSAL_RMB(dev) rte_rmb()\n-#define OSAL_WMB(dev) rte_wmb()\n+#define OSAL_MMIOWB(dev)\t\trte_wmb()\n+#define OSAL_BARRIER(dev)\t\trte_compiler_barrier()\n+#define OSAL_SMP_RMB(dev)\t\trte_rmb()\n+#define OSAL_SMP_WMB(dev)\t\trte_wmb()\n+#define OSAL_RMB(dev)\t\t\trte_rmb()\n+#define OSAL_WMB(dev)\t\t\trte_wmb()\n #define OSAL_DMA_SYNC(dev, addr, length, is_post) nothing\n \n-#define OSAL_BITS_PER_BYTE\t(8)\n+#define OSAL_BITS_PER_BYTE\t\t(8)\n #define OSAL_BITS_PER_UL\t(sizeof(unsigned long)*OSAL_BITS_PER_BYTE)\n-#define OSAL_BITS_PER_UL_MASK   (OSAL_BITS_PER_UL - 1)\n-\n-#define OSAL_BUILD_BUG_ON(cond) nothing\n-#define ETH_ALEN ETHER_ADDR_LEN\n-\n-static inline u32 osal_ffz(unsigned long word)\n-{\n-\tunsigned long first_zero;\n-\n-\tfirst_zero = __builtin_ffsl(~word);\n-\treturn first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;\n-}\n-\n-static inline void OSAL_SET_BIT(u32 nr, unsigned long *addr)\n-{\n-\taddr[nr / OSAL_BITS_PER_UL] |= 1UL << (nr & OSAL_BITS_PER_UL_MASK);\n-}\n-\n-static inline void OSAL_CLEAR_BIT(u32 nr, unsigned long *addr)\n-{\n-\taddr[nr / OSAL_BITS_PER_UL] &= ~(1UL << (nr & OSAL_BITS_PER_UL_MASK));\n-}\n-\n-static inline bool OSAL_TEST_BIT(u32 nr, unsigned long *addr)\n-{\n-\treturn !!(addr[nr / OSAL_BITS_PER_UL] &\n-\t\t   (1UL << (nr & OSAL_BITS_PER_UL_MASK)));\n-}\n-\n-static inline u32 OSAL_FIND_FIRST_ZERO_BIT(unsigned long *addr, u32 limit)\n-{\n-\tu32 i;\n-\tu32 nwords = 0;\n-\tOSAL_BUILD_BUG_ON(!limit);\n-\tnwords = (limit - 1) / OSAL_BITS_PER_UL + 1;\n-\tfor (i = 0; i < nwords; i++)\n-\t\tif (~(addr[i] != 0))\n-\t\t\tbreak;\n-\treturn (i == nwords) ? limit : i * OSAL_BITS_PER_UL + osal_ffz(addr[i]);\n-}\n+#define OSAL_BITS_PER_UL_MASK\t\t(OSAL_BITS_PER_UL - 1)\n \n-/* SR-IOV channel */\n+/* Bitops */\n+void qede_set_bit(u32, unsigned long *);\n+#define OSAL_SET_BIT(bit, bitmap) \\\n+\tqede_set_bit(bit, bitmap)\n+\n+void qede_clr_bit(u32, unsigned long *);\n+#define OSAL_CLEAR_BIT(bit, bitmap) \\\n+\tqede_clr_bit(bit, bitmap)\n+\n+bool qede_test_bit(u32, unsigned long *);\n+#define OSAL_TEST_BIT(bit, bitmap) \\\n+\tqede_test_bit(bit, bitmap)\n+\n+u32 qede_find_first_zero_bit(unsigned long *, u32);\n+#define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \\\n+\tqede_find_first_zero_bit(bitmap, length)\n+\n+#define OSAL_BUILD_BUG_ON(cond)\t\tnothing\n+#define ETH_ALEN\t\t\tETHER_ADDR_LEN\n \n #define OSAL_LINK_UPDATE(hwfn) nothing\n+#define OSAL_DCBX_AEN(hwfn, mib_type) nothing\n+\n+/* SR-IOV channel */\n+\n #define OSAL_VF_FLR_UPDATE(hwfn) nothing\n #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0\n #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol)\t(0)\n@@ -333,15 +318,18 @@ static inline u32 OSAL_FIND_FIRST_ZERO_BIT(unsigned long *addr, u32 limit)\n #define OSAL_IOV_VF_ACQUIRE(hwfn, vfid) 0\n #define OSAL_IOV_VF_CLEANUP(hwfn, vfid) nothing\n #define OSAL_IOV_VF_VPORT_UPDATE(hwfn, vfid, p_params, p_mask) 0\n-#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(_dev_p, _resc_req, _os_info) nothing\n #define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(_dev_p, _resc_resp) 0\n #define OSAL_IOV_GET_OS_TYPE() 0\n \n-u32 qed_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,\n-\t\t   u8 *input_buf, u32 max_size, u8 *unzip_buf);\n+void qede_vf_fill_driver_data(struct ecore_hwfn *, struct vf_pf_resc_request *,\n+\t\t\t      struct ecore_vf_acquire_sw_info *);\n+#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(_dev_p, _resc_req, _os_info) \\\n+\tqede_vf_fill_driver_data(_dev_p, _resc_req, _os_info)\n \n+u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,\n+\t\t   u8 *input_buf, u32 max_size, u8 *unzip_buf);\n #define OSAL_UNZIP_DATA(p_hwfn, input_len, buf, max_size, unzip_buf) \\\n-\tqed_unzip_data(p_hwfn, input_len, buf, max_size, unzip_buf)\n+\tqede_unzip_data(p_hwfn, input_len, buf, max_size, unzip_buf)\n \n /* TODO: */\n #define OSAL_SCHEDULE_RECOVERY_HANDLER(hwfn) nothing\n@@ -357,13 +345,13 @@ u32 qed_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,\n #define RTE_ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))\n #define ROUNDUP(value, to_what) RTE_ROUNDUP((value), (to_what))\n \n-unsigned long log2_align(unsigned long n);\n+unsigned long qede_log2_align(unsigned long n);\n #define OSAL_ROUNDUP_POW_OF_TWO(val) \\\n-\tlog2_align(val)\n+\tqede_log2_align(val)\n \n-u32 osal_log2(u32 val);\n+u32 qede_osal_log2(u32);\n #define OSAL_LOG2(val) \\\n-\tosal_log2(val)\n+\tqede_osal_log2(val)\n \n #define PRINT(format, ...) printf\n #define PRINT_ERR(format, ...) PRINT\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex 942aaee..79e7526 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -152,6 +152,7 @@ struct ecore_dma_mem;\n struct ecore_sb_sp_info;\n struct ecore_igu_info;\n struct ecore_mcp_info;\n+struct ecore_dcbx_info;\n \n struct ecore_rt_data {\n \tu32 *init_val;\n@@ -499,6 +500,7 @@ struct ecore_hwfn {\n \tstruct ecore_vf_iov *vf_iov_info;\n \tstruct ecore_pf_iov *pf_iov_info;\n \tstruct ecore_mcp_info *mcp_info;\n+\tstruct ecore_dcbx_info *p_dcbx_info;\n \n \tstruct ecore_hw_cid_data *p_tx_cids;\n \tstruct ecore_hw_cid_data *p_rx_cids;\ndiff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c\nnew file mode 100644\nindex 0000000..6a966cb\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_dcbx.c\n@@ -0,0 +1,887 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#include \"bcm_osal.h\"\n+#include \"ecore.h\"\n+#include \"ecore_sp_commands.h\"\n+#include \"ecore_dcbx.h\"\n+#include \"ecore_cxt.h\"\n+#include \"ecore_gtt_reg_addr.h\"\n+#include \"ecore_iro.h\"\n+\n+#define ECORE_DCBX_MAX_MIB_READ_TRY\t(100)\n+#define ECORE_MAX_PFC_PRIORITIES\t8\n+#define ECORE_ETH_TYPE_DEFAULT\t\t(0)\n+\n+#define ECORE_DCBX_INVALID_PRIORITY\t0xFF\n+\n+/* Get Traffic Class from priority traffic class table, 4 bits represent\n+ * the traffic class corresponding to the priority.\n+ */\n+#define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \\\n+\t\t((u32)(pri_tc_tbl >> ((7 - prio) * 4)) & 0x7)\n+\n+static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap)\n+{\n+\treturn (ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==\n+\t\tDCBX_APP_SF_ETHTYPE) ? true : false;\n+}\n+\n+static bool ecore_dcbx_app_port(u32 app_info_bitmap)\n+{\n+\treturn (ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==\n+\t\tDCBX_APP_SF_PORT) ? true : false;\n+}\n+\n+static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id)\n+{\n+\treturn (ecore_dcbx_app_ethtype(app_info_bitmap) &&\n+\t\tproto_id == ECORE_ETH_TYPE_DEFAULT) ? true : false;\n+}\n+\n+static bool ecore_dcbx_enabled(u32 dcbx_cfg_bitmap)\n+{\n+\treturn (ECORE_MFW_GET_FIELD(dcbx_cfg_bitmap, DCBX_CONFIG_VERSION) ==\n+\t\tDCBX_CONFIG_VERSION_DISABLED) ? false : true;\n+}\n+\n+static bool ecore_dcbx_cee(u32 dcbx_cfg_bitmap)\n+{\n+\treturn (ECORE_MFW_GET_FIELD(dcbx_cfg_bitmap, DCBX_CONFIG_VERSION) ==\n+\t\tDCBX_CONFIG_VERSION_CEE) ? true : false;\n+}\n+\n+static bool ecore_dcbx_ieee(u32 dcbx_cfg_bitmap)\n+{\n+\treturn (ECORE_MFW_GET_FIELD(dcbx_cfg_bitmap, DCBX_CONFIG_VERSION) ==\n+\t\tDCBX_CONFIG_VERSION_IEEE) ? true : false;\n+}\n+\n+/* @@@TBD A0 Eagle workaround */\n+void ecore_dcbx_eagle_workaround(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t struct ecore_ptt *p_ptt, bool set_to_pfc)\n+{\n+\tif (!ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))\n+\t\treturn;\n+\n+\tecore_wr(p_hwfn, p_ptt,\n+\t\t YSEM_REG_FAST_MEMORY + 0x20000 /* RAM in FASTMEM */  +\n+\t\t YSTORM_FLOW_CONTROL_MODE_OFFSET,\n+\t\t set_to_pfc ? flow_ctrl_pfc : flow_ctrl_pause);\n+\tecore_wr(p_hwfn, p_ptt, NIG_REG_FLOWCTRL_MODE,\n+\t\t EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE);\n+}\n+\n+static void\n+ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,\n+\t\t       struct ecore_dcbx_results *p_data)\n+{\n+\tstruct ecore_hw_info *p_info = &p_hwfn->hw_info;\n+\tenum dcbx_protocol_type id;\n+\tbool enable, update;\n+\tu8 prio, tc, size;\n+\tconst char *name;\t/* @DPDK */\n+\tint i;\n+\n+\tsize = OSAL_ARRAY_SIZE(ecore_dcbx_app_update);\n+\n+\tDP_INFO(p_hwfn, \"DCBX negotiated: %d\\n\", p_data->dcbx_enabled);\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tid = ecore_dcbx_app_update[i].id;\n+\t\tname = ecore_dcbx_app_update[i].name;\n+\n+\t\tenable = p_data->arr[id].enable;\n+\t\tupdate = p_data->arr[id].update;\n+\t\ttc = p_data->arr[id].tc;\n+\t\tprio = p_data->arr[id].priority;\n+\n+\t\tDP_INFO(p_hwfn,\n+\t\t\t\"%s info: update %d, enable %d, prio %d, tc %d, num_tc %d\\n\",\n+\t\t\tname, update, enable, prio, tc, p_info->num_tc);\n+\t}\n+}\n+\n+static void\n+ecore_dcbx_set_pf_tcs(struct ecore_hw_info *p_info,\n+\t\t      u8 tc, enum ecore_pci_personality personality)\n+{\n+\t/* QM reconf data */\n+\tif (p_info->personality == personality) {\n+\t\tif (personality == ECORE_PCI_ETH)\n+\t\t\tp_info->non_offload_tc = tc;\n+\t\telse\n+\t\t\tp_info->offload_tc = tc;\n+\t}\n+}\n+\n+void\n+ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,\n+\t\t      struct ecore_hw_info *p_info,\n+\t\t      bool enable, bool update, u8 prio, u8 tc,\n+\t\t      enum dcbx_protocol_type type,\n+\t\t      enum ecore_pci_personality personality)\n+{\n+\t/* PF update ramrod data */\n+\tp_data->arr[type].update = update;\n+\tp_data->arr[type].enable = enable;\n+\tp_data->arr[type].priority = prio;\n+\tp_data->arr[type].tc = tc;\n+\n+\tecore_dcbx_set_pf_tcs(p_info, tc, personality);\n+}\n+\n+/* Update app protocol data and hw_info fields with the TLV info */\n+static void\n+ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,\n+\t\t\t   struct ecore_hwfn *p_hwfn,\n+\t\t\t   bool enable, bool update, u8 prio, u8 tc,\n+\t\t\t   enum dcbx_protocol_type type)\n+{\n+\tstruct ecore_hw_info *p_info = &p_hwfn->hw_info;\n+\tenum ecore_pci_personality personality;\n+\tenum dcbx_protocol_type id;\n+\tconst char *name;\t/* @DPDK */\n+\tu8 size;\n+\tint i;\n+\n+\tsize = OSAL_ARRAY_SIZE(ecore_dcbx_app_update);\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tid = ecore_dcbx_app_update[i].id;\n+\n+\t\tif (type != id)\n+\t\t\tcontinue;\n+\n+\t\tpersonality = ecore_dcbx_app_update[i].personality;\n+\t\tname = ecore_dcbx_app_update[i].name;\n+\n+\t\tecore_dcbx_set_params(p_data, p_info, enable, update,\n+\t\t\t\t      prio, tc, type, personality);\n+\t}\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)\n+{\n+\tu32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES;\n+\tu32 index = ECORE_MAX_PFC_PRIORITIES - 1;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\t/* Bitmap 1 corresponds to priority 0, return priority 0 */\n+\tif (pri_bitmap == 1) {\n+\t\t*priority = 0;\n+\t\treturn rc;\n+\t}\n+\n+\t/* Choose the highest priority */\n+\twhile ((pri == ECORE_MAX_PFC_PRIORITIES) && index) {\n+\t\tpri_mask = 1 << index;\n+\t\tif (pri_bitmap & pri_mask)\n+\t\t\tpri = index;\n+\t\tindex--;\n+\t}\n+\n+\tif (pri < ECORE_MAX_PFC_PRIORITIES)\n+\t\t*priority = (u8)pri;\n+\telse\n+\t\trc = ECORE_INVAL;\n+\n+\treturn rc;\n+}\n+\n+static bool\n+ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t u32 app_prio_bitmap, u16 id, int *type)\n+{\n+\tbool status = false;\n+\n+\tif (ecore_dcbx_default_tlv(app_prio_bitmap, id)) {\n+\t\t*type = DCBX_PROTOCOL_ETH;\n+\t\tstatus = true;\n+\t} else {\n+\t\tDP_ERR(p_hwfn, \"Unsupported protocol %d\\n\", id);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/*  Parse app TLV's to update TC information in hw_info structure for\n+ * reconfiguring QM. Get protocol specific data for PF update ramrod command.\n+ */\n+static enum _ecore_status_t\n+ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,\n+\t\t       struct ecore_dcbx_results *p_data,\n+\t\t       struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl,\n+\t\t       int count, bool dcbx_enabled)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu8 tc, priority, priority_map;\n+\tint i, type = -1;\n+\tu16 protocol_id;\n+\tbool enable;\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB, \"Num APP entries = %d\\n\", count);\n+\n+\t/* Parse APP TLV */\n+\tfor (i = 0; i < count; i++) {\n+\t\tprotocol_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,\n+\t\t\t\t\t\t  DCBX_APP_PROTOCOL_ID);\n+\t\tpriority_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry,\n+\t\t\t\t\t\t   DCBX_APP_PRI_MAP);\n+\t\trc = ecore_dcbx_get_app_priority(priority_map, &priority);\n+\t\tif (rc == ECORE_INVAL) {\n+\t\t\tDP_ERR(p_hwfn, \"Invalid priority\\n\");\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\ttc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority);\n+\t\tif (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,\n+\t\t\t\t\t\t     protocol_id, &type)) {\n+\t\t\t/* ETH always have the enable bit reset, as it gets\n+\t\t\t * vlan information per packet. For other protocols,\n+\t\t\t * should be set according to the dcbx_enabled\n+\t\t\t * indication, but we only got here if there was an\n+\t\t\t * app tlv for the protocol, so dcbx must be enabled.\n+\t\t\t */\n+\t\t\tenable = (type == DCBX_PROTOCOL_ETH ? false : true);\n+\n+\t\t\tecore_dcbx_update_app_info(p_data, p_hwfn, enable, true,\n+\t\t\t\t\t\t   priority, tc, type);\n+\t\t}\n+\t}\n+\t/* Update ramrod protocol data and hw_info fields\n+\t * with default info when corresponding APP TLV's are not detected.\n+\t * The enabled field has a different logic for ethernet as only for\n+\t * ethernet dcb should disabled by default, as the information arrives\n+\t * from the OS (unless an explicit app tlv was present).\n+\t */\n+\ttc = p_data->arr[DCBX_PROTOCOL_ETH].tc;\n+\tpriority = p_data->arr[DCBX_PROTOCOL_ETH].priority;\n+\tfor (type = 0; type < DCBX_MAX_PROTOCOL_TYPE; type++) {\n+\t\tif (p_data->arr[type].update)\n+\t\t\tcontinue;\n+\n+\t\tenable = (type == DCBX_PROTOCOL_ETH) ? false : dcbx_enabled;\n+\t\tecore_dcbx_update_app_info(p_data, p_hwfn, enable, true,\n+\t\t\t\t\t   priority, tc, type);\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+/* Parse app TLV's to update TC information in hw_info structure for\n+ * reconfiguring QM. Get protocol specific data for PF update ramrod command.\n+ */\n+static enum _ecore_status_t\n+ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct dcbx_app_priority_feature *p_app;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tstruct ecore_dcbx_results data = { 0 };\n+\tstruct dcbx_app_priority_entry *p_tbl;\n+\tstruct dcbx_ets_feature *p_ets;\n+\tstruct ecore_hw_info *p_info;\n+\tu32 pri_tc_tbl, flags;\n+\tbool dcbx_enabled;\n+\tint num_entries;\n+\n+\t/* If DCBx version is non zero, then negotiation was\n+\t * successfuly performed\n+\t */\n+\tflags = p_hwfn->p_dcbx_info->operational.flags;\n+\tdcbx_enabled = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) != 0;\n+\n+\tp_app = &p_hwfn->p_dcbx_info->operational.features.app;\n+\tp_tbl = p_app->app_pri_tbl;\n+\n+\tp_ets = &p_hwfn->p_dcbx_info->operational.features.ets;\n+\tpri_tc_tbl = p_ets->pri_tc_tbl[0];\n+\n+\tp_info = &p_hwfn->hw_info;\n+\tnum_entries = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);\n+\n+\trc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl,\n+\t\t\t\t    num_entries, dcbx_enabled);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tp_info->num_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS);\n+\tdata.pf_id = p_hwfn->rel_pf_id;\n+\tdata.dcbx_enabled = dcbx_enabled;\n+\n+\tecore_dcbx_dp_protocol(p_hwfn, &data);\n+\n+\tOSAL_MEMCPY(&p_hwfn->p_dcbx_info->results, &data,\n+\t\t    sizeof(struct ecore_dcbx_results));\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_copy_mib(struct ecore_hwfn *p_hwfn,\n+\t\t    struct ecore_ptt *p_ptt,\n+\t\t    struct ecore_dcbx_mib_meta_data *p_data,\n+\t\t    enum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu32 prefix_seq_num, suffix_seq_num;\n+\tint read_count = 0;\n+\n+\tdo {\n+\t\tif (type == ECORE_DCBX_REMOTE_LLDP_MIB) {\n+\t\t\tecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_remote,\n+\t\t\t\t\t  p_data->addr, p_data->size);\n+\t\t\tprefix_seq_num = p_data->lldp_remote->prefix_seq_num;\n+\t\t\tsuffix_seq_num = p_data->lldp_remote->suffix_seq_num;\n+\t\t} else {\n+\t\t\tecore_memcpy_from(p_hwfn, p_ptt, p_data->mib,\n+\t\t\t\t\t  p_data->addr, p_data->size);\n+\t\t\tprefix_seq_num = p_data->mib->prefix_seq_num;\n+\t\t\tsuffix_seq_num = p_data->mib->suffix_seq_num;\n+\t\t}\n+\t\tread_count++;\n+\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t\t   \"mib type = %d, try count = %d prefix seq num  = %d suffix seq num = %d\\n\",\n+\t\t\t   type, read_count, prefix_seq_num, suffix_seq_num);\n+\t} while ((prefix_seq_num != suffix_seq_num) &&\n+\t\t (read_count < ECORE_DCBX_MAX_MIB_READ_TRY));\n+\n+\tif (read_count >= ECORE_DCBX_MAX_MIB_READ_TRY) {\n+\t\tDP_ERR(p_hwfn,\n+\t\t       \"MIB read err, mib type = %d, try count = %d prefix seq num = %d suffix seq num = %d\\n\",\n+\t\t       type, read_count, prefix_seq_num, suffix_seq_num);\n+\t\trc = ECORE_IO;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_priority_info(struct ecore_hwfn *p_hwfn,\n+\t\t\t     struct ecore_dcbx_app_prio *p_prio,\n+\t\t\t     struct ecore_dcbx_results *p_results)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tif (p_results->arr[DCBX_PROTOCOL_ETH].update &&\n+\t    p_results->arr[DCBX_PROTOCOL_ETH].enable) {\n+\t\tp_prio->eth = p_results->arr[DCBX_PROTOCOL_ETH].priority;\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t\t   \"Priority: eth %d\\n\", p_prio->eth);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static void\n+ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn,\n+\t\t\tstruct dcbx_app_priority_feature *p_app,\n+\t\t\tstruct dcbx_app_priority_entry *p_tbl,\n+\t\t\tstruct ecore_dcbx_params *p_params)\n+{\n+\tint i;\n+\n+\tp_params->app_willing = ECORE_MFW_GET_FIELD(p_app->flags,\n+\t\t\t\t\t\t    DCBX_APP_WILLING);\n+\tp_params->app_valid = ECORE_MFW_GET_FIELD(p_app->flags,\n+\t\t\t\t\t\t  DCBX_APP_ENABLED);\n+\tp_params->num_app_entries = ECORE_MFW_GET_FIELD(p_app->flags,\n+\t\t\t\t\t\t\tDCBX_APP_ENABLED);\n+\tfor (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++)\n+\t\tp_params->app_bitmap[i] = p_tbl[i].entry;\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t   \"APP params: willing %d, valid %d\\n\",\n+\t\t   p_params->app_willing, p_params->app_valid);\n+}\n+\n+static void\n+ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn,\n+\t\t\tu32 pfc, struct ecore_dcbx_params *p_params)\n+{\n+\tp_params->pfc_willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);\n+\tp_params->max_pfc_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);\n+\tp_params->pfc_enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);\n+\tp_params->pfc_bitmap = pfc;\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t   \"PFC params: willing %d, pfc_bitmap %d\\n\",\n+\t\t   p_params->pfc_willing, p_params->pfc_bitmap);\n+}\n+\n+static void\n+ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn,\n+\t\t\tstruct dcbx_ets_feature *p_ets,\n+\t\t\tstruct ecore_dcbx_params *p_params)\n+{\n+\tint i;\n+\n+\tp_params->ets_willing = ECORE_MFW_GET_FIELD(p_ets->flags,\n+\t\t\t\t\t\t    DCBX_ETS_WILLING);\n+\tp_params->ets_enabled = ECORE_MFW_GET_FIELD(p_ets->flags,\n+\t\t\t\t\t\t    DCBX_ETS_ENABLED);\n+\tp_params->max_ets_tc = ECORE_MFW_GET_FIELD(p_ets->flags,\n+\t\t\t\t\t\t   DCBX_ETS_MAX_TCS);\n+\tp_params->ets_pri_tc_tbl[0] = p_ets->pri_tc_tbl[0];\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t   \"ETS params: willing %d, pri_tc_tbl_0 %x max_ets_tc %d\\n\",\n+\t\t   p_params->ets_willing, p_params->ets_pri_tc_tbl[0],\n+\t\t   p_params->max_ets_tc);\n+\n+\t/* 8 bit tsa and bw data corresponding to each of the 8 TC's are\n+\t * encoded in a type u32 array of size 2.\n+\t */\n+\tfor (i = 0; i < 2; i++) {\n+\t\tp_params->ets_tc_tsa_tbl[i] = p_ets->tc_tsa_tbl[i];\n+\t\tp_params->ets_tc_bw_tbl[i] = p_ets->tc_bw_tbl[i];\n+\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t\t   \"elem %d  bw_tbl %x tsa_tbl %x\\n\",\n+\t\t\t   i, p_params->ets_tc_bw_tbl[i],\n+\t\t\t   p_params->ets_tc_tsa_tbl[i]);\n+\t}\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t     struct dcbx_app_priority_feature *p_app,\n+\t\t\t     struct dcbx_app_priority_entry *p_tbl,\n+\t\t\t     struct dcbx_ets_feature *p_ets,\n+\t\t\t     u32 pfc, struct ecore_dcbx_params *p_params)\n+{\n+\tecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params);\n+\tecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params);\n+\tecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t    struct ecore_ptt *p_ptt,\n+\t\t\t    struct ecore_dcbx_get *params)\n+{\n+\tstruct ecore_dcbx_admin_params *p_local;\n+\tstruct dcbx_app_priority_feature *p_app;\n+\tstruct dcbx_app_priority_entry *p_tbl;\n+\tstruct ecore_dcbx_params *p_data;\n+\tstruct dcbx_ets_feature *p_ets;\n+\tu32 pfc;\n+\n+\tp_local = &params->local;\n+\tp_data = &p_local->params;\n+\tp_app = &p_hwfn->p_dcbx_info->local_admin.features.app;\n+\tp_tbl = p_app->app_pri_tbl;\n+\tp_ets = &p_hwfn->p_dcbx_info->local_admin.features.ets;\n+\tpfc = p_hwfn->p_dcbx_info->local_admin.features.pfc;\n+\n+\tecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);\n+\tp_local->valid = true;\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t     struct ecore_ptt *p_ptt,\n+\t\t\t     struct ecore_dcbx_get *params)\n+{\n+\tstruct ecore_dcbx_remote_params *p_remote;\n+\tstruct dcbx_app_priority_feature *p_app;\n+\tstruct dcbx_app_priority_entry *p_tbl;\n+\tstruct ecore_dcbx_params *p_data;\n+\tstruct dcbx_ets_feature *p_ets;\n+\tu32 pfc;\n+\n+\tp_remote = &params->remote;\n+\tp_data = &p_remote->params;\n+\tp_app = &p_hwfn->p_dcbx_info->remote.features.app;\n+\tp_tbl = p_app->app_pri_tbl;\n+\tp_ets = &p_hwfn->p_dcbx_info->remote.features.ets;\n+\tpfc = p_hwfn->p_dcbx_info->remote.features.pfc;\n+\n+\tecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);\n+\tp_remote->valid = true;\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t  struct ecore_dcbx_get *params)\n+{\n+\tstruct ecore_dcbx_operational_params *p_operational;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tstruct dcbx_app_priority_feature *p_app;\n+\tstruct dcbx_app_priority_entry *p_tbl;\n+\tstruct ecore_dcbx_results *p_results;\n+\tstruct ecore_dcbx_params *p_data;\n+\tstruct dcbx_ets_feature *p_ets;\n+\tbool enabled, err;\n+\tu32 pfc, flags;\n+\n+\tflags = p_hwfn->p_dcbx_info->operational.flags;\n+\n+\t/* If DCBx version is non zero, then negotiation\n+\t * was successfuly performed\n+\t */\n+\tp_operational = &params->operational;\n+\tenabled = ecore_dcbx_enabled(flags);\n+\tif (!enabled) {\n+\t\tp_operational->enabled = enabled;\n+\t\tp_operational->valid = false;\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\tp_data = &p_operational->params;\n+\tp_results = &p_hwfn->p_dcbx_info->results;\n+\tp_app = &p_hwfn->p_dcbx_info->operational.features.app;\n+\tp_tbl = p_app->app_pri_tbl;\n+\tp_ets = &p_hwfn->p_dcbx_info->operational.features.ets;\n+\tpfc = p_hwfn->p_dcbx_info->operational.features.pfc;\n+\n+\tp_operational->ieee = ecore_dcbx_ieee(flags);\n+\tp_operational->cee = ecore_dcbx_cee(flags);\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t   \"Version support: ieee %d, cee %d\\n\",\n+\t\t   p_operational->ieee, p_operational->cee);\n+\n+\tecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);\n+\tecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio,\n+\t\t\t\t     p_results);\n+\terr = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);\n+\tp_operational->err = err;\n+\tp_operational->enabled = enabled;\n+\tp_operational->valid = true;\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t struct ecore_dcbx_get *params)\n+{\n+\tstruct ecore_dcbx_lldp_local *p_local;\n+\tosal_size_t size;\n+\tu32 *dest;\n+\n+\tp_local = &params->lldp_local;\n+\n+\tsize = OSAL_ARRAY_SIZE(p_local->local_chassis_id);\n+\tdest = p_hwfn->p_dcbx_info->get.lldp_local.local_chassis_id;\n+\tOSAL_MEMCPY(dest, p_local->local_chassis_id, size);\n+\n+\tsize = OSAL_ARRAY_SIZE(p_local->local_port_id);\n+\tdest = p_hwfn->p_dcbx_info->get.lldp_local.local_port_id;\n+\tOSAL_MEMCPY(dest, p_local->local_port_id, size);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_remote_lldp_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t  struct ecore_dcbx_get *params)\n+{\n+\tstruct ecore_dcbx_lldp_remote *p_remote;\n+\tosal_size_t size;\n+\tu32 *dest;\n+\n+\tp_remote = &params->lldp_remote;\n+\n+\tsize = OSAL_ARRAY_SIZE(p_remote->peer_chassis_id);\n+\tdest = p_hwfn->p_dcbx_info->get.lldp_remote.peer_chassis_id;\n+\tOSAL_MEMCPY(dest, p_remote->peer_chassis_id, size);\n+\n+\tsize = OSAL_ARRAY_SIZE(p_remote->peer_port_id);\n+\tdest = p_hwfn->p_dcbx_info->get.lldp_remote.peer_port_id;\n+\tOSAL_MEMCPY(dest, p_remote->peer_port_id, size);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_get_params(struct ecore_hwfn *p_hwfn,\n+\t\t      struct ecore_ptt *p_ptt, enum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tstruct ecore_dcbx_get *p_params;\n+\n+\tp_params = &p_hwfn->p_dcbx_info->get;\n+\n+\tswitch (type) {\n+\tcase ECORE_DCBX_REMOTE_MIB:\n+\t\tecore_dcbx_get_remote_params(p_hwfn, p_ptt, p_params);\n+\t\tbreak;\n+\tcase ECORE_DCBX_LOCAL_MIB:\n+\t\tecore_dcbx_get_local_params(p_hwfn, p_ptt, p_params);\n+\t\tbreak;\n+\tcase ECORE_DCBX_OPERATIONAL_MIB:\n+\t\tecore_dcbx_get_operational_params(p_hwfn, p_ptt, p_params);\n+\t\tbreak;\n+\tcase ECORE_DCBX_REMOTE_LLDP_MIB:\n+\t\trc = ecore_dcbx_get_remote_lldp_params(p_hwfn, p_ptt, p_params);\n+\t\tbreak;\n+\tcase ECORE_DCBX_LOCAL_LLDP_MIB:\n+\t\trc = ecore_dcbx_get_local_lldp_params(p_hwfn, p_ptt, p_params);\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_ERR(p_hwfn, \"MIB read err, unknown mib type %d\\n\", type);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_read_local_lldp_mib(struct ecore_hwfn *p_hwfn,\n+\t\t\t       struct ecore_ptt *p_ptt)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tstruct ecore_dcbx_mib_meta_data data;\n+\n+\tdata.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,\n+\t\t\t\t\t\t\t   lldp_config_params);\n+\tdata.lldp_local = p_hwfn->p_dcbx_info->lldp_local;\n+\tdata.size = sizeof(struct lldp_config_params_s);\n+\tecore_memcpy_from(p_hwfn, p_ptt, data.lldp_local, data.addr, data.size);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn,\n+\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\tenum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tstruct ecore_dcbx_mib_meta_data data;\n+\n+\tdata.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,\n+\t\t\t\t\t\t\t   lldp_status_params);\n+\tdata.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote;\n+\tdata.size = sizeof(struct lldp_status_params_s);\n+\trc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn,\n+\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\tenum ecore_mib_read_type type)\n+{\n+\tstruct ecore_dcbx_mib_meta_data data;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tdata.addr = p_hwfn->mcp_info->port_addr +\n+\t    offsetof(struct public_port, operational_dcbx_mib);\n+\tdata.mib = &p_hwfn->p_dcbx_info->operational;\n+\tdata.size = sizeof(struct dcbx_mib);\n+\trc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn,\n+\t\t\t   struct ecore_ptt *p_ptt,\n+\t\t\t   enum ecore_mib_read_type type)\n+{\n+\tstruct ecore_dcbx_mib_meta_data data;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tdata.addr = p_hwfn->mcp_info->port_addr +\n+\t    offsetof(struct public_port, remote_dcbx_mib);\n+\tdata.mib = &p_hwfn->p_dcbx_info->remote;\n+\tdata.size = sizeof(struct dcbx_mib);\n+\trc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)\n+{\n+\tstruct ecore_dcbx_mib_meta_data data;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tdata.addr = p_hwfn->mcp_info->port_addr +\n+\t    offsetof(struct public_port, local_admin_dcbx_mib);\n+\tdata.local_admin = &p_hwfn->p_dcbx_info->local_admin;\n+\tdata.size = sizeof(struct dcbx_local_params);\n+\tecore_memcpy_from(p_hwfn, p_ptt, data.local_admin,\n+\t\t\t  data.addr, data.size);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\t\t\tenum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tswitch (type) {\n+\tcase ECORE_DCBX_OPERATIONAL_MIB:\n+\t\trc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type);\n+\t\tbreak;\n+\tcase ECORE_DCBX_REMOTE_MIB:\n+\t\trc = ecore_dcbx_read_remote_mib(p_hwfn, p_ptt, type);\n+\t\tbreak;\n+\tcase ECORE_DCBX_LOCAL_MIB:\n+\t\trc = ecore_dcbx_read_local_mib(p_hwfn, p_ptt);\n+\t\tbreak;\n+\tcase ECORE_DCBX_REMOTE_LLDP_MIB:\n+\t\trc = ecore_dcbx_read_remote_lldp_mib(p_hwfn, p_ptt, type);\n+\t\tbreak;\n+\tcase ECORE_DCBX_LOCAL_LLDP_MIB:\n+\t\trc = ecore_dcbx_read_local_lldp_mib(p_hwfn, p_ptt);\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_ERR(p_hwfn, \"MIB read err, unknown mib type %d\\n\", type);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+/*\n+ * Read updated MIB.\n+ * Reconfigure QM and invoke PF update ramrod command if operational MIB\n+ * change is detected.\n+ */\n+enum _ecore_status_t\n+ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t\t    enum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\trc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (type == ECORE_DCBX_OPERATIONAL_MIB) {\n+\t\trc = ecore_dcbx_process_mib_info(p_hwfn);\n+\t\tif (!rc) {\n+\t\t\tbool enabled;\n+\n+\t\t\t/* reconfigure tcs of QM queues according\n+\t\t\t * to negotiation results\n+\t\t\t */\n+\t\t\tecore_qm_reconf(p_hwfn, p_ptt);\n+\n+\t\t\t/* update storm FW with negotiation results */\n+\t\t\tecore_sp_pf_update(p_hwfn);\n+\n+\t\t\t/* set eagle enigne 1 flow control workaround\n+\t\t\t * according to negotiation results\n+\t\t\t */\n+\t\t\tenabled = p_hwfn->p_dcbx_info->results.dcbx_enabled;\n+\t\t\tecore_dcbx_eagle_workaround(p_hwfn, p_ptt, enabled);\n+\t\t}\n+\t}\n+\tecore_dcbx_get_params(p_hwfn, p_ptt, type);\n+\tOSAL_DCBX_AEN(p_hwfn, type);\n+\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn)\n+{\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tp_hwfn->p_dcbx_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,\n+\t\t\t\t\t  sizeof(struct ecore_dcbx_info));\n+\tif (!p_hwfn->p_dcbx_info) {\n+\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\t  \"Failed to allocate `struct ecore_dcbx_info'\");\n+\t\trc = ECORE_NOMEM;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void ecore_dcbx_info_free(struct ecore_hwfn *p_hwfn,\n+\t\t\t  struct ecore_dcbx_info *p_dcbx_info)\n+{\n+\tOSAL_FREE(p_hwfn->p_dev, p_hwfn->p_dcbx_info);\n+}\n+\n+static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data,\n+\t\t\t\t\t    struct ecore_dcbx_results *p_src,\n+\t\t\t\t\t    enum dcbx_protocol_type type)\n+{\n+\tp_data->dcb_enable_flag = p_src->arr[type].enable;\n+\tp_data->dcb_priority = p_src->arr[type].priority;\n+\tp_data->dcb_tc = p_src->arr[type].tc;\n+}\n+\n+/* Set pf update ramrod command params */\n+void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,\n+\t\t\t\t     struct pf_update_ramrod_data *p_dest)\n+{\n+\tstruct protocol_dcb_data *p_dcb_data;\n+\tbool update_flag;\n+\n+\tp_dest->pf_id = p_src->pf_id;\n+\n+\tupdate_flag = p_src->arr[DCBX_PROTOCOL_ETH].update;\n+\tp_dest->update_eth_dcb_data_flag = update_flag;\n+\n+\tp_dcb_data = &p_dest->eth_dcb_data;\n+\tecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH);\n+}\n+\n+static\n+enum _ecore_status_t ecore_dcbx_query(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t      enum ecore_mib_read_type type)\n+{\n+\tstruct ecore_ptt *p_ptt;\n+\tenum _ecore_status_t rc;\n+\n+\tp_ptt = ecore_ptt_acquire(p_hwfn);\n+\tif (!p_ptt) {\n+\t\trc = ECORE_TIMEOUT;\n+\t\tDP_ERR(p_hwfn, \"rc = %d\\n\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto out;\n+\n+\trc = ecore_dcbx_get_params(p_hwfn, p_ptt, type);\n+\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t     struct ecore_dcbx_get *p_get,\n+\t\t\t\t\t     enum ecore_mib_read_type type)\n+{\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_dcbx_query(p_hwfn, type);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (p_get != OSAL_NULL)\n+\t\tOSAL_MEMCPY(p_get, &p_hwfn->p_dcbx_info->get,\n+\t\t\t    sizeof(struct ecore_dcbx_get));\n+\n+\treturn rc;\n+}\ndiff --git a/drivers/net/qede/base/ecore_dcbx.h b/drivers/net/qede/base/ecore_dcbx.h\nnew file mode 100644\nindex 0000000..d577f4e\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_dcbx.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#ifndef __ECORE_DCBX_H__\n+#define __ECORE_DCBX_H__\n+\n+#include \"ecore.h\"\n+#include \"ecore_mcp.h\"\n+#include \"mcp_public.h\"\n+#include \"reg_addr.h\"\n+#include \"ecore_hw.h\"\n+#include \"ecore_hsi_common.h\"\n+#include \"ecore_dcbx_api.h\"\n+\n+#define ECORE_MFW_GET_FIELD(name, field) \\\n+\t(((name) & (field ## _MASK)) >> (field ## _SHIFT))\n+\n+struct ecore_dcbx_info {\n+\tstruct lldp_status_params_s lldp_remote[LLDP_MAX_LLDP_AGENTS];\n+\tstruct lldp_config_params_s lldp_local[LLDP_MAX_LLDP_AGENTS];\n+\tstruct dcbx_local_params local_admin;\n+\tstruct ecore_dcbx_results results;\n+\tstruct dcbx_mib operational;\n+\tstruct dcbx_mib remote;\n+\tstruct ecore_dcbx_set set;\n+\tstruct ecore_dcbx_get get;\n+\tu8 dcbx_cap;\n+};\n+\n+/* Upper layer driver interface routines */\n+enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *,\n+\t\t\t\t\t      struct ecore_ptt *,\n+\t\t\t\t\t      struct ecore_dcbx_set *);\n+\n+/* ECORE local interface routines */\n+enum _ecore_status_t\n+ecore_dcbx_mib_update_event(struct ecore_hwfn *, struct ecore_ptt *,\n+\t\t\t    enum ecore_mib_read_type);\n+\n+enum _ecore_status_t ecore_dcbx_read_lldp_params(struct ecore_hwfn *,\n+\t\t\t\t\t\t struct ecore_ptt *);\n+enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn);\n+void ecore_dcbx_info_free(struct ecore_hwfn *, struct ecore_dcbx_info *);\n+void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,\n+\t\t\t\t     struct pf_update_ramrod_data *p_dest);\n+/* @@@TBD eagle phy workaround */\n+void ecore_dcbx_eagle_workaround(struct ecore_hwfn *, struct ecore_ptt *,\n+\t\t\t\t bool set_to_pfc);\n+\n+#endif /* __ECORE_DCBX_H__ */\ndiff --git a/drivers/net/qede/base/ecore_dcbx_api.h b/drivers/net/qede/base/ecore_dcbx_api.h\nnew file mode 100644\nindex 0000000..1deddd6\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_dcbx_api.h\n@@ -0,0 +1,160 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#ifndef __ECORE_DCBX_API_H__\n+#define __ECORE_DCBX_API_H__\n+\n+#include \"ecore.h\"\n+\n+#define DCBX_CONFIG_MAX_APP_PROTOCOL\t4\n+\n+enum ecore_mib_read_type {\n+\tECORE_DCBX_OPERATIONAL_MIB,\n+\tECORE_DCBX_REMOTE_MIB,\n+\tECORE_DCBX_LOCAL_MIB,\n+\tECORE_DCBX_REMOTE_LLDP_MIB,\n+\tECORE_DCBX_LOCAL_LLDP_MIB\n+};\n+\n+struct ecore_dcbx_app_data {\n+\tbool enable;\t\t/* DCB enabled */\n+\tbool update;\t\t/* Update indication */\n+\tu8 priority;\t\t/* Priority */\n+\tu8 tc;\t\t\t/* Traffic Class */\n+};\n+\n+#ifndef __EXTRACT__LINUX__\n+enum dcbx_protocol_type {\n+\tDCBX_PROTOCOL_ETH,\n+\tDCBX_MAX_PROTOCOL_TYPE\n+};\n+\n+#ifdef LINUX_REMOVE\n+/* We can't assume THE HSI values are avaiable to clients, so we need\n+ * to redefine those here.\n+ */\n+#ifndef LLDP_CHASSIS_ID_STAT_LEN\n+#define LLDP_CHASSIS_ID_STAT_LEN 4\n+#endif\n+#ifndef LLDP_PORT_ID_STAT_LEN\n+#define LLDP_PORT_ID_STAT_LEN 4\n+#endif\n+#ifndef DCBX_MAX_APP_PROTOCOL\n+#define DCBX_MAX_APP_PROTOCOL 32\n+#endif\n+\n+#endif\n+\n+struct ecore_dcbx_lldp_remote {\n+\tu32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n+\tu32 peer_port_id[LLDP_PORT_ID_STAT_LEN];\n+\tbool enable_rx;\n+\tbool enable_tx;\n+\tu32 tx_interval;\n+\tu32 max_credit;\n+};\n+\n+struct ecore_dcbx_lldp_local {\n+\tu32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n+\tu32 local_port_id[LLDP_PORT_ID_STAT_LEN];\n+};\n+\n+struct ecore_dcbx_app_prio {\n+\tu8 eth;\n+};\n+\n+struct ecore_dcbx_params {\n+\tu32 app_bitmap[DCBX_MAX_APP_PROTOCOL];\n+\tu16 num_app_entries;\n+\tbool app_willing;\n+\tbool app_valid;\n+\tbool ets_willing;\n+\tbool ets_enabled;\n+\tbool valid;\t\t/* Indicate validity of params */\n+\tu32 ets_pri_tc_tbl[1];\n+\tu32 ets_tc_bw_tbl[2];\n+\tu32 ets_tc_tsa_tbl[2];\n+\tbool pfc_willing;\n+\tbool pfc_enabled;\n+\tu32 pfc_bitmap;\n+\tu8 max_pfc_tc;\n+\tu8 max_ets_tc;\n+};\n+\n+struct ecore_dcbx_admin_params {\n+\tstruct ecore_dcbx_params params;\n+\tbool valid;\t\t/* Indicate validity of params */\n+};\n+\n+struct ecore_dcbx_remote_params {\n+\tstruct ecore_dcbx_params params;\n+\tbool valid;\t\t/* Indicate validity of params */\n+};\n+\n+struct ecore_dcbx_operational_params {\n+\tstruct ecore_dcbx_app_prio app_prio;\n+\tstruct ecore_dcbx_params params;\n+\tbool valid;\t\t/* Indicate validity of params */\n+\tbool enabled;\n+\tbool ieee;\n+\tbool cee;\n+\tu32 err;\n+};\n+\n+struct ecore_dcbx_get {\n+\tstruct ecore_dcbx_operational_params operational;\n+\tstruct ecore_dcbx_lldp_remote lldp_remote;\n+\tstruct ecore_dcbx_lldp_local lldp_local;\n+\tstruct ecore_dcbx_remote_params remote;\n+\tstruct ecore_dcbx_admin_params local;\n+};\n+#endif\n+\n+struct ecore_dcbx_set {\n+\tstruct ecore_dcbx_admin_params config;\n+\tbool enabled;\n+\tu32 ver_num;\n+};\n+\n+struct ecore_dcbx_results {\n+\tbool dcbx_enabled;\n+\tu8 pf_id;\n+\tstruct ecore_dcbx_app_data arr[DCBX_MAX_PROTOCOL_TYPE];\n+};\n+\n+struct ecore_dcbx_app_metadata {\n+\tenum dcbx_protocol_type id;\n+\tconst char *name;\t/* @DPDK */\n+\tenum ecore_pci_personality personality;\n+};\n+\n+struct ecore_dcbx_mib_meta_data {\n+\tstruct lldp_config_params_s *lldp_local;\n+\tstruct lldp_status_params_s *lldp_remote;\n+\tstruct dcbx_local_params *local_admin;\n+\tstruct dcbx_mib *mib;\n+\tosal_size_t size;\n+\tu32 addr;\n+};\n+\n+void\n+ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,\n+\t\t      struct ecore_hw_info *p_info,\n+\t\t      bool enable, bool update, u8 prio, u8 tc,\n+\t\t      enum dcbx_protocol_type type,\n+\t\t      enum ecore_pci_personality personality);\n+\n+enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *,\n+\t\t\t\t\t     struct ecore_dcbx_get *,\n+\t\t\t\t\t     enum ecore_mib_read_type);\n+\n+static const struct ecore_dcbx_app_metadata ecore_dcbx_app_update[] = {\n+\t{DCBX_PROTOCOL_ETH, \"ETH\", ECORE_PCI_ETH}\n+};\n+\n+#endif /* __ECORE_DCBX_API_H__ */\ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex e68f60b..38476ee 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -30,6 +30,7 @@\n #include \"nvm_cfg.h\"\n #include \"ecore_dev_api.h\"\n #include \"ecore_attn_values.h\"\n+#include \"ecore_dcbx.h\"\n \n /* Configurable */\n #define ECORE_MIN_DPIS\t\t(4)\t/* The minimal number of DPIs required\n@@ -157,6 +158,7 @@ void ecore_resc_free(struct ecore_dev *p_dev)\n \t\tecore_int_free(p_hwfn);\n \t\tecore_iov_free(p_hwfn);\n \t\tecore_dmae_info_free(p_hwfn);\n+\t\tecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);\n \t\t/* @@@TBD Flush work-queue ? */\n \t}\n }\n@@ -279,6 +281,9 @@ static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,\n \tfor (i = 0; i < num_ports; i++) {\n \t\tp_qm_port = &qm_info->qm_port_params[i];\n \t\tp_qm_port->active = 1;\n+\t\t/* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will\n+\t\t * be in place\n+\t\t */\n \t\tif (num_ports == 4)\n \t\t\tp_qm_port->num_active_phys_tcs = 2;\n \t\telse\n@@ -477,6 +482,14 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n \t\t\t\t  \" dmae_info structure\\n\");\n \t\t\tgoto alloc_err;\n \t\t}\n+\n+\t\t/* DCBX initialization */\n+\t\trc = ecore_dcbx_info_alloc(p_hwfn);\n+\t\tif (rc) {\n+\t\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\t\t  \"Failed to allocate memory for dcbxstruct\\n\");\n+\t\t\tgoto alloc_err;\n+\t\t}\n \t}\n \n \tp_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,\n@@ -1418,6 +1431,20 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\treturn mfw_rc;\n \t\t}\n \n+\t\t/* send DCBX attention request command */\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n+\t\t\t   \"sending phony dcbx set command to trigger DCBx\"\n+\t\t\t   \" attention handling\\n\");\n+\t\tmfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t       DRV_MSG_CODE_SET_DCBX,\n+\t\t\t\t       1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,\n+\t\t\t\t       &load_code, &param);\n+\t\tif (mfw_rc != ECORE_SUCCESS) {\n+\t\t\tDP_NOTICE(p_hwfn, true,\n+\t\t\t\t  \"Failed to send DCBX attention request\\n\");\n+\t\t\treturn mfw_rc;\n+\t\t}\n+\n \t\tp_hwfn->hw_init_done = true;\n \t}\n \ndiff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c\nindex 23ea426..e57155b 100644\n--- a/drivers/net/qede/base/ecore_l2.c\n+++ b/drivers/net/qede/base/ecore_l2.c\n@@ -1419,9 +1419,6 @@ enum _ecore_status_t ecore_sp_vf_start(struct ecore_hwfn *p_hwfn,\n \tcase ECORE_PCI_ETH:\n \t\tp_ramrod->personality = PERSONALITY_ETH;\n \t\tbreak;\n-\tcase ECORE_PCI_ETH_ROCE:\n-\t\tp_ramrod->personality = PERSONALITY_RDMA_AND_ETH;\n-\t\tbreak;\n \tdefault:\n \t\tDP_NOTICE(p_hwfn, true, \"Unkown VF personality %d\\n\",\n \t\t\t  p_hwfn->hw_info.personality);\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 7dff695..db41ee0 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -18,6 +18,7 @@\n #include \"ecore_iov_api.h\"\n #include \"ecore_gtt_reg_addr.h\"\n #include \"ecore_iro.h\"\n+#include \"ecore_dcbx.h\"\n \n #define CHIP_MCP_RESP_ITER_US 10\n #define EMUL_MCP_RESP_ITER_US (1000 * 1000)\n@@ -726,6 +727,9 @@ static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,\n \n \tp_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);\n \n+\tif (p_link->link_up)\n+\t\tecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);\n+\n \tOSAL_LINK_UPDATE(p_hwfn);\n }\n \n@@ -998,6 +1002,18 @@ enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,\n \t\tcase MFW_DRV_MSG_VF_DISABLED:\n \t\t\tecore_mcp_handle_vf_flr(p_hwfn, p_ptt);\n \t\t\tbreak;\n+\t\tcase MFW_DRV_MSG_LLDP_DATA_UPDATED:\n+\t\t\tecore_dcbx_mib_update_event(p_hwfn, p_ptt,\n+\t\t\t\t\t\t    ECORE_DCBX_REMOTE_LLDP_MIB);\n+\t\t\tbreak;\n+\t\tcase MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:\n+\t\t\tecore_dcbx_mib_update_event(p_hwfn, p_ptt,\n+\t\t\t\t\t\t    ECORE_DCBX_REMOTE_MIB);\n+\t\t\tbreak;\n+\t\tcase MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:\n+\t\t\tecore_dcbx_mib_update_event(p_hwfn, p_ptt,\n+\t\t\t\t\t\t    ECORE_DCBX_OPERATIONAL_MIB);\n+\t\t\tbreak;\n \t\tcase MFW_DRV_MSG_ERROR_RECOVERY:\n \t\t\tecore_mcp_handle_process_kill(p_hwfn, p_ptt);\n \t\t\tbreak;\ndiff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c\nindex d2c2aae..564a6b2 100644\n--- a/drivers/net/qede/base/ecore_sp_commands.c\n+++ b/drivers/net/qede/base/ecore_sp_commands.c\n@@ -20,6 +20,7 @@\n #include \"reg_addr.h\"\n #include \"ecore_int.h\"\n #include \"ecore_hw.h\"\n+#include \"ecore_dcbx.h\"\n \n enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t   struct ecore_spq_entry **pp_ent,\n@@ -430,6 +431,9 @@ enum _ecore_status_t ecore_sp_pf_update(struct ecore_hwfn *p_hwfn)\n \tif (rc != ECORE_SUCCESS)\n \t\treturn rc;\n \n+\tecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,\n+\t\t\t\t\t&p_ent->ramrod.pf_update);\n+\n \treturn ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);\n }\n \ndiff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h\nindex 07f3673..0e61502 100644\n--- a/drivers/net/qede/base/mcp_public.h\n+++ b/drivers/net/qede/base/mcp_public.h\n@@ -183,6 +183,179 @@ struct couple_mode_teaming {\n #define PORT_CMT_TEAM1              (1 << 2)\n };\n \n+/**************************************\n+ *     LLDP and DCBX HSI structures\n+ **************************************/\n+#define LLDP_CHASSIS_ID_STAT_LEN 4\n+#define LLDP_PORT_ID_STAT_LEN 4\n+#define DCBX_MAX_APP_PROTOCOL\t\t32\n+#define MAX_SYSTEM_LLDP_TLV_DATA    32\n+\n+typedef enum _lldp_agent_e {\n+\tLLDP_NEAREST_BRIDGE = 0,\n+\tLLDP_NEAREST_NON_TPMR_BRIDGE,\n+\tLLDP_NEAREST_CUSTOMER_BRIDGE,\n+\tLLDP_MAX_LLDP_AGENTS\n+} lldp_agent_e;\n+\n+struct lldp_config_params_s {\n+\tu32 config;\n+#define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff\n+#define LLDP_CONFIG_TX_INTERVAL_SHIFT       0\n+#define LLDP_CONFIG_HOLD_MASK               0x00000f00\n+#define LLDP_CONFIG_HOLD_SHIFT              8\n+#define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000\n+#define LLDP_CONFIG_MAX_CREDIT_SHIFT        12\n+#define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000\n+#define LLDP_CONFIG_ENABLE_RX_SHIFT         30\n+#define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000\n+#define LLDP_CONFIG_ENABLE_TX_SHIFT         31\n+\t/* Holds local Chassis ID TLV header, subtype and 9B of payload.\n+\t   If firtst byte is 0, then we will use default chassis ID */\n+\tu32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n+\t/* Holds local Port ID TLV header, subtype and 9B of payload.\n+\t   If firtst byte is 0, then we will use default port ID */\n+\tu32 local_port_id[LLDP_PORT_ID_STAT_LEN];\n+};\n+\n+struct lldp_status_params_s {\n+\tu32 prefix_seq_num;\n+\tu32 status;\t\t/* TBD */\n+\t/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */\n+\tu32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];\n+\t/* Holds remote Port ID TLV header, subtype and 9B of payload. */\n+\tu32 peer_port_id[LLDP_PORT_ID_STAT_LEN];\n+\tu32 suffix_seq_num;\n+};\n+\n+struct dcbx_ets_feature {\n+\tu32 flags;\n+#define DCBX_ETS_ENABLED_MASK                   0x00000001\n+#define DCBX_ETS_ENABLED_SHIFT                  0\n+#define DCBX_ETS_WILLING_MASK                   0x00000002\n+#define DCBX_ETS_WILLING_SHIFT                  1\n+#define DCBX_ETS_ERROR_MASK                     0x00000004\n+#define DCBX_ETS_ERROR_SHIFT                    2\n+#define DCBX_ETS_CBS_MASK                       0x00000008\n+#define DCBX_ETS_CBS_SHIFT                      3\n+#define DCBX_ETS_MAX_TCS_MASK                   0x000000f0\n+#define DCBX_ETS_MAX_TCS_SHIFT                  4\n+\tu32 pri_tc_tbl[1];\n+#define DCBX_CEE_STRICT_PRIORITY\t\t0xf\n+#define DCBX_CEE_STRICT_PRIORITY_TC\t\t0x7\n+\tu32 tc_bw_tbl[2];\n+\tu32 tc_tsa_tbl[2];\n+#define DCBX_ETS_TSA_STRICT\t\t\t0\n+#define DCBX_ETS_TSA_CBS\t\t\t1\n+#define DCBX_ETS_TSA_ETS\t\t\t2\n+};\n+\n+struct dcbx_app_priority_entry {\n+\tu32 entry;\n+#define DCBX_APP_PRI_MAP_MASK       0x000000ff\n+#define DCBX_APP_PRI_MAP_SHIFT      0\n+#define DCBX_APP_PRI_0              0x01\n+#define DCBX_APP_PRI_1              0x02\n+#define DCBX_APP_PRI_2              0x04\n+#define DCBX_APP_PRI_3              0x08\n+#define DCBX_APP_PRI_4              0x10\n+#define DCBX_APP_PRI_5              0x20\n+#define DCBX_APP_PRI_6              0x40\n+#define DCBX_APP_PRI_7              0x80\n+#define DCBX_APP_SF_MASK            0x00000300\n+#define DCBX_APP_SF_SHIFT           8\n+#define DCBX_APP_SF_ETHTYPE         0\n+#define DCBX_APP_SF_PORT            1\n+#define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000\n+#define DCBX_APP_PROTOCOL_ID_SHIFT  16\n+};\n+\n+/* FW structure in BE */\n+struct dcbx_app_priority_feature {\n+\tu32 flags;\n+#define DCBX_APP_ENABLED_MASK           0x00000001\n+#define DCBX_APP_ENABLED_SHIFT          0\n+#define DCBX_APP_WILLING_MASK           0x00000002\n+#define DCBX_APP_WILLING_SHIFT          1\n+#define DCBX_APP_ERROR_MASK             0x00000004\n+#define DCBX_APP_ERROR_SHIFT            2\n+\t/* Not in use\n+\t   #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00\n+\t   #define DCBX_APP_DEFAULT_PRI_SHIFT      8\n+\t */\n+#define DCBX_APP_MAX_TCS_MASK           0x0000f000\n+#define DCBX_APP_MAX_TCS_SHIFT          12\n+#define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000\n+#define DCBX_APP_NUM_ENTRIES_SHIFT      16\n+\tstruct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];\n+};\n+\n+/* FW structure in BE */\n+struct dcbx_features {\n+\t/* PG feature */\n+\tstruct dcbx_ets_feature ets;\n+\t/* PFC feature */\n+\tu32 pfc;\n+#define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff\n+#define DCBX_PFC_PRI_EN_BITMAP_SHIFT            0\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40\n+#define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80\n+\n+#define DCBX_PFC_FLAGS_MASK                     0x0000ff00\n+#define DCBX_PFC_FLAGS_SHIFT                    8\n+#define DCBX_PFC_CAPS_MASK                      0x00000f00\n+#define DCBX_PFC_CAPS_SHIFT                     8\n+#define DCBX_PFC_MBC_MASK                       0x00004000\n+#define DCBX_PFC_MBC_SHIFT                      14\n+#define DCBX_PFC_WILLING_MASK                   0x00008000\n+#define DCBX_PFC_WILLING_SHIFT                  15\n+#define DCBX_PFC_ENABLED_MASK                   0x00010000\n+#define DCBX_PFC_ENABLED_SHIFT                  16\n+#define DCBX_PFC_ERROR_MASK                     0x00020000\n+#define DCBX_PFC_ERROR_SHIFT                    17\n+\n+\t/* APP feature */\n+\tstruct dcbx_app_priority_feature app;\n+};\n+\n+struct dcbx_local_params {\n+\tu32 config;\n+#define DCBX_CONFIG_VERSION_MASK            0x00000003\n+#define DCBX_CONFIG_VERSION_SHIFT           0\n+#define DCBX_CONFIG_VERSION_DISABLED        0\n+#define DCBX_CONFIG_VERSION_IEEE            1\n+#define DCBX_CONFIG_VERSION_CEE             2\n+\n+\tu32 flags;\n+\tstruct dcbx_features features;\n+};\n+\n+struct dcbx_mib {\n+\tu32 prefix_seq_num;\n+\tu32 flags;\n+\t/*\n+\t * #define DCBX_CONFIG_VERSION_MASK            0x00000003\n+\t * #define DCBX_CONFIG_VERSION_SHIFT           0\n+\t * #define DCBX_CONFIG_VERSION_DISABLED        0\n+\t * #define DCBX_CONFIG_VERSION_IEEE            1\n+\t * #define DCBX_CONFIG_VERSION_CEE             2\n+\t */\n+\tstruct dcbx_features features;\n+\tu32 suffix_seq_num;\n+};\n+\n+struct lldp_system_tlvs_buffer_s {\n+\tu16 valid;\n+\tu16 length;\n+\tu32 data[MAX_SYSTEM_LLDP_TLV_DATA];\n+};\n+\n /**************************************/\n /*                                    */\n /*     P U B L I C      G L O B A L   */\n@@ -386,6 +559,16 @@ struct public_port {\n \n \tu32 link_change_count;\n \n+\t/* LLDP params */\n+\tstruct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];\n+\tstruct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];\n+\tstruct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;\n+\n+\t/* DCBX related MIB */\n+\tstruct dcbx_local_params local_admin_dcbx_mib;\n+\tstruct dcbx_mib remote_dcbx_mib;\n+\tstruct dcbx_mib operational_dcbx_mib;\n+\n \t/* FC_NPIV table offset & size in NVRAM value of 0 means not present */\n \tu32 fc_npiv_nvram_tbl_addr;\n \tu32 fc_npiv_nvram_tbl_size;\n@@ -629,6 +812,9 @@ struct public_drv_mb {\n \t/*        - DONT_CARE - Don't flap the link if up */\n #define DRV_MSG_CODE_LINK_RESET\t\t\t0x23000000\n \n+\t/* Vitaly: LLDP commands */\n+#define DRV_MSG_CODE_SET_LLDP                   0x24000000\n+#define DRV_MSG_CODE_SET_DCBX                   0x25000000\n \t/* OneView feature driver HSI */\n #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG\t\t0x26000000\n #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM\t\t0x27000000\n@@ -700,6 +886,14 @@ struct public_drv_mb {\n #define DRV_MB_PARAM_INIT_PHY_FORCE\t\t0x00000001\n #define DRV_MB_PARAM_INIT_PHY_DONT_CARE\t\t0x00000002\n \n+\t/* LLDP / DCBX params */\n+#define DRV_MB_PARAM_LLDP_SEND_MASK\t\t0x00000001\n+#define DRV_MB_PARAM_LLDP_SEND_SHIFT\t\t0\n+#define DRV_MB_PARAM_LLDP_AGENT_MASK\t\t0x00000006\n+#define DRV_MB_PARAM_LLDP_AGENT_SHIFT\t\t1\n+#define DRV_MB_PARAM_DCBX_NOTIFY_MASK\t\t0x00000008\n+#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT\t\t3\n+\n #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK\t0x000000FF\n #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT\t0\n \n@@ -806,6 +1000,9 @@ struct public_drv_mb {\n #define FW_MSG_CODE_INIT_PHY_DONE\t\t0x21200000\n #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS\t0x21300000\n #define FW_MSG_CODE_LINK_RESET_DONE\t\t0x23000000\n+#define FW_MSG_CODE_SET_LLDP_DONE               0x24000000\n+#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000\n+#define FW_MSG_CODE_SET_DCBX_DONE               0x25000000\n #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE        0x26000000\n #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE         0x27000000\n #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE   0x28000000\n@@ -916,6 +1113,9 @@ enum MFW_DRV_MSG_TYPE {\n \tMFW_DRV_MSG_LINK_CHANGE,\n \tMFW_DRV_MSG_FLR_FW_ACK_FAILED,\n \tMFW_DRV_MSG_VF_DISABLED,\n+\tMFW_DRV_MSG_LLDP_DATA_UPDATED,\n+\tMFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,\n+\tMFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,\n \tMFW_DRV_MSG_ERROR_RECOVERY,\n \tMFW_DRV_MSG_BW_UPDATE,\n \tMFW_DRV_MSG_S_TAG_UPDATE,\ndiff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h\nindex 907994b..7f1a60d 100644\n--- a/drivers/net/qede/base/nvm_cfg.h\n+++ b/drivers/net/qede/base/nvm_cfg.h\n@@ -553,6 +553,12 @@ struct nvm_cfg1_port {\n #define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD\n #define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE\n #define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF\n+#define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000\n+#define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16\n+#define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0\n+#define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1\n+#define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2\n+#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3\n #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000\n #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20\n #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 46d4b6c..d5046a2 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -325,8 +325,8 @@ qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info)\n \tif (IS_PF(edev)) {\n \t\tinfo->num_queues = 0;\n \t\tfor_each_hwfn(edev, i)\n-\t\t    info->num_queues +=\n-\t\t    FEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE);\n+\t\t\tinfo->num_queues +=\n+\t\t\tFEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE);\n \n \t\tinfo->num_vlan_filters = RESC_NUM(&edev->hwfns[0], ECORE_VLAN);\n \n@@ -339,7 +339,7 @@ qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info)\n \t\t\t\t\t      &info->num_vlan_filters);\n \n \t\tecore_vf_get_port_mac(&edev->hwfns[0],\n-\t\t\t\t      (uint8_t *) &info->port_mac);\n+\t\t\t\t      (uint8_t *)&info->port_mac);\n \t}\n \n \tqed_fill_dev_info(edev, &info->common);\ndiff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex f76f42c..f08c7d5 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -603,7 +603,7 @@ static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)\n \n \tif (!qdev->num_rss) {\n \t\tDP_ERR(edev,\n-\t\t       \"Cannot update V-VPORT as active as\"\n+\t\t       \"Cannot update V-VPORT as active as \"\n \t\t       \"there are no Rx queues\\n\");\n \t\treturn -EINVAL;\n \t}\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "09/10"
    ]
}