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GET /api/patches/111893/?format=api
{ "id": 111893, "url": "https://patches.dpdk.org/api/patches/111893/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220526073215.428410-5-robinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220526073215.428410-5-robinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220526073215.428410-5-robinx.zhang@intel.com", "date": "2022-05-26T07:32:14", "name": "[v9,4/5] ethdev: support SFF-8472 module information telemetry", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1d4e63357d06048880a549448347d84db80e2b1f", "submitter": { "id": 2004, "url": "https://patches.dpdk.org/api/people/2004/?format=api", "name": "Robin Zhang", "email": "robinx.zhang@intel.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220526073215.428410-5-robinx.zhang@intel.com/mbox/", "series": [ { "id": 23180, "url": "https://patches.dpdk.org/api/series/23180/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23180", "date": "2022-05-26T07:32:10", "name": "add telemetry command for show module EEPROM", "version": 9, "mbox": "https://patches.dpdk.org/series/23180/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/111893/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/111893/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2DE54A0557;\n\tThu, 26 May 2022 09:40:01 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB0954281C;\n\tThu, 26 May 2022 09:39:39 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 842A3410DC\n for <dev@dpdk.org>; Thu, 26 May 2022 09:39:32 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 May 2022 00:39:30 -0700", "from intel-cd-odc-robin.cd.intel.com ([10.240.178.142])\n by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 May 2022 00:39:28 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653550772; x=1685086772;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=7d3efdIexF0PA9fqjmCgzVfyIrxub5gzBi3nQiI62mU=;\n b=danYpU4YaM2GhwhblG75Ll/gMNfm9BFcquJHsI9PwAokIvvpwvUt1wo7\n +3WB0cg+vuS8a9ydWRCyitlNckXrj8C+sfr0F6PfoGsyf807ABZWKTSkw\n fR/EE5lAKugg+gTfMtD5vxc/UklJcJVSTnC8x7jt6J80AnXgKZSlgQipj\n skz8tndr2BjNanIbjSwMwKwoH3JKutEnjsIdBR2ClPHRDnTgryT0Ro/K1\n KIxl88oN14GFWgVIcBYNN+lvCzL9vnu8EuwhGPNDCNm4A77JAUxtFJjoV\n 2yARJN0b7Ni0dSFYdRy5pS6xZ0a5mwRf5/wO9yi+0wcNjiJF5EYJKkFnn w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10358\"; a=\"272885337\"", "E=Sophos;i=\"5.91,252,1647327600\"; d=\"scan'208\";a=\"272885337\"", "E=Sophos;i=\"5.91,252,1647327600\"; d=\"scan'208\";a=\"549441867\"" ], "From": "Robin Zhang <robinx.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, andrew.rybchenko@oktetlabs.ru, kevinx.liu@intel.com,\n Robin Zhang <robinx.zhang@intel.com>", "Subject": "[PATCH v9 4/5] ethdev: support SFF-8472 module information telemetry", "Date": "Thu, 26 May 2022 07:32:14 +0000", "Message-Id": "<20220526073215.428410-5-robinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220526073215.428410-1-robinx.zhang@intel.com>", "References": "<20220525031446.72578-1-robinx.zhang@intel.com>\n <20220526073215.428410-1-robinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for module EEPROM information format defined in\nSFF-8472 Rev 12.0\n\nSigned-off-by: Robin Zhang <robinx.zhang@intel.com>\nSigned-off-by: Kevin Liu <kevinx.liu@intel.com>\n---\n lib/ethdev/meson.build | 1 +\n lib/ethdev/sff_8472.c | 280 +++++++++++++++++++++++++++++++++++++\n lib/ethdev/sff_telemetry.c | 4 +\n 3 files changed, 285 insertions(+)\n create mode 100644 lib/ethdev/sff_8472.c", "diff": "diff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build\nindex 5823fa0375..6c24c0b715 100644\n--- a/lib/ethdev/meson.build\n+++ b/lib/ethdev/meson.build\n@@ -14,6 +14,7 @@ sources = files(\n 'sff_telemetry.c',\n 'sff_common.c',\n 'sff_8079.c',\n+ 'sff_8472.c',\n )\n \n headers = files(\ndiff --git a/lib/ethdev/sff_8472.c b/lib/ethdev/sff_8472.c\nnew file mode 100644\nindex 0000000000..97f231854c\n--- /dev/null\n+++ b/lib/ethdev/sff_8472.c\n@@ -0,0 +1,280 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ * Implements SFF-8472 optics diagnostics.\n+ */\n+\n+#include <stdio.h>\n+\n+#include \"sff_common.h\"\n+\n+/* Offsets in decimal, for direct comparison with the SFF specs */\n+\n+/* A0-based EEPROM offsets for DOM support checks */\n+#define SFF_A0_DOM 92\n+#define SFF_A0_OPTIONS 93\n+#define SFF_A0_COMP 94\n+\n+/* EEPROM bit values for various registers */\n+#define SFF_A0_DOM_EXTCAL RTE_BIT32(4)\n+#define SFF_A0_DOM_INTCAL RTE_BIT32(5)\n+#define SFF_A0_DOM_IMPL RTE_BIT32(6)\n+#define SFF_A0_DOM_PWRT RTE_BIT32(3)\n+\n+#define SFF_A0_OPTIONS_AW RTE_BIT32(7)\n+\n+/*\n+ * This is the offset at which the A2 page is in the EEPROM\n+ * blob returned by the kernel.\n+ */\n+#define SFF_A2_BASE 0x100\n+\n+/* A2-based offsets for DOM */\n+#define SFF_A2_TEMP 96\n+#define SFF_A2_TEMP_HALRM 0\n+#define SFF_A2_TEMP_LALRM 2\n+#define SFF_A2_TEMP_HWARN 4\n+#define SFF_A2_TEMP_LWARN 6\n+\n+#define SFF_A2_VCC 98\n+#define SFF_A2_VCC_HALRM 8\n+#define SFF_A2_VCC_LALRM 10\n+#define SFF_A2_VCC_HWARN 12\n+#define SFF_A2_VCC_LWARN 14\n+\n+#define SFF_A2_BIAS 100\n+#define SFF_A2_BIAS_HALRM 16\n+#define SFF_A2_BIAS_LALRM 18\n+#define SFF_A2_BIAS_HWARN 20\n+#define SFF_A2_BIAS_LWARN 22\n+\n+#define SFF_A2_TX_PWR 102\n+#define SFF_A2_TX_PWR_HALRM 24\n+#define SFF_A2_TX_PWR_LALRM 26\n+#define SFF_A2_TX_PWR_HWARN 28\n+#define SFF_A2_TX_PWR_LWARN 30\n+\n+#define SFF_A2_RX_PWR 104\n+#define SFF_A2_RX_PWR_HALRM 32\n+#define SFF_A2_RX_PWR_LALRM 34\n+#define SFF_A2_RX_PWR_HWARN 36\n+#define SFF_A2_RX_PWR_LWARN 38\n+\n+#define SFF_A2_ALRM_FLG 112\n+#define SFF_A2_WARN_FLG 116\n+\n+/* 32-bit little-endian calibration constants */\n+#define SFF_A2_CAL_RXPWR4 56\n+#define SFF_A2_CAL_RXPWR3 60\n+#define SFF_A2_CAL_RXPWR2 64\n+#define SFF_A2_CAL_RXPWR1 68\n+#define SFF_A2_CAL_RXPWR0 72\n+\n+/* 16-bit little endian calibration constants */\n+#define SFF_A2_CAL_TXI_SLP 76\n+#define SFF_A2_CAL_TXI_OFF 78\n+#define SFF_A2_CAL_TXPWR_SLP 80\n+#define SFF_A2_CAL_TXPWR_OFF 82\n+#define SFF_A2_CAL_T_SLP 84\n+#define SFF_A2_CAL_T_OFF 86\n+#define SFF_A2_CAL_V_SLP 88\n+#define SFF_A2_CAL_V_OFF 90\n+\n+static struct sff_8472_aw_flags {\n+\tconst char *str; /* Human-readable string, null at the end */\n+\tint offset; /* A2-relative address offset */\n+\tuint8_t value; /* Alarm is on if (offset & value) != 0. */\n+} sff_8472_aw_flags[] = {\n+\t{ \"Laser bias current high alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(3) },\n+\t{ \"Laser bias current low alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(2) },\n+\t{ \"Laser bias current high warning\", SFF_A2_WARN_FLG, RTE_BIT32(3) },\n+\t{ \"Laser bias current low warning\", SFF_A2_WARN_FLG, RTE_BIT32(2) },\n+\n+\t{ \"Laser output power high alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(1) },\n+\t{ \"Laser output power low alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(0) },\n+\t{ \"Laser output power high warning\", SFF_A2_WARN_FLG, RTE_BIT32(1) },\n+\t{ \"Laser output power low warning\", SFF_A2_WARN_FLG, RTE_BIT32(0) },\n+\n+\t{ \"Module temperature high alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(7) },\n+\t{ \"Module temperature low alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(6) },\n+\t{ \"Module temperature high warning\", SFF_A2_WARN_FLG, RTE_BIT32(7) },\n+\t{ \"Module temperature low warning\", SFF_A2_WARN_FLG, RTE_BIT32(6) },\n+\n+\t{ \"Module voltage high alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(5) },\n+\t{ \"Module voltage low alarm\", SFF_A2_ALRM_FLG, RTE_BIT32(4) },\n+\t{ \"Module voltage high warning\", SFF_A2_WARN_FLG, RTE_BIT32(5) },\n+\t{ \"Module voltage low warning\", SFF_A2_WARN_FLG, RTE_BIT32(4) },\n+\n+\t{ \"Laser rx power high alarm\", SFF_A2_ALRM_FLG + 1, RTE_BIT32(7) },\n+\t{ \"Laser rx power low alarm\", SFF_A2_ALRM_FLG + 1, RTE_BIT32(6) },\n+\t{ \"Laser rx power high warning\", SFF_A2_WARN_FLG + 1, RTE_BIT32(7) },\n+\t{ \"Laser rx power low warning\", SFF_A2_WARN_FLG + 1, RTE_BIT32(6) },\n+\n+\t{ NULL, 0, 0 },\n+};\n+\n+/* Most common case: 16-bit unsigned integer in a certain unit */\n+#define A2_OFFSET_TO_U16(offset) \\\n+\t(data[SFF_A2_BASE + (offset)] << 8 | data[SFF_A2_BASE + (offset) + 1])\n+\n+/* Calibration slope is a number between 0.0 included and 256.0 excluded. */\n+#define A2_OFFSET_TO_SLP(offset) \\\n+\t(data[SFF_A2_BASE + (offset)] + data[SFF_A2_BASE + (offset) + 1] / 256.)\n+\n+/* Calibration offset is an integer from -32768 to 32767 */\n+#define A2_OFFSET_TO_OFF(offset) \\\n+\t((int16_t)A2_OFFSET_TO_U16(offset))\n+\n+/* RXPWR(x) are IEEE-754 floating point numbers in big-endian format */\n+#define A2_OFFSET_TO_RXPWRx(offset) \\\n+\t(befloattoh((const uint32_t *)(data + SFF_A2_BASE + (offset))))\n+\n+/*\n+ * 2-byte internal temperature conversions:\n+ * First byte is a signed 8-bit integer, which is the temp decimal part\n+ * Second byte are 1/256th of degree, which are added to the dec part.\n+ */\n+#define A2_OFFSET_TO_TEMP(offset) ((int16_t)A2_OFFSET_TO_U16(offset))\n+\n+static void sff_8472_dom_parse(const uint8_t *data, struct sff_diags *sd)\n+{\n+\tsd->bias_cur[SFF_MCURR] = A2_OFFSET_TO_U16(SFF_A2_BIAS);\n+\tsd->bias_cur[SFF_HALRM] = A2_OFFSET_TO_U16(SFF_A2_BIAS_HALRM);\n+\tsd->bias_cur[SFF_LALRM] = A2_OFFSET_TO_U16(SFF_A2_BIAS_LALRM);\n+\tsd->bias_cur[SFF_HWARN] = A2_OFFSET_TO_U16(SFF_A2_BIAS_HWARN);\n+\tsd->bias_cur[SFF_LWARN] = A2_OFFSET_TO_U16(SFF_A2_BIAS_LWARN);\n+\n+\tsd->sfp_voltage[SFF_MCURR] = A2_OFFSET_TO_U16(SFF_A2_VCC);\n+\tsd->sfp_voltage[SFF_HALRM] = A2_OFFSET_TO_U16(SFF_A2_VCC_HALRM);\n+\tsd->sfp_voltage[SFF_LALRM] = A2_OFFSET_TO_U16(SFF_A2_VCC_LALRM);\n+\tsd->sfp_voltage[SFF_HWARN] = A2_OFFSET_TO_U16(SFF_A2_VCC_HWARN);\n+\tsd->sfp_voltage[SFF_LWARN] = A2_OFFSET_TO_U16(SFF_A2_VCC_LWARN);\n+\n+\tsd->tx_power[SFF_MCURR] = A2_OFFSET_TO_U16(SFF_A2_TX_PWR);\n+\tsd->tx_power[SFF_HALRM] = A2_OFFSET_TO_U16(SFF_A2_TX_PWR_HALRM);\n+\tsd->tx_power[SFF_LALRM] = A2_OFFSET_TO_U16(SFF_A2_TX_PWR_LALRM);\n+\tsd->tx_power[SFF_HWARN] = A2_OFFSET_TO_U16(SFF_A2_TX_PWR_HWARN);\n+\tsd->tx_power[SFF_LWARN] = A2_OFFSET_TO_U16(SFF_A2_TX_PWR_LWARN);\n+\n+\tsd->rx_power[SFF_MCURR] = A2_OFFSET_TO_U16(SFF_A2_RX_PWR);\n+\tsd->rx_power[SFF_HALRM] = A2_OFFSET_TO_U16(SFF_A2_RX_PWR_HALRM);\n+\tsd->rx_power[SFF_LALRM] = A2_OFFSET_TO_U16(SFF_A2_RX_PWR_LALRM);\n+\tsd->rx_power[SFF_HWARN] = A2_OFFSET_TO_U16(SFF_A2_RX_PWR_HWARN);\n+\tsd->rx_power[SFF_LWARN] = A2_OFFSET_TO_U16(SFF_A2_RX_PWR_LWARN);\n+\n+\tsd->sfp_temp[SFF_MCURR] = A2_OFFSET_TO_TEMP(SFF_A2_TEMP);\n+\tsd->sfp_temp[SFF_HALRM] = A2_OFFSET_TO_TEMP(SFF_A2_TEMP_HALRM);\n+\tsd->sfp_temp[SFF_LALRM] = A2_OFFSET_TO_TEMP(SFF_A2_TEMP_LALRM);\n+\tsd->sfp_temp[SFF_HWARN] = A2_OFFSET_TO_TEMP(SFF_A2_TEMP_HWARN);\n+\tsd->sfp_temp[SFF_LWARN] = A2_OFFSET_TO_TEMP(SFF_A2_TEMP_LWARN);\n+}\n+\n+/* Converts to a float from a big-endian 4-byte source buffer. */\n+static float befloattoh(const uint32_t *source)\n+{\n+\tunion {\n+\t\tuint32_t src;\n+\t\tfloat dst;\n+\t} converter;\n+\n+\tconverter.src = ntohl(*source);\n+\treturn converter.dst;\n+}\n+\n+static void sff_8472_calibration(const uint8_t *data, struct sff_diags *sd)\n+{\n+\tunsigned long i;\n+\tuint16_t rx_reading;\n+\n+\t/* Calibration should occur for all values (threshold and current) */\n+\tfor (i = 0; i < RTE_DIM(sd->bias_cur); ++i) {\n+\t\t/*\n+\t\t * Apply calibration formula 1 (Temp., Voltage, Bias, Tx Power)\n+\t\t */\n+\t\tsd->bias_cur[i] *= A2_OFFSET_TO_SLP(SFF_A2_CAL_TXI_SLP);\n+\t\tsd->tx_power[i] *= A2_OFFSET_TO_SLP(SFF_A2_CAL_TXPWR_SLP);\n+\t\tsd->sfp_voltage[i] *= A2_OFFSET_TO_SLP(SFF_A2_CAL_V_SLP);\n+\t\tsd->sfp_temp[i] *= A2_OFFSET_TO_SLP(SFF_A2_CAL_T_SLP);\n+\n+\t\tsd->bias_cur[i] += A2_OFFSET_TO_OFF(SFF_A2_CAL_TXI_OFF);\n+\t\tsd->tx_power[i] += A2_OFFSET_TO_OFF(SFF_A2_CAL_TXPWR_OFF);\n+\t\tsd->sfp_voltage[i] += A2_OFFSET_TO_OFF(SFF_A2_CAL_V_OFF);\n+\t\tsd->sfp_temp[i] += A2_OFFSET_TO_OFF(SFF_A2_CAL_T_OFF);\n+\n+\t\t/*\n+\t\t * Apply calibration formula 2 (Rx Power only)\n+\t\t */\n+\t\trx_reading = sd->rx_power[i];\n+\t\tsd->rx_power[i] = A2_OFFSET_TO_RXPWRx(SFF_A2_CAL_RXPWR0);\n+\t\tsd->rx_power[i] += rx_reading *\n+\t\t\tA2_OFFSET_TO_RXPWRx(SFF_A2_CAL_RXPWR1);\n+\t\tsd->rx_power[i] += rx_reading *\n+\t\t\tA2_OFFSET_TO_RXPWRx(SFF_A2_CAL_RXPWR2);\n+\t\tsd->rx_power[i] += rx_reading *\n+\t\t\tA2_OFFSET_TO_RXPWRx(SFF_A2_CAL_RXPWR3);\n+\t}\n+}\n+\n+static void sff_8472_parse_eeprom(const uint8_t *data, struct sff_diags *sd)\n+{\n+\tsd->supports_dom = data[SFF_A0_DOM] & SFF_A0_DOM_IMPL;\n+\tsd->supports_alarms = data[SFF_A0_OPTIONS] & SFF_A0_OPTIONS_AW;\n+\tsd->calibrated_ext = data[SFF_A0_DOM] & SFF_A0_DOM_EXTCAL;\n+\tsd->rx_power_type = data[SFF_A0_DOM] & SFF_A0_DOM_PWRT;\n+\n+\tsff_8472_dom_parse(data, sd);\n+\n+\t/*\n+\t * If the SFP is externally calibrated, we need to read calibration data\n+\t * and compensate the already stored readings.\n+\t */\n+\tif (sd->calibrated_ext)\n+\t\tsff_8472_calibration(data, sd);\n+}\n+\n+void sff_8472_show_all(const uint8_t *data, struct rte_tel_data *d)\n+{\n+\tstruct sff_diags sd = {0};\n+\tconst char *rx_power_string = NULL;\n+\tchar val_string[SFF_ITEM_VAL_COMPOSE_SIZE];\n+\tint i;\n+\n+\tsff_8472_parse_eeprom(data, &sd);\n+\n+\tif (!sd.supports_dom) {\n+\t\tssf_add_dict_string(d, \"Optical diagnostics support\", \"No\");\n+\t\treturn;\n+\t}\n+\tssf_add_dict_string(d, \"Optical diagnostics support\", \"Yes\");\n+\n+\tSFF_SPRINT_BIAS(val_string, sd.bias_cur[SFF_MCURR]);\n+\tssf_add_dict_string(d, \"Laser bias current\", val_string);\n+\n+\tSFF_SPRINT_xX_PWR(val_string, sd.tx_power[SFF_MCURR]);\n+\tssf_add_dict_string(d, \"Laser output power\", val_string);\n+\n+\tif (!sd.rx_power_type)\n+\t\trx_power_string = \"Receiver signal OMA\";\n+\telse\n+\t\trx_power_string = \"Receiver signal average optical power\";\n+\n+\tSFF_SPRINT_xX_PWR(val_string, sd.rx_power[SFF_MCURR]);\n+\tssf_add_dict_string(d, rx_power_string, val_string);\n+\n+\tSFF_SPRINT_TEMP(val_string, sd.sfp_temp[SFF_MCURR]);\n+\tssf_add_dict_string(d, \"Module temperature\", val_string);\n+\n+\tSFF_SPRINT_VCC(val_string, sd.sfp_voltage[SFF_MCURR]);\n+\tssf_add_dict_string(d, \"Module voltage\", val_string);\n+\n+\tssf_add_dict_string(d, \"Alarm/warning flags implemented\",\n+\t\t\t(sd.supports_alarms ? \"Yes\" : \"No\"));\n+\n+\tif (sd.supports_alarms) {\n+\t\tfor (i = 0; sff_8472_aw_flags[i].str; ++i) {\n+\t\t\tssf_add_dict_string(d, sff_8472_aw_flags[i].str,\n+\t\t\t\t\tdata[SFF_A2_BASE + sff_8472_aw_flags[i].offset]\n+\t\t\t\t\t& sff_8472_aw_flags[i].value ? \"On\" : \"Off\");\n+\t\t}\n+\t\tsff_show_thresholds(sd, d);\n+\t}\n+}\ndiff --git a/lib/ethdev/sff_telemetry.c b/lib/ethdev/sff_telemetry.c\nindex bc458af532..babb9418b2 100644\n--- a/lib/ethdev/sff_telemetry.c\n+++ b/lib/ethdev/sff_telemetry.c\n@@ -73,6 +73,10 @@ sff_port_module_eeprom_parse(uint16_t port_id, struct rte_tel_data *d)\n \tcase RTE_ETH_MODULE_SFF_8079:\n \t\tsff_8079_show_all(einfo.data, d);\n \t\tbreak;\n+\tcase RTE_ETH_MODULE_SFF_8472:\n+\t\tsff_8079_show_all(einfo.data, d);\n+\t\tsff_8472_show_all(einfo.data, d);\n+\t\tbreak;\n \tdefault:\n \t\tRTE_ETHDEV_LOG(NOTICE, \"Unsupported module type: %u\\n\", minfo.type);\n \t\tbreak;\n", "prefixes": [ "v9", "4/5" ] }