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{
    "id": 111773,
    "url": "https://patches.dpdk.org/api/patches/111773/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1653443483-30971-2-git-send-email-wei.huang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1653443483-30971-2-git-send-email-wei.huang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1653443483-30971-2-git-send-email-wei.huang@intel.com",
    "date": "2022-05-25T01:51:22",
    "name": "[v1,1/2] raw/ifpga/base: add pmci driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "96d2a4583c084c3bcf2a1b25dad5dc7700a86b99",
    "submitter": {
        "id": 2033,
        "url": "https://patches.dpdk.org/api/people/2033/?format=api",
        "name": "Wei Huang",
        "email": "wei.huang@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1653443483-30971-2-git-send-email-wei.huang@intel.com/mbox/",
    "series": [
        {
            "id": 23136,
            "url": "https://patches.dpdk.org/api/series/23136/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23136",
            "date": "2022-05-25T01:51:21",
            "name": "Update rsu implementation",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/23136/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/111773/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/111773/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6B55FA0545;\n\tWed, 25 May 2022 03:44:31 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C111A42685;\n\tWed, 25 May 2022 03:44:26 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 8AA9040E2D;\n Wed, 25 May 2022 03:44:24 +0200 (CEST)",
            "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 May 2022 18:44:23 -0700",
            "from unknown (HELO zj-fpga-amt.sh.intel.com) ([10.238.175.102])\n by orsmga004.jf.intel.com with ESMTP; 24 May 2022 18:44:20 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653443064; x=1684979064;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=9whPs2PWPcnyrw3UmmYDfF5iPGVTTRnaROLy/uHSVNU=;\n b=GVnSwkjFggp0N/aiODC9vnF1epBIt8rBQnEFgbgqZ3W0qqiNlhAoYhTS\n O83Y9LuE/SvTjtfY0a1PPftlh5QjfjXzDgHpg93KfF0TfQ6sslNZsKChk\n Ki4dVepIsp854OO9XFbx+a+yK6YsZUsxaJsIJVAhecfoUApV85+yLVOEf\n 0d+Iwgp+TXtz4vnHIiz5WHNP/9mupD4jdqxDv2yAFmPOmg2wsr2FUQ4BC\n X9f1GAhksJHGsVaW9vWDTgTuuDjpF/vbDNXtPjo1O+2JCUayyCnKUJhbn\n 7mogVmzyiQKbCZWoXzxOnkla5N60UsA1llc5OsCfPhRtyYn/vWsobku54 g==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10357\"; a=\"299019359\"",
            "E=Sophos;i=\"5.91,250,1647327600\"; d=\"scan'208\";a=\"299019359\"",
            "E=Sophos;i=\"5.91,250,1647327600\"; d=\"scan'208\";a=\"703705946\""
        ],
        "X-ExtLoop1": "1",
        "From": "Wei Huang <wei.huang@intel.com>",
        "To": "dev@dpdk.org, thomas@monjalon.net, nipun.gupta@nxp.com,\n hemant.agrawal@nxp.com",
        "Cc": "stable@dpdk.org, rosen.xu@intel.com, tianfei.zhang@intel.com,\n qi.z.zhang@intel.com, Wei Huang <wei.huang@intel.com>",
        "Subject": "[PATCH v1 1/2] raw/ifpga/base: add pmci driver",
        "Date": "Tue, 24 May 2022 21:51:22 -0400",
        "Message-Id": "<1653443483-30971-2-git-send-email-wei.huang@intel.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1653443483-30971-1-git-send-email-wei.huang@intel.com>",
        "References": "<1653443483-30971-1-git-send-email-wei.huang@intel.com>",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "PMCI (Platform Management Control Interface) is a new module in FPGA,\nwhich is designed to cooperate with BMC chip to fulfill board management\nfunctions.\nThis driver provide interfaces to access registers of BMC chip and\nexternal flash of FPGA.\n\nSigned-off-by: Wei Huang <wei.huang@intel.com>\nAcked-by: Tianfei Zhang <tianfei.zhang@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_defines.h           | 103 ++-\n drivers/raw/ifpga/base/ifpga_feature_dev.c       |   2 +\n drivers/raw/ifpga/base/ifpga_feature_dev.h       |   1 +\n drivers/raw/ifpga/base/ifpga_fme.c               | 265 +++++--\n drivers/raw/ifpga/base/ifpga_fme_error.c         |   2 +\n drivers/raw/ifpga/base/ifpga_port_error.c        |   2 +-\n drivers/raw/ifpga/base/ifpga_sec_mgr.c           |   9 +-\n drivers/raw/ifpga/base/ifpga_sec_mgr.h           |   9 +-\n drivers/raw/ifpga/base/opae_hw_api.c             |  29 +\n drivers/raw/ifpga/base/opae_hw_api.h             |   1 +\n drivers/raw/ifpga/base/opae_intel_max10.c        | 938 ++++++++++++++++++++---\n drivers/raw/ifpga/base/opae_intel_max10.h        | 313 +++++++-\n drivers/raw/ifpga/base/opae_osdep.h              |  43 +-\n drivers/raw/ifpga/base/osdep_rte/osdep_generic.h |  10 +\n 14 files changed, 1524 insertions(+), 203 deletions(-)",
    "diff": "diff --git a/drivers/raw/ifpga/base/ifpga_defines.h b/drivers/raw/ifpga/base/ifpga_defines.h\nindex 9a280eb..7c8fa89 100644\n--- a/drivers/raw/ifpga/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga/base/ifpga_defines.h\n@@ -23,6 +23,7 @@\n #define FME_FEATURE_NIOS_SPI        \"fme_nios_spi\"\n #define FME_FEATURE_I2C_MASTER      \"fme_i2c_master\"\n #define FME_FEATURE_ETH_GROUP       \"fme_eth_group\"\n+#define FME_FEATURE_PMCI            \"fme_pmci\"\n \n #define PORT_FEATURE_HEADER         \"port_hdr\"\n #define PORT_FEATURE_UAFU           \"port_uafu\"\n@@ -91,6 +92,7 @@ enum fpga_id_type {\n #define FME_FEATURE_ID_NIOS_SPI 0xd\n #define FME_FEATURE_ID_I2C_MASTER  0xf\n #define FME_FEATURE_ID_ETH_GROUP 0x10\n+#define FME_FEATURE_ID_PMCI      0x12\n \n #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER\n #define PORT_FEATURE_ID_ERROR 0x10\n@@ -266,6 +268,24 @@ struct feature_fme_bitstream_id {\n \tunion {\n \t\tu64 csr;\n \t\tstruct {\n+\t\t\tu8 build_patch:8;\n+\t\t\tu8 build_minor:8;\n+\t\t\tu8 build_major:8;\n+\t\t\tu8 fvl_bypass:1;\n+\t\t\tu8 mac_lightweight:1;\n+\t\t\tu8 disagregate:1;\n+\t\t\tu8 lightweiht:1;\n+\t\t\tu8 seu:1;\n+\t\t\tu8 ptp:1;\n+\t\t\tu8 reserve:2;\n+\t\t\tu8 interface:4;\n+\t\t\tu32 afu_revision:12;\n+\t\t\tu8 patch:4;\n+\t\t\tu8 minor:4;\n+\t\t\tu8 major:4;\n+\t\t\tu8 reserved:4;\n+\t\t} v1;\n+\t\tstruct {\n \t\t\tu32 gitrepo_hash:32;\t/* GIT repository hash */\n \t\t\t/*\n \t\t\t * HSSI configuration identifier:\n@@ -274,7 +294,8 @@ struct feature_fme_bitstream_id {\n \t\t\t * 2 - Ethernet\n \t\t\t */\n \t\t\tu8  hssi_id:4;\n-\t\t\tu16 rsvd1:12;\t\t/* Reserved */\n+\t\t\tu8  rsvd1:4;\n+\t\t\tu8  fim_type:8;\n \t\t\t/* Bitstream version patch number */\n \t\t\tu8  bs_verpatch:4;\n \t\t\t/* Bitstream version minor number */\n@@ -283,7 +304,7 @@ struct feature_fme_bitstream_id {\n \t\t\tu8  bs_vermajor:4;\n \t\t\t/* Bitstream version debug number */\n \t\t\tu8  bs_verdebug:4;\n-\t\t};\n+\t\t} v2;\n \t};\n };\n \n@@ -1670,31 +1691,6 @@ struct bts_header {\n \n #define check_support(n) (n == 1 ? \"support\" : \"no\")\n \n-/* bitstream id definition */\n-struct fme_bitstream_id {\n-\tunion {\n-\t\tu64 id;\n-\t\tstruct {\n-\t\t\tu8 build_patch:8;\n-\t\t\tu8 build_minor:8;\n-\t\t\tu8 build_major:8;\n-\t\t\tu8 fvl_bypass:1;\n-\t\t\tu8 mac_lightweight:1;\n-\t\t\tu8 disagregate:1;\n-\t\t\tu8 lightweiht:1;\n-\t\t\tu8 seu:1;\n-\t\t\tu8 ptp:1;\n-\t\t\tu8 reserve:2;\n-\t\t\tu8 interface:4;\n-\t\t\tu32 afu_revision:12;\n-\t\t\tu8 patch:4;\n-\t\t\tu8 minor:4;\n-\t\t\tu8 major:4;\n-\t\t\tu8 reserved:4;\n-\t\t};\n-\t};\n-};\n-\n enum board_interface {\n \tVC_8_10G = 0,\n \tVC_4_25G = 1,\n@@ -1703,10 +1699,30 @@ enum board_interface {\n \tVC_2_2_25G = 4,\n };\n \n+enum fim_type {\n+\tBASE_ADP = 0,\n+\tBASE_FDK,\n+\tBASE_X16_ADP,\n+\tBASE_X16_FDK,\n+\tFIMA_10G_ADP,\n+\tFIMA_25G_ADP,\n+\tFIMA_100G_ADP,\n+\tFIMB_ADP,\n+\tFIMC_ADP\n+};\n+\n+enum hssi_id {\n+\tNO_HSSI = 0,\n+\tPCIE_RP,\n+\tETHER_NET\n+};\n+\n enum pac_major {\n \tVISTA_CREEK = 0,\n \tRUSH_CREEK = 1,\n \tDARBY_CREEK = 2,\n+\tLIGHTNING_CREEK = 3,\n+\tARROW_CREEK = 5,\n };\n \n enum pac_minor {\n@@ -1718,23 +1734,30 @@ enum pac_minor {\n struct opae_board_info {\n \tenum pac_major major;\n \tenum pac_minor minor;\n-\tenum board_interface type;\n-\n-\t/* PAC features */\n-\tu8 fvl_bypass;\n-\tu8 mac_lightweight;\n-\tu8 disaggregate;\n-\tu8 lightweight;\n-\tu8 seu;\n-\tu8 ptp;\n \n \tu32 boot_page;\n \tu32 max10_version;\n \tu32 nios_fw_version;\n-\tu32 nums_of_retimer;\n-\tu32 ports_per_retimer;\n-\tu32 nums_of_fvl;\n-\tu32 ports_per_fvl;\n+\n+\tunion {\n+\t\tstruct {  /* N3000 specific */\n+\t\t\tenum board_interface type;\n+\t\t\tu8 fvl_bypass;\n+\t\t\tu8 mac_lightweight;\n+\t\t\tu8 disaggregate;\n+\t\t\tu8 lightweight;\n+\t\t\tu8 seu;\n+\t\t\tu8 ptp;\n+\t\t\tu32 nums_of_retimer;\n+\t\t\tu32 ports_per_retimer;\n+\t\t\tu32 nums_of_fvl;\n+\t\t\tu32 ports_per_fvl;\n+\t\t};\n+\t\tstruct {\n+\t\t\tenum fim_type n6000_fim_type;\n+\t\t\tenum hssi_id n6000_hssi_id;\n+\t\t};\n+\t};\n };\n \n #pragma pack(pop)\ndiff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.c b/drivers/raw/ifpga/base/ifpga_feature_dev.c\nindex dbecc7b..0a00af1 100644\n--- a/drivers/raw/ifpga/base/ifpga_feature_dev.c\n+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.c\n@@ -227,6 +227,8 @@ int port_clear_error(struct ifpga_port_hw *port)\n \t&fme_i2c_master_ops),},\n \t{FEATURE_DRV(FME_FEATURE_ID_ETH_GROUP, FME_FEATURE_ETH_GROUP,\n \t&fme_eth_group_ops),},\n+\t{FEATURE_DRV(FME_FEATURE_ID_PMCI, FME_FEATURE_PMCI,\n+\t&fme_pmci_ops),},\n \t{0, NULL, NULL}, /* end of arrary */\n };\n \ndiff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.h b/drivers/raw/ifpga/base/ifpga_feature_dev.h\nindex b355d22..a637eb5 100644\n--- a/drivers/raw/ifpga/base/ifpga_feature_dev.h\n+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.h\n@@ -178,6 +178,7 @@ int do_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, u32 size,\n extern struct ifpga_feature_ops fme_i2c_master_ops;\n extern struct ifpga_feature_ops fme_eth_group_ops;\n extern struct ifpga_feature_ops fme_nios_spi_master_ops;\n+extern struct ifpga_feature_ops fme_pmci_ops;\n \n int port_get_prop(struct ifpga_port_hw *port, struct feature_prop *prop);\n int port_set_prop(struct ifpga_port_hw *port, struct feature_prop *prop);\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c\nindex 43c7b9c..1b9a922 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme.c\n@@ -790,19 +790,32 @@ struct ifpga_feature_ops fme_emif_ops = {\n \t.uinit = fme_emif_uinit,\n };\n \n-static const char *board_type_to_string(u32 type)\n-{\n-\tswitch (type) {\n-\tcase VC_8_10G:\n-\t\treturn \"VC_8x10G\";\n-\tcase VC_4_25G:\n-\t\treturn \"VC_4x25G\";\n-\tcase VC_2_1_25:\n-\t\treturn \"VC_2x1x25G\";\n-\tcase VC_4_25G_2_25G:\n-\t\treturn \"VC_4x25G+2x25G\";\n-\tcase VC_2_2_25G:\n-\t\treturn \"VC_2x2x25G\";\n+static const char *board_type_to_string(u32 board, u32 type)\n+{\n+\tif (board == VISTA_CREEK) {\n+\t\tswitch (type) {\n+\t\tcase VC_8_10G:\n+\t\t\treturn \"8x10G\";\n+\t\tcase VC_4_25G:\n+\t\t\treturn \"4x25G\";\n+\t\tcase VC_2_1_25:\n+\t\t\treturn \"2x1x25G\";\n+\t\tcase VC_4_25G_2_25G:\n+\t\t\treturn \"4x25G+2x25G\";\n+\t\tcase VC_2_2_25G:\n+\t\t\treturn \"2x2x25G\";\n+\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tswitch (type) {\n+\t\tcase FIMA_10G_ADP:\n+\t\t\treturn \"2x4x10G\";\n+\t\tcase FIMA_25G_ADP:\n+\t\t\treturn \"2x2x25G\";\n+\t\tcase FIMA_100G_ADP:\n+\t\t\treturn \"2x100G\";\n+\t\tbreak;\n+\t\t}\n \t}\n \n \treturn \"unknown\";\n@@ -817,6 +830,12 @@ static const char *board_major_to_string(u32 major)\n \t\treturn \"RUSH_CREEK\";\n \tcase DARBY_CREEK:\n \t\treturn \"DARBY_CREEK\";\n+\tcase LIGHTNING_CREEK:\n+\t\treturn \"LIGHTNING_CREEK\";\n+\tcase ARROW_CREEK:\n+\t\treturn \"ARROW_CREEK\";\n+\tdefault:\n+\t\tbreak;\n \t}\n \n \treturn \"unknown\";\n@@ -859,35 +878,56 @@ static int board_type_to_info(u32 type,\n \n static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n {\n-\tstruct fme_bitstream_id id;\n+\tstruct feature_fme_bitstream_id id;\n \tstruct ifpga_hw *hw;\n \tu32 val;\n+\tconst char *type = NULL;\n+\tint ret;\n \n \thw = fme->parent;\n \tif (!hw)\n \t\treturn -ENODEV;\n \n-\tif (fme_hdr_get_bitstream_id(fme, &id.id))\n+\tif (fme_hdr_get_bitstream_id(fme, &id.csr))\n \t\treturn -EINVAL;\n \n-\tfme->board_info.major = id.major;\n-\tfme->board_info.minor = id.minor;\n-\tfme->board_info.type = id.interface;\n-\tfme->board_info.fvl_bypass = id.fvl_bypass;\n-\tfme->board_info.mac_lightweight = id.mac_lightweight;\n-\tfme->board_info.lightweight = id.lightweiht;\n-\tfme->board_info.disaggregate = id.disagregate;\n-\tfme->board_info.seu = id.seu;\n-\tfme->board_info.ptp = id.ptp;\n+\tif (id.v1.major == ARROW_CREEK) {\n+\t\tfme->board_info.major = id.v2.bs_vermajor;\n+\t\tfme->board_info.minor = id.v2.bs_verminor;\n+\t\tfme->board_info.n6000_fim_type = id.v2.fim_type;\n+\t\tfme->board_info.n6000_hssi_id = id.v2.hssi_id;\n+\t\ttype = board_type_to_string(fme->board_info.major,\n+\t\t\t\tfme->board_info.n6000_fim_type);\n+\t} else {\n+\t\tfme->board_info.major = id.v1.major;\n+\t\tfme->board_info.minor = id.v1.minor;\n+\t\tfme->board_info.type = id.v1.interface;\n+\t\tfme->board_info.fvl_bypass = id.v1.fvl_bypass;\n+\t\tfme->board_info.mac_lightweight = id.v1.mac_lightweight;\n+\t\tfme->board_info.lightweight = id.v1.lightweiht;\n+\t\tfme->board_info.disaggregate = id.v1.disagregate;\n+\t\tfme->board_info.seu = id.v1.seu;\n+\t\tfme->board_info.ptp = id.v1.ptp;\n+\t\ttype = board_type_to_string(fme->board_info.major,\n+\t\t\t\tfme->board_info.type);\n+\t}\n \n \tdev_info(fme, \"found: PCI dev: %02x:%02x:%x board: %s type: %s\\n\",\n \t\t\thw->pci_data->bus,\n \t\t\thw->pci_data->devid,\n \t\t\thw->pci_data->function,\n \t\t\tboard_major_to_string(fme->board_info.major),\n-\t\t\tboard_type_to_string(fme->board_info.type));\n+\t\t\ttype);\n \n-\tdev_info(fme, \"support feature:\\n\"\n+\tret = max10_get_fpga_load_info(fme->max10_dev, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\tfme->board_info.boot_page = val;\n+\n+\tif (fme->board_info.major == VISTA_CREEK) {\n+\t\tdev_info(dev, \"FPGA loaded from %s Image\\n\",\n+\t\t\tval ? \"User\" : \"Factory\");\n+\t\tdev_info(fme, \"support feature:\\n\"\n \t\t\t\"fvl_bypass:%s\\n\"\n \t\t\t\"mac_lightweight:%s\\n\"\n \t\t\t\"lightweight:%s\\n\"\n@@ -901,26 +941,29 @@ static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n \t\t\tcheck_support(fme->board_info.seu),\n \t\t\tcheck_support(fme->board_info.ptp));\n \n+\t\tif (board_type_to_info(fme->board_info.type, &fme->board_info))\n+\t\t\treturn -EINVAL;\n \n-\tif (board_type_to_info(fme->board_info.type, &fme->board_info))\n-\t\treturn -EINVAL;\n-\n-\tdev_info(fme, \"get board info: nums_retimers %d ports_per_retimer %d nums_fvl %d ports_per_fvl %d\\n\",\n+\t\tdev_info(fme, \"get board info: nums_retimers %d \"\n+\t\t\t\"ports_per_retimer %d nums_fvl %d \"\n+\t\t\t\"ports_per_fvl %d\\n\",\n \t\t\tfme->board_info.nums_of_retimer,\n \t\t\tfme->board_info.ports_per_retimer,\n \t\t\tfme->board_info.nums_of_fvl,\n \t\t\tfme->board_info.ports_per_fvl);\n+\t} else {\n+\t\tdev_info(dev, \"FPGA loaded from %s Image\\n\",\n+\t\t\tval ? (val == 1 ? \"User1\" : \"User2\") : \"Factory\");\n+\t}\n \n-\tif (max10_sys_read(fme->max10_dev, FPGA_PAGE_INFO, &val))\n-\t\treturn -EINVAL;\n-\tfme->board_info.boot_page = val & 0x7;\n-\n-\tif (max10_sys_read(fme->max10_dev, MAX10_BUILD_VER, &val))\n-\t\treturn -EINVAL;\n+\tret = max10_get_bmc_version(fme->max10_dev, &val);\n+\tif (ret)\n+\t\treturn ret;\n \tfme->board_info.max10_version = val;\n \n-\tif (max10_sys_read(fme->max10_dev, NIOS2_FW_VERSION, &val))\n-\t\treturn -EINVAL;\n+\tret = max10_get_bmcfw_version(fme->max10_dev, &val);\n+\tif (ret)\n+\t\treturn ret;\n \tfme->board_info.nios_fw_version = val;\n \n \tdev_info(fme, \"max10 version 0x%x, nios fw version 0x%x\\n\",\n@@ -983,11 +1026,25 @@ static int fme_spi_init(struct ifpga_feature *feature)\n \n \taltera_spi_init(spi_master);\n \n-\tmax10 = intel_max10_device_probe(spi_master, 0);\n-\tif (!max10) {\n+\tmax10 = opae_zmalloc(sizeof(*max10));\n+\tif (!max10)\n+\t\tgoto release_dev;\n+\n+\tmax10->spi_master = spi_master;\n+\tmax10->type = M10_N3000;\n+\n+\tmax10->spi_tran_dev = spi_transaction_init(spi_master, 0);\n+\tif (!max10->spi_tran_dev) {\n+\t\tdev_err(fme, \"%s spi tran init fail\\n\", __func__);\n+\t\tgoto free_max10;\n+\t}\n+\n+\t/* init the max10 device */\n+\tret = intel_max10_device_init(max10);\n+\tif (ret) {\n \t\tret = -ENODEV;\n \t\tdev_err(fme, \"max10 init fail\\n\");\n-\t\tgoto spi_fail;\n+\t\tgoto release_spi_tran_dev;\n \t}\n \n \tfme->max10_dev = max10;\n@@ -1002,17 +1059,24 @@ static int fme_spi_init(struct ifpga_feature *feature)\n \n max10_fail:\n \tintel_max10_device_remove(fme->max10_dev);\n-spi_fail:\n+release_spi_tran_dev:\n+\tif (max10->spi_tran_dev)\n+\t\tspi_transaction_remove(max10->spi_tran_dev);\n+free_max10:\n+\topae_free(max10);\n+release_dev:\n \taltera_spi_release(spi_master);\n-\treturn ret;\n+\treturn -ENODEV;\n }\n \n static void fme_spi_uinit(struct ifpga_feature *feature)\n {\n \tstruct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;\n \n-\tif (fme->max10_dev)\n+\tif (fme->max10_dev) {\n \t\tintel_max10_device_remove(fme->max10_dev);\n+\t\topae_free(fme->max10_dev);\n+\t}\n }\n \n struct ifpga_feature_ops fme_spi_master_ops = {\n@@ -1157,27 +1221,37 @@ static int fme_nios_spi_init(struct ifpga_feature *feature)\n \t/* 3. init the spi master*/\n \taltera_spi_init(spi_master);\n \n+\tmax10 = opae_zmalloc(sizeof(*max10));\n+\tif (!max10)\n+\t\tgoto release_dev;\n+\n+\tmax10->spi_master = spi_master;\n+\tmax10->type = M10_N3000;\n+\n+\tmax10->spi_tran_dev = spi_transaction_init(spi_master, 0);\n+\tif (!max10->spi_tran_dev) {\n+\t\tdev_err(fme, \"%s spi tran init fail\\n\", __func__);\n+\t\tgoto free_max10;\n+\t}\n+\n \t/* init the max10 device */\n-\tmax10 = intel_max10_device_probe(spi_master, 0);\n-\tif (!max10) {\n+\tret = intel_max10_device_init(max10);\n+\tif (ret) {\n \t\tret = -ENODEV;\n \t\tdev_err(fme, \"max10 init fail\\n\");\n-\t\tgoto release_dev;\n+\t\tgoto release_spi_tran_dev;\n \t}\n \n \tfme->max10_dev = max10;\n-\n \tmax10->bus = hw->pci_data->bus;\n-\n \tfme_get_board_interface(fme);\n-\n \tmgr->sensor_list = &max10->opae_sensor_list;\n \n \t/* SPI self test */\n \tif (spi_self_checking(max10))\n \t\tgoto spi_fail;\n \n-\tret = init_sec_mgr(fme);\n+\tret = init_sec_mgr(fme, N3000BMC_SEC);\n \tif (ret) {\n \t\tdev_err(fme, \"security manager init fail\\n\");\n \t\tgoto spi_fail;\n@@ -1187,6 +1261,11 @@ static int fme_nios_spi_init(struct ifpga_feature *feature)\n \n spi_fail:\n \tintel_max10_device_remove(fme->max10_dev);\n+release_spi_tran_dev:\n+\tif (max10->spi_tran_dev)\n+\t\tspi_transaction_remove(max10->spi_tran_dev);\n+free_max10:\n+\topae_free(max10);\n release_dev:\n \taltera_spi_release(spi_master);\n \treturn -ENODEV;\n@@ -1197,8 +1276,10 @@ static void fme_nios_spi_uinit(struct ifpga_feature *feature)\n \tstruct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;\n \n \trelease_sec_mgr(fme);\n-\tif (fme->max10_dev)\n+\tif (fme->max10_dev) {\n \t\tintel_max10_device_remove(fme->max10_dev);\n+\t\topae_free(fme->max10_dev);\n+\t}\n }\n \n struct ifpga_feature_ops fme_nios_spi_master_ops = {\n@@ -1230,7 +1311,7 @@ static int i2c_mac_rom_test(struct altera_i2c_dev *dev)\n \t}\n \n \tif (memcmp(buf, read_buf, strlen(string))) {\n-\t\tdev_err(NULL, \"%s test fail!\\n\", __func__);\n+\t\tdev_info(NULL, \"%s test fail!\\n\", __func__);\n \t\treturn -EFAULT;\n \t}\n \n@@ -1499,3 +1580,81 @@ int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,\n \n \treturn 0;\n }\n+\n+static int fme_pmci_init(struct ifpga_feature *feature)\n+{\n+\tstruct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;\n+\tstruct intel_max10_device *max10;\n+\tstruct ifpga_hw *hw;\n+\tstruct opae_manager *mgr;\n+\topae_share_data *sd = NULL;\n+\tint ret = 0;\n+\n+\thw = fme->parent;\n+\tif (!hw)\n+\t\treturn -ENODEV;\n+\n+\tmgr = hw->adapter->mgr;\n+\tif (!mgr)\n+\t\treturn -ENODEV;\n+\n+\tdev_info(fme, \"FME PMCI Init.\\n\");\n+\tdev_debug(fme, \"FME PMCI base addr %p.\\n\",\n+\t\t\tfeature->addr);\n+\n+\tmax10 = opae_zmalloc(sizeof(*max10));\n+\tif (!max10)\n+\t\treturn -ENOMEM;\n+\n+\tmax10->type = M10_N6000;\n+\tmax10->mmio = feature->addr;\n+\tif (hw->adapter && hw->adapter->shm.ptr) {\n+\t\tsd = (opae_share_data *)hw->adapter->shm.ptr;\n+\t\tmax10->bmc_ops.mutex = &sd->spi_mutex;\n+\t} else {\n+\t\tmax10->bmc_ops.mutex = NULL;\n+\t}\n+\n+\t/* init the max10 device */\n+\tret = intel_max10_device_init(max10);\n+\tif (ret) {\n+\t\tdev_err(fme, \"max10 init fail\\n\");\n+\t\tgoto free_max10;\n+\t}\n+\n+\tfme->max10_dev = max10;\n+\tmax10->bus = hw->pci_data->bus;\n+\tfme_get_board_interface(fme);\n+\tmgr->sensor_list = &max10->opae_sensor_list;\n+\n+\tret = init_sec_mgr(fme, N6000BMC_SEC);\n+\tif (ret) {\n+\t\tdev_err(fme, \"security manager init fail\\n\");\n+\t\tgoto release_max10;\n+\t}\n+\n+\treturn ret;\n+\n+release_max10:\n+\tintel_max10_device_remove(max10);\n+free_max10:\n+\topae_free(max10);\n+\n+\treturn ret;\n+}\n+\n+static void fme_pmci_uinit(struct ifpga_feature *feature)\n+{\n+\tstruct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;\n+\n+\trelease_sec_mgr(fme);\n+\tif (fme->max10_dev) {\n+\t\tintel_max10_device_remove(fme->max10_dev);\n+\t\topae_free(fme->max10_dev);\n+\t}\n+}\n+\n+struct ifpga_feature_ops fme_pmci_ops = {\n+\t.init = fme_pmci_init,\n+\t.uinit = fme_pmci_uinit,\n+};\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c b/drivers/raw/ifpga/base/ifpga_fme_error.c\nindex 5905eac..c5bed28 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme_error.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c\n@@ -224,6 +224,8 @@ static int fme_global_error_init(struct ifpga_feature *feature)\n {\n \tstruct ifpga_fme_hw *fme = feature->parent;\n \n+\tdev_info(NULL, \"FME error_module Init.\\n\");\n+\n \tfme_error_enable(fme);\n \n \tif (feature->ctx_num)\ndiff --git a/drivers/raw/ifpga/base/ifpga_port_error.c b/drivers/raw/ifpga/base/ifpga_port_error.c\nindex 189f762..6c8a7d7 100644\n--- a/drivers/raw/ifpga/base/ifpga_port_error.c\n+++ b/drivers/raw/ifpga/base/ifpga_port_error.c\n@@ -88,7 +88,7 @@ static int port_error_init(struct ifpga_feature *feature)\n {\n \tstruct ifpga_port_hw *port = feature->parent;\n \n-\tdev_info(NULL, \"port error Init.\\n\");\n+\tdev_info(NULL, \"port error_module Init.\\n\");\n \n \tspinlock_lock(&port->lock);\n \tport_err_mask(port, false);\ndiff --git a/drivers/raw/ifpga/base/ifpga_sec_mgr.c b/drivers/raw/ifpga/base/ifpga_sec_mgr.c\nindex 15fb5b6..557c4e3 100644\n--- a/drivers/raw/ifpga/base/ifpga_sec_mgr.c\n+++ b/drivers/raw/ifpga/base/ifpga_sec_mgr.c\n@@ -227,7 +227,7 @@ static int n3000_bulk_write(struct intel_max10_device *dev, uint32_t addr,\n \tfor (i = 0; i < n; i++) {\n \t\tp = i << 2;\n \t\tv = *(uint32_t *)(buf + p);\n-\t\tret = max10_reg_write(dev, addr + p, v);\n+\t\tret = max10_sys_raw_write(dev, addr + p, v);\n \t\tif (ret < 0) {\n \t\t\tdev_err(dev,\n \t\t\t\t\"Failed to write to staging area 0x%08x [e:%d]\\n\",\n@@ -490,7 +490,7 @@ static int n3000_reload_bmc(struct intel_max10_device *dev, int page)\n \t\t\tCONFIG_SEL_S(page) | REBOOT_REQ);\n \t} else {\n \t\tval = (page == 0) ? 0x1 : 0x3;\n-\t\tret = max10_reg_write(dev, IFPGA_DUAL_CFG_CTRL1, val);\n+\t\tret = max10_sys_raw_write(dev, IFPGA_DUAL_CFG_CTRL1, val);\n \t\tif (ret < 0) {\n \t\t\tdev_err(dev,\n \t\t\t\t\"Failed to write to dual config1 register [e:%d]\\n\",\n@@ -498,7 +498,7 @@ static int n3000_reload_bmc(struct intel_max10_device *dev, int page)\n \t\t\tgoto end;\n \t\t}\n \n-\t\tret = max10_reg_write(dev, IFPGA_DUAL_CFG_CTRL0, 0x1);\n+\t\tret = max10_sys_raw_write(dev, IFPGA_DUAL_CFG_CTRL0, 0x1);\n \t\tif (ret < 0) {\n \t\t\tif (ret == -EIO) {\n \t\t\t\tret = 0;\n@@ -584,7 +584,7 @@ static uint64_t n3000_get_hw_errinfo(struct ifpga_sec_mgr *smgr)\n \t.get_hw_errinfo = n3000_get_hw_errinfo,\n };\n \n-int init_sec_mgr(struct ifpga_fme_hw *fme)\n+int init_sec_mgr(struct ifpga_fme_hw *fme, enum fpga_sec_type type)\n {\n \tstruct ifpga_hw *hw = NULL;\n \topae_share_data *sd = NULL;\n@@ -621,6 +621,7 @@ int init_sec_mgr(struct ifpga_fme_hw *fme)\n \n \tsmgr->fme = fme;\n \tsmgr->max10_dev = fme->max10_dev;\n+\tsmgr->type = type;\n \n \treturn 0;\n }\ndiff --git a/drivers/raw/ifpga/base/ifpga_sec_mgr.h b/drivers/raw/ifpga/base/ifpga_sec_mgr.h\nindex fbeba56..09cc038 100644\n--- a/drivers/raw/ifpga/base/ifpga_sec_mgr.h\n+++ b/drivers/raw/ifpga/base/ifpga_sec_mgr.h\n@@ -55,6 +55,12 @@\n #define IFPGA_RSU_ERR_WEAROUT\t\t-7\n #define IFPGA_RSU_ERR_FILE_READ\t\t-8\n \n+/* Supported fpga secure manager types */\n+enum fpga_sec_type {\n+\tN3000BMC_SEC,\n+\tN6000BMC_SEC\n+};\n+\n struct ifpga_sec_mgr;\n \n struct ifpga_sec_ops {\n@@ -80,9 +86,10 @@ struct ifpga_sec_mgr {\n \tunsigned int *rsu_control;\n \tunsigned int *rsu_status;\n \tconst struct ifpga_sec_ops *ops;\n+\tenum fpga_sec_type type;\n };\n \n-int init_sec_mgr(struct ifpga_fme_hw *fme);\n+int init_sec_mgr(struct ifpga_fme_hw *fme, enum fpga_sec_type type);\n void release_sec_mgr(struct ifpga_fme_hw *fme);\n int fpga_update_flash(struct ifpga_fme_hw *fme, const char *image,\n \tuint64_t *status);\ndiff --git a/drivers/raw/ifpga/base/opae_hw_api.c b/drivers/raw/ifpga/base/opae_hw_api.c\nindex 87256fc..6b78094 100644\n--- a/drivers/raw/ifpga/base/opae_hw_api.c\n+++ b/drivers/raw/ifpga/base/opae_hw_api.c\n@@ -831,6 +831,35 @@ int opae_manager_get_retimer_status(struct opae_manager *mgr,\n }\n \n /**\n+ * opae_manager_get_sensor_list - get sensor name list\n+ * @mgr: opae_manager of sensors\n+ * @buf: buffer to accommodate name list separated by semicolon\n+ * @size: size of buffer\n+ *\n+ * Return: the pointer of the opae_sensor_info\n+ */\n+int\n+opae_mgr_get_sensor_list(struct opae_manager *mgr, char *buf, size_t size)\n+{\n+\tstruct opae_sensor_info *sensor;\n+\tuint32_t offset = 0;\n+\n+\topae_mgr_for_each_sensor(mgr, sensor) {\n+\t\tif (sensor->name) {\n+\t\t\tif (buf && (offset < size))\n+\t\t\t\tsnprintf(buf + offset, size - offset, \"%s;\",\n+\t\t\t\t\tsensor->name);\n+\t\t\toffset += strlen(sensor->name) + 1;\n+\t\t}\n+\t}\n+\n+\tif (buf && (offset > 0) && (offset <= size))\n+\t\tbuf[offset-1] = 0;\n+\n+\treturn offset;\n+}\n+\n+/**\n  * opae_manager_get_sensor_by_id - get sensor device\n  * @id: the id of the sensor\n  *\ndiff --git a/drivers/raw/ifpga/base/opae_hw_api.h b/drivers/raw/ifpga/base/opae_hw_api.h\nindex fd40e09..8aead4d 100644\n--- a/drivers/raw/ifpga/base/opae_hw_api.h\n+++ b/drivers/raw/ifpga/base/opae_hw_api.h\n@@ -93,6 +93,7 @@ int opae_manager_flash(struct opae_manager *mgr, int acc_id, const char *buf,\n \t\t       u32 size, u64 *status);\n int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,\n \t\tu8 group_id, struct opae_eth_group_region_info *info);\n+int opae_mgr_get_sensor_list(struct opae_manager *mgr, char *buf, size_t size);\n struct opae_sensor_info *opae_mgr_get_sensor_by_name(struct opae_manager *mgr,\n \t\tconst char *name);\n struct opae_sensor_info *opae_mgr_get_sensor_by_id(struct opae_manager *mgr,\ndiff --git a/drivers/raw/ifpga/base/opae_intel_max10.c b/drivers/raw/ifpga/base/opae_intel_max10.c\nindex 9d82fb0..465494a 100644\n--- a/drivers/raw/ifpga/base/opae_intel_max10.c\n+++ b/drivers/raw/ifpga/base/opae_intel_max10.c\n@@ -4,51 +4,42 @@\n \n #include \"opae_intel_max10.h\"\n #include <libfdt.h>\n+#include \"opae_osdep.h\"\n \n-int max10_reg_read(struct intel_max10_device *dev,\n-\tunsigned int reg, unsigned int *val)\n+int max10_sys_read(struct intel_max10_device *dev,\n+\tunsigned int offset, unsigned int *val)\n {\n-\tif (!dev)\n+\tif (!dev || !dev->ops->reg_read)\n \t\treturn -ENODEV;\n \n-\tdev_debug(dev, \"%s: bus:0x%x, reg:0x%x\\n\", __func__, dev->bus, reg);\n-\n-\treturn spi_transaction_read(dev->spi_tran_dev,\n-\t\t\treg, 4, (unsigned char *)val);\n+\treturn dev->ops->reg_read(dev, dev->csr->base + offset, val);\n }\n \n-int max10_reg_write(struct intel_max10_device *dev,\n-\tunsigned int reg, unsigned int val)\n+int max10_sys_write(struct intel_max10_device *dev,\n+\tunsigned int offset, unsigned int val)\n {\n-\tunsigned int tmp = val;\n-\n-\tif (!dev)\n+\tif (!dev || !dev->ops->reg_write)\n \t\treturn -ENODEV;\n \n-\tdev_debug(dev, \"%s: bus:0x%x, reg:0x%x, val:0x%x\\n\", __func__,\n-\t\t\tdev->bus, reg, val);\n-\n-\treturn spi_transaction_write(dev->spi_tran_dev,\n-\t\t\treg, 4, (unsigned char *)&tmp);\n+\treturn dev->ops->reg_write(dev, dev->csr->base + offset, val);\n }\n \n-int max10_sys_read(struct intel_max10_device *dev,\n+int max10_sys_raw_read(struct intel_max10_device *dev,\n \tunsigned int offset, unsigned int *val)\n {\n-\tif (!dev)\n+\tif (!dev || !dev->ops->reg_read)\n \t\treturn -ENODEV;\n \n-\n-\treturn max10_reg_read(dev, dev->base + offset, val);\n+\treturn dev->ops->reg_read(dev, offset, val);\n }\n \n-int max10_sys_write(struct intel_max10_device *dev,\n+int max10_sys_raw_write(struct intel_max10_device *dev,\n \tunsigned int offset, unsigned int val)\n {\n-\tif (!dev)\n+\tif (!dev || !dev->ops->reg_write)\n \t\treturn -ENODEV;\n \n-\treturn max10_reg_write(dev, dev->base + offset, val);\n+\treturn dev->ops->reg_write(dev, offset, val);\n }\n \n int max10_sys_update_bits(struct intel_max10_device *dev, unsigned int offset,\n@@ -67,6 +58,402 @@ int max10_sys_update_bits(struct intel_max10_device *dev, unsigned int offset,\n \treturn max10_sys_write(dev, offset, temp);\n }\n \n+static int n3000_bulk_raw_write(struct intel_max10_device *dev, uint32_t addr,\n+\tvoid *buf, uint32_t len)\n+{\n+\tuint32_t v = 0;\n+\tuint32_t i = 0;\n+\tchar *p = buf;\n+\tint ret = 0;\n+\n+\tlen = IFPGA_ALIGN(len, 4);\n+\n+\tfor (i = 0; i < len; i += 4) {\n+\t\tv = *(uint32_t *)(p + i);\n+\t\tret = max10_sys_raw_write(dev, addr + i, v);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev,\n+\t\t\t\t\"Failed to write to staging area 0x%08x [e:%d]\\n\",\n+\t\t\t\taddr + i, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int n3000_bulk_raw_read(struct intel_max10_device *dev,\n+\t\tuint32_t addr, void *buf, uint32_t len)\n+{\n+\tu32 v, i;\n+\tchar *p = buf;\n+\tint ret;\n+\n+\tlen = IFPGA_ALIGN(len, 4);\n+\n+\tfor (i = 0; i < len; i += 4) {\n+\t\tret = max10_sys_raw_read(dev, addr + i, &v);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev,\n+\t\t\t\t\"Failed to write to staging area 0x%08x [e:%d]\\n\",\n+\t\t\t\taddr + i, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\t*(u32 *)(p + i) = v;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int n3000_flash_read(struct intel_max10_device *dev,\n+\t\tu32 addr, void *buf, u32 size)\n+{\n+\tif (!dev->raw_blk_ops.read_blk)\n+\t\treturn -ENODEV;\n+\n+\treturn dev->raw_blk_ops.read_blk(dev, addr, buf, size);\n+}\n+\n+static int n3000_flash_write(struct intel_max10_device *dev,\n+\t\tu32 addr, void *buf, u32 size)\n+{\n+\tif (!dev->raw_blk_ops.write_blk)\n+\t\treturn -ENODEV;\n+\n+\treturn dev->raw_blk_ops.write_blk(dev, addr, buf, size);\n+}\n+\n+static u32\n+pmci_get_write_space(struct intel_max10_device *dev, u32 size)\n+{\n+\tu32 count, val;\n+\tint ret;\n+\n+\tret = opae_readl_poll_timeout(dev->mmio + PMCI_FLASH_CTRL, val,\n+\t\t\t\tGET_FIELD(PMCI_FLASH_FIFO_SPACE, val) ==\n+\t\t\t\tPMCI_FIFO_MAX_WORDS,\n+\t\t\t\tPMCI_FLASH_INT_US, PMCI_FLASH_TIMEOUT_US);\n+\tif (ret == -ETIMEDOUT)\n+\t\treturn 0;\n+\n+\tcount = GET_FIELD(PMCI_FLASH_FIFO_SPACE, val) * 4;\n+\n+\treturn (size > count) ? count : size;\n+}\n+\n+static void pmci_write_fifo(void __iomem *base, char *buf, size_t count)\n+{\n+\tsize_t i;\n+\tu32 val;\n+\n+\tfor (i = 0; i < count/4 ; i++) {\n+\t\tval = *(u32 *)(buf + i * 4);\n+\t\twritel(val, base);\n+\t}\n+}\n+\n+static void pmci_read_fifo(void __iomem *base, char *buf, size_t count)\n+{\n+\tsize_t i;\n+\tu32 val;\n+\n+\tfor (i = 0; i < count/4; i++) {\n+\t\tval = readl(base);\n+\t\t*(u32 *)(buf + i * 4) = val;\n+\t}\n+}\n+\n+static int\n+__pmci_flash_bulk_write(struct intel_max10_device *dev, u32 addr,\n+\t\tvoid *buf, u32 size)\n+{\n+\tUNUSED(addr);\n+\tu32 blk_size, n_offset = 0;\n+\n+\twhile (size) {\n+\t\tblk_size = pmci_get_write_space(dev, size);\n+\t\tif (blk_size == 0) {\n+\t\t\tdev_err(pmci->dev, \"get FIFO available size fail\\n\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\t\tsize -= blk_size;\n+\t\tpmci_write_fifo(dev->mmio + PMCI_FLASH_FIFO, (char *)buf + n_offset,\n+\t\t\t\tblk_size);\n+\t\tn_offset += blk_size;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+pmci_flash_bulk_write(struct intel_max10_device *dev, u32 addr,\n+\t\tvoid *buf, u32 size)\n+{\n+\tint ret;\n+\n+\tpthread_mutex_lock(dev->bmc_ops.mutex);\n+\n+\tret = __pmci_flash_bulk_write(dev, addr, buf, size);\n+\n+\tpthread_mutex_unlock(dev->bmc_ops.mutex);\n+\treturn ret;\n+}\n+\n+static int\n+pmci_set_flash_host_mux(struct intel_max10_device *dev, bool request)\n+{\n+\tu32 ctrl;\n+\tint ret;\n+\n+\tret = max10_sys_update_bits(dev,\n+\t\t\tm10bmc_base(dev) + M10BMC_PMCI_FLASH_CTRL,\n+\t\t\tFLASH_HOST_REQUEST,\n+\t\t\tSET_FIELD(FLASH_HOST_REQUEST, request));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn opae_max10_read_poll_timeout(dev, m10bmc_base(dev) + M10BMC_PMCI_FLASH_CTRL,\n+\t\t\tctrl, request ? (get_flash_mux(ctrl) == FLASH_MUX_HOST) :\n+\t\t\t(get_flash_mux(ctrl) != FLASH_MUX_HOST),\n+\t\t\tPMCI_FLASH_INT_US, PMCI_FLASH_TIMEOUT_US);\n+}\n+\n+static int\n+pmci_get_mux(struct intel_max10_device *dev)\n+{\n+\tpthread_mutex_lock(dev->bmc_ops.mutex);\n+\treturn pmci_set_flash_host_mux(dev, true);\n+}\n+\n+static int\n+pmci_put_mux(struct intel_max10_device *dev)\n+{\n+\tint ret;\n+\n+\tret = pmci_set_flash_host_mux(dev, false);\n+\tpthread_mutex_unlock(dev->bmc_ops.mutex);\n+\treturn ret;\n+}\n+\n+static int\n+__pmci_flash_bulk_read(struct intel_max10_device *dev, u32 addr,\n+\t\t     void *buf, u32 size)\n+{\n+\tu32 blk_size, offset = 0, val;\n+\tint ret;\n+\n+\twhile (size) {\n+\t\tblk_size = min_t(u32, size, PMCI_READ_BLOCK_SIZE);\n+\n+\t\topae_writel(addr + offset, dev->mmio + PMCI_FLASH_ADDR);\n+\n+\t\topae_writel(SET_FIELD(PMCI_FLASH_READ_COUNT, blk_size / 4)\n+\t\t\t\t| PMCI_FLASH_RD_MODE,\n+\t\t\tdev->mmio + PMCI_FLASH_CTRL);\n+\n+\t\tret = opae_readl_poll_timeout((dev->mmio + PMCI_FLASH_CTRL),\n+\t\t\t\tval, !(val & PMCI_FLASH_BUSY),\n+\t\t\t\tPMCI_FLASH_INT_US,\n+\t\t\t\tPMCI_FLASH_TIMEOUT_US);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"%s timed out on reading flash 0x%xn\",\n+\t\t\t\t__func__, val);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tpmci_read_fifo(dev->mmio + PMCI_FLASH_FIFO, (char *)buf + offset,\n+\t\t\t\tblk_size);\n+\n+\t\tsize -= blk_size;\n+\t\toffset += blk_size;\n+\n+\t\topae_writel(0, dev->mmio + PMCI_FLASH_CTRL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+pmci_flash_bulk_read(struct intel_max10_device *dev, u32 addr,\n+\t\t     void *buf, u32 size)\n+{\n+\tint ret;\n+\n+\tret = pmci_get_mux(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = __pmci_flash_bulk_read(dev, addr, buf, size);\n+\tif (ret)\n+\t\tgoto fail;\n+\n+\treturn pmci_put_mux(dev);\n+\n+fail:\n+\tpmci_put_mux(dev);\n+\treturn ret;\n+}\n+\n+static int pmci_check_flash_address(u32 start, u32 end)\n+{\n+\tif (start < PMCI_FLASH_START || end > PMCI_FLASH_END)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+int opae_read_flash(struct intel_max10_device *dev, u32 addr,\n+\t\tu32 size, void *buf)\n+{\n+\tint ret;\n+\n+\tif (!dev->bmc_ops.check_flash_range ||\n+\t\t\t!dev->bmc_ops.flash_read)\n+\t\treturn -ENODEV;\n+\n+\tif (!buf)\n+\t\treturn -EINVAL;\n+\n+\tret = dev->bmc_ops.check_flash_range(addr, addr + size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dev->bmc_ops.flash_read(dev, addr, buf, size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int max10_spi_read(struct intel_max10_device *dev,\n+\tunsigned int addr, unsigned int *val)\n+{\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tdev_debug(dev, \"%s: bus:0x%x, addr:0x%x\\n\", __func__, dev->bus, addr);\n+\n+\treturn spi_transaction_read(dev->spi_tran_dev,\n+\t\t\taddr, 4, (unsigned char *)val);\n+}\n+\n+static int max10_spi_write(struct intel_max10_device *dev,\n+\tunsigned int addr, unsigned int val)\n+{\n+\tunsigned int tmp = val;\n+\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tdev_debug(dev, \"%s: bus:0x%x, reg:0x%x, val:0x%x\\n\", __func__,\n+\t\t\tdev->bus, addr, val);\n+\n+\treturn spi_transaction_write(dev->spi_tran_dev,\n+\t\t\taddr, 4, (unsigned char *)&tmp);\n+}\n+\n+static int indirect_bus_clr_cmd(struct intel_max10_device *dev)\n+{\n+\tunsigned int cmd;\n+\tint ret;\n+\n+\topae_writel(0, dev->mmio + INDIRECT_CMD_OFF);\n+\n+\tret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd,\n+\t\t\t\t (!cmd), INDIRECT_INT_US, INDIRECT_TIMEOUT_US);\n+\n+\tif (ret)\n+\t\tdev_err(dev, \"%s timed out on clearing cmd 0x%x\\n\",\n+\t\t\t\t__func__, cmd);\n+\n+\treturn ret;\n+}\n+\n+static int max10_indirect_reg_read(struct intel_max10_device *dev,\n+\tunsigned int addr, unsigned int *val)\n+{\n+\tunsigned int cmd;\n+\tint ret;\n+\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tpthread_mutex_lock(dev->bmc_ops.mutex);\n+\n+\tcmd = opae_readl(dev->mmio + INDIRECT_CMD_OFF);\n+\tif (cmd)\n+\t\tdev_warn(dev, \"%s non-zero cmd 0x%x\\n\", __func__, cmd);\n+\n+\topae_writel(addr, dev->mmio + INDIRECT_ADDR_OFF);\n+\n+\topae_writel(INDIRECT_CMD_RD, dev->mmio + INDIRECT_CMD_OFF);\n+\n+\tret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd,\n+\t\t\t\t (cmd & INDIRECT_CMD_ACK), INDIRECT_INT_US,\n+\t\t\t\t INDIRECT_TIMEOUT_US);\n+\n+\t*val = opae_readl(dev->mmio + INDIRECT_RD_OFF);\n+\n+\tif (ret)\n+\t\tdev_err(dev, \"%s timed out on reg 0x%x cmd 0x%x\\n\",\n+\t\t\t\t__func__, addr, cmd);\n+\n+\tif (indirect_bus_clr_cmd(dev))\n+\t\tret = -ETIME;\n+\n+\tpthread_mutex_unlock(dev->bmc_ops.mutex);\n+\n+\treturn ret;\n+}\n+\n+static int max10_indirect_reg_write(struct intel_max10_device *dev,\n+\tunsigned int addr, unsigned int val)\n+{\n+\tunsigned int cmd;\n+\tint ret;\n+\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tpthread_mutex_lock(dev->bmc_ops.mutex);\n+\n+\tcmd = readl(dev->mmio + INDIRECT_CMD_OFF);\n+\n+\tif (cmd)\n+\t\tdev_warn(dev, \"%s non-zero cmd 0x%x\\n\", __func__, cmd);\n+\n+\topae_writel(val, dev->mmio + INDIRECT_WR_OFF);\n+\n+\topae_writel(addr, dev->mmio + INDIRECT_ADDR_OFF);\n+\n+\twritel(INDIRECT_CMD_WR, dev->mmio + INDIRECT_CMD_OFF);\n+\n+\tret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd,\n+\t\t\t\t (cmd & INDIRECT_CMD_ACK), INDIRECT_INT_US,\n+\t\t\t\t INDIRECT_TIMEOUT_US);\n+\n+\tif (ret)\n+\t\tdev_err(dev, \"%s timed out on reg 0x%x cmd 0x%x\\n\",\n+\t\t\t\t__func__, addr, cmd);\n+\n+\tif (indirect_bus_clr_cmd(dev))\n+\t\tret = -ETIME;\n+\n+\tpthread_mutex_unlock(dev->bmc_ops.mutex);\n+\n+\treturn ret;\n+}\n+\n+const struct m10bmc_regmap m10bmc_pmci_regmap = {\n+\t.reg_write = max10_indirect_reg_write,\n+\t.reg_read = max10_indirect_reg_read,\n+};\n+\n+const struct m10bmc_regmap m10bmc_n3000_regmap = {\n+\t.reg_write = max10_spi_write,\n+\t.reg_read = max10_spi_read,\n+};\n+\n static struct max10_compatible_id max10_id_table[] = {\n \t{.compatible = MAX10_PAC,},\n \t{.compatible = MAX10_PAC_N3000,},\n@@ -122,7 +509,7 @@ static int altera_nor_flash_read(struct intel_max10_device *dev,\n \tword_len = len/4;\n \n \tfor (i = 0; i < word_len; i++) {\n-\t\tret = max10_reg_read(dev, offset + i*4,\n+\t\tret = max10_sys_raw_read(dev, offset + i*4,\n \t\t\t\t&value);\n \t\tif (ret)\n \t\t\treturn -EBUSY;\n@@ -557,15 +944,13 @@ static int check_max10_version(struct intel_max10_device *dev)\n {\n \tunsigned int v;\n \n-\tif (!max10_reg_read(dev, MAX10_SEC_BASE_ADDR + MAX10_BUILD_VER,\n+\tif (!max10_sys_raw_read(dev, MAX10_SEC_BASE_ADDR + MAX10_BUILD_VER,\n \t\t\t\t&v)) {\n \t\tif (v != 0xffffffff) {\n \t\t\tdev_info(dev, \"secure MAX10 detected\\n\");\n-\t\t\tdev->base = MAX10_SEC_BASE_ADDR;\n \t\t\tdev->flags |= MAX10_FLAGS_SECURE;\n \t\t} else {\n \t\t\tdev_info(dev, \"non-secure MAX10 detected\\n\");\n-\t\t\tdev->base = MAX10_BASE_ADDR;\n \t\t}\n \t\treturn 0;\n \t}\n@@ -648,73 +1033,455 @@ static int max10_staging_area_init(struct intel_max10_device *dev)\n \treturn 0;\n }\n \n-struct intel_max10_device *\n-intel_max10_device_probe(struct altera_spi_device *spi,\n-\t\tint chipselect)\n+int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned int *val)\n {\n-\tstruct intel_max10_device *dev;\n \tint ret;\n-\tunsigned int val;\n+\tunsigned int value;\n \n-\tdev = opae_malloc(sizeof(*dev));\n-\tif (!dev)\n-\t\treturn NULL;\n+\t/* read FPGA loading information */\n+\tret = max10_sys_read(dev, dev->csr->fpga_page_info, &value);\n+\tif (ret) {\n+\t\tdev_err(dev, \"fail to get FPGA loading info\\n\");\n+\t\treturn ret;\n+\t}\n \n-\tTAILQ_INIT(&dev->opae_sensor_list);\n+\tif (dev->type == M10_N3000)\n+\t\t*val = value & 0x7;\n+\telse if (dev->type == M10_N6000) {\n+\t\tif (!GET_FIELD(PMCI_FPGA_CONFIGED, value))\n+\t\t\treturn -EINVAL;\n+\t\t*val = GET_FIELD(PMCI_FPGA_BOOT_PAGE, value);\n+\t}\n \n-\tdev->spi_master = spi;\n+\treturn 0;\n+}\n \n-\tdev->spi_tran_dev = spi_transaction_init(spi, chipselect);\n-\tif (!dev->spi_tran_dev) {\n-\t\tdev_err(dev, \"%s spi tran init fail\\n\", __func__);\n-\t\tgoto free_dev;\n-\t}\n+int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int *val)\n+{\n+\tint ret;\n \n-\t/* check the max10 version */\n-\tret = check_max10_version(dev);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to find max10 hardware!\\n\");\n-\t\tgoto free_dev;\n-\t}\n+\tret = max10_sys_read(dev, dev->csr->build_version, val);\n+\tif (ret)\n+\t\treturn ret;\n \n-\t/* load the MAX10 device table */\n-\tret = init_max10_device_table(dev);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Init max10 device table fail\\n\");\n-\t\tgoto free_dev;\n-\t}\n+\treturn 0;\n+}\n \n-\t/* init max10 devices, like sensor*/\n-\tif (dev->flags & MAX10_FLAGS_SECURE)\n-\t\tret = max10_secure_hw_init(dev);\n-\telse\n-\t\tret = max10_non_secure_hw_init(dev);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to init max10 hardware!\\n\");\n-\t\tgoto free_dtb;\n+int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned int *val)\n+{\n+\tint ret;\n+\n+\tret = max10_sys_read(dev, dev->csr->fw_version, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct m10bmc_csr m10bmc_spi_csr = {\n+\t.base = MAX10_SEC_BASE_ADDR,\n+\t.build_version = MAX10_BUILD_VER,\n+\t.fw_version = NIOS2_FW_VERSION,\n+\t.fpga_page_info = FPGA_PAGE_INFO,\n+\t.doorbell = MAX10_DOORBELL,\n+\t.auth_result = MAX10_AUTH_RESULT,\n+};\n+\n+static const struct m10bmc_csr m10bmc_pmci_csr = {\n+\t.base = M10BMC_PMCI_SYS_BASE,\n+\t.build_version = M10BMC_PMCI_BUILD_VER,\n+\t.fw_version = NIOS2_PMCI_FW_VERSION,\n+\t.fpga_page_info = M10BMC_PMCI_FPGA_CONF_STS,\n+\t.doorbell = M10BMC_PMCI_DOORBELL,\n+\t.auth_result = M10BMC_PMCI_AUTH_RESULT,\n+};\n+\n+static const struct max10_sensor_raw_data n6010bmc_temp_tbl[] = {\n+\t{ 0x444, 0x448, 0x44c, 0x0, 0x0, 500,\n+\t\t\"FPGA E-TILE Temperature #1\" },\n+\t{ 0x450, 0x454, 0x458, 0x0, 0x0, 500,\n+\t\t\"FPGA E-TILE Temperature #2\" },\n+\t{ 0x45c, 0x460, 0x464, 0x0, 0x0, 500,\n+\t\t\"FPGA E-TILE Temperature #3\" },\n+\t{ 0x468, 0x46c, 0x470, 0x0, 0x0, 500,\n+\t\t\"FPGA E-TILE Temperature #4\" },\n+\t{ 0x474, 0x478, 0x47c, 0x0, 0x0, 500,\n+\t\t\"FPGA P-TILE Temperature\" },\n+\t{ 0x484, 0x488, 0x48c, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Digital Temperature#1\" },\n+\t{ 0x490, 0x494, 0x498, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Digital Temperature#2\" },\n+\t{ 0x49c, 0x4a0, 0x4a4, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Digital Temperature#3\" },\n+\t{ 0x4a8, 0x4ac, 0x4b0, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Digital Temperature#4\" },\n+\t{ 0x4b4, 0x4b8, 0x4bc, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Digital Temperature#5\" },\n+\t{ 0x4c0, 0x4c4, 0x4c8, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Remote Digital Temperature#1\" },\n+\t{ 0x4cc, 0x4d0, 0x4d4, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Remote Digital Temperature#2\" },\n+\t{ 0x4d8, 0x4dc, 0x4e0, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Remote Digital Temperature#3\" },\n+\t{ 0x4e4, 0x4e8, 0x4ec, 0x0, 0x0, 500,\n+\t\t\"FPGA FABRIC Remote Digital Temperature#4\" },\n+\t{ 0x4f0, 0x4f4, 0x4f8, 0x0, 0x0, 500,\n+\t\t\"Board Top Near FPGA Temperature\" },\n+\t{ 0x4fc, 0x500, 0x504, 0x52c, 0x0, 500,\n+\t\t\"Board Bottom Near CVL Temperature\" },\n+\t{ 0x508, 0x50c, 0x510, 0x52c, 0x0, 500,\n+\t\t\"Board Top East Near VRs Temperature\" },\n+\t{ 0x514, 0x518, 0x51c, 0x52c, 0x0, 500,\n+\t\t\"Columbiaville Die Temperature\" },\n+\t{ 0x520, 0x524, 0x528, 0x52c, 0x0, 500,\n+\t\t\"Board Rear Side Temperature\" },\n+\t{ 0x530, 0x534, 0x538, 0x52c, 0x0, 500,\n+\t\t\"Board Front Side Temperature\" },\n+\t{ 0x53c, 0x540, 0x544, 0x0, 0x0, 500,\n+\t\t\"QSFP1 Temperature\" },\n+\t{ 0x548, 0x54c, 0x550, 0x0, 0x0, 500,\n+\t\t\"QSFP2 Temperature\" },\n+\t{ 0x554, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA Core Voltage Phase 0 VR Temperature\" },\n+\t{ 0x560, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA Core Voltage Phase 1 VR Temperature\" },\n+\t{ 0x56c, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA Core Voltage Phase 2 VR Temperature\" },\n+\t{ 0x578, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA Core Voltage VR Controller Temperature\" },\n+\t{ 0x584, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA VCCH VR Temperature\" },\n+\t{ 0x590, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA VCC_1V2 VR Temperature\" },\n+\t{ 0x59c, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"FPGA VCCH, VCC_1V2 VR Controller Temperature\" },\n+\t{ 0x5a8, 0x0, 0x0, 0x0, 0x0, 500,\n+\t\t\"3V3 VR Temperature\" },\n+\t{ 0x5b4, 0x5b8, 0x5bc, 0x0, 0x0, 500,\n+\t\t\"CVL Core Voltage VR Temperature\" },\n+\t{ 0x5c4, 0x5c8, 0x5cc, 0x5c0, 0x0, 500,\n+\t\t\"FPGA P-Tile Temperature [Remote]\" },\n+\t{ 0x5d0, 0x5d4, 0x5d8, 0x5c0, 0x0, 500,\n+\t\t\"FPGA E-Tile Temperature [Remote]\" },\n+\t{ 0x5dc, 0x5e0, 0x5e4, 0x5c0, 0x0, 500,\n+\t\t\"FPGA SDM Temperature [Remote]\" },\n+\t{ 0x5e8, 0x5ec, 0x5f0, 0x5c0, 0x0, 500,\n+\t\t\"FPGA Corner Temperature [Remote]\" },\n+};\n+\n+static const struct max10_sensor_data n6010bmc_tmp_data = {\n+\t.type = SENSOR_TMP_NAME,\n+\t.number = ARRAY_SIZE(n6010bmc_temp_tbl),\n+\t.table = n6010bmc_temp_tbl,\n+};\n+\n+static const struct max10_sensor_raw_data n6010bmc_in_tbl[] = {\n+\t{ 0x5f4, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"Inlet 12V PCIe Rail Voltage\" },\n+\t{ 0x60c, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"Inlet 12V Aux Rail Voltage\" },\n+\t{ 0x624, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"Inlet 3V3 PCIe Rail Voltage\" },\n+\t{ 0x63c, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA Core Voltage Rail Voltage\" },\n+\t{ 0x644, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCH Rail Voltage\" },\n+\t{ 0x64c, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCC_1V2 Rail Voltage\" },\n+\t{ 0x654, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage\" },\n+\t{ 0x664, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCIO_1V2 Voltage\" },\n+\t{ 0x674, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"CVL Non Core Rails Inlet Voltage\" },\n+\t{ 0x684, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"MAX10 & Board CLK PWR 3V3 Inlet Voltage\" },\n+\t{ 0x694, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"CVL Core Voltage Rail Voltage\" },\n+\t{ 0x6ac, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"Board 3V3 VR Voltage\" },\n+\t{ 0x6b4, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"QSFP 3V3 Rail Voltage\" },\n+\t{ 0x6c4, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"QSFP (Primary) Supply Rail Voltage\" },\n+\t{ 0x6c8, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"QSFP (Secondary) Supply Rail Voltage\" },\n+\t{ 0x6cc, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCCLK_GXER_2V5 Voltage\" },\n+\t{ 0x6d0, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"AVDDH_1V1_CVL Voltage\" },\n+\t{ 0x6d4, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VDDH_1V8_CVL Voltage\" },\n+\t{ 0x6d8, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCA_PLL Voltage\" },\n+\t{ 0x6e0, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCRT_GXER_0V9 Voltage\" },\n+\t{ 0x6e8, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCRT_GXEL_0V9 Voltage\" },\n+\t{ 0x6f0, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCH_GXPL_1V8 Voltage\" },\n+\t{ 0x6f4, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCPT_1V8 Voltage\" },\n+\t{ 0x6fc, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCC_3V3_M10 Voltage\" },\n+\t{ 0x700, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCC_1V8_M10 Voltage\" },\n+\t{ 0x704, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCC_1V2_EMIF1_2_3 Voltage\" },\n+\t{ 0x70c, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCC_1V2_EMIF4_5 Voltage\" },\n+\t{ 0x714, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCA_1V8 Voltage\" },\n+\t{ 0x718, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"VCCH_GXER_1V1 Voltage\" },\n+\t{ 0x71c, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"AVDD_ETH_0V9_CVL Voltage\" },\n+\t{ 0x720, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"AVDD_PCIE_0V9_CVL Voltage\" },\n+};\n+\n+static const struct max10_sensor_data n6010bmc_in_data = {\n+\t.type = SENSOR_IN_NAME,\n+\t.number = ARRAY_SIZE(n6010bmc_in_tbl),\n+\t.table = n6010bmc_in_tbl,\n+};\n+\n+static const struct max10_sensor_raw_data n6010bmc_curr_tbl[] = {\n+\t{ 0x600, 0x604, 0x608, 0x0, 0x0, 1,\n+\t\t\"Inlet 12V PCIe Rail Current\" },\n+\t{ 0x618, 0x61c, 0x620, 0x0, 0x0, 1,\n+\t\t\"Inlet 12V Aux Rail Current\" },\n+\t{ 0x630, 0x634, 0x638, 0x0, 0x0, 1,\n+\t\t\"Inlet 3V3 PCIe Rail Current\" },\n+\t{ 0x640, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA Core Voltage Rail Current\" },\n+\t{ 0x648, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCH Rail Current\" },\n+\t{ 0x650, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"FPGA VCC_1V2 Rail Current\" },\n+\t{ 0x658, 0x65c, 0x660, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCH_GXER_1V1, VCCA_1V8 Current\" },\n+\t{ 0x668, 0x66c, 0x670, 0x0, 0x0, 1,\n+\t\t\"FPGA VCCIO_1V2 Current\" },\n+\t{ 0x678, 0x67c, 0x680, 0x0, 0x0, 1,\n+\t\t\"CVL Non Core Rails Inlet Current\" },\n+\t{ 0x688, 0x68c, 0x680, 0x0, 0x0, 1,\n+\t\t\"MAX10 & Board CLK PWR 3V3 Inlet Current\" },\n+\t{ 0x690, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"CVL Core Voltage Rail Current\" },\n+\t{ 0x6b0, 0x0, 0x0, 0x0, 0x0, 1,\n+\t\t\"Board 3V3 VR Current\" },\n+\t{ 0x6b8, 0x6bc, 0x670, 0x0, 0x0, 1,\n+\t\t\"QSFP 3V3 Rail Current\" },\n+};\n+\n+static const struct max10_sensor_data n6010bmc_curr_data = {\n+\t.type = SENSOR_CURR_NAME,\n+\t.number = ARRAY_SIZE(n6010bmc_curr_tbl),\n+\t.table = n6010bmc_curr_tbl,\n+};\n+\n+static const struct max10_sensor_raw_data n6010bmc_power_tbl[] = {\n+\t{ 0x724, 0x0, 0x0, 0x0, 0x0, 1000, \"Board Power\" },\n+};\n+\n+static const struct max10_sensor_data n6010bmc_power_data = {\n+\t.type = SENSOR_POWER_NAME,\n+\t.number = ARRAY_SIZE(n6010bmc_power_tbl),\n+\t.table = n6010bmc_power_tbl,\n+};\n+\n+static const struct max10_sensor_board_data n6010bmc_sensor_board_data = {\n+\t.tables = {\n+\t\t[sensor_temp] = &n6010bmc_tmp_data,\n+\t\t[sensor_in] = &n6010bmc_in_data,\n+\t\t[sensor_curr] = &n6010bmc_curr_data,\n+\t\t[sensor_power] = &n6010bmc_power_data,\n+\t},\n+};\n+\n+static int get_sensor_data(struct intel_max10_device *dev,\n+\t\tstruct opae_sensor_info *sensor,\n+\t\tunsigned int *value,\n+\t\tunsigned int reg,\n+\t\tunsigned int flags)\n+{\n+\tint ret;\n+\tunsigned int data;\n+\n+\tif (!reg)\n+\t\treturn 0;\n+\n+\tret = max10_sys_read(dev, reg, &data);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (data == SENSOR_INVALID) {\n+\t\tdev_debug(dev, \"%s: sensor:%s invalid 0x%x at:%d\\n\",\n+\t\t\t\t__func__, sensor->name, data, reg);\n+\t\treturn ret;\n \t}\n \n-\t/* read FPGA loading information */\n-\tret = max10_sys_read(dev, FPGA_PAGE_INFO, &val);\n-\tif (ret) {\n-\t\tdev_err(dev, \"fail to get FPGA loading info\\n\");\n-\t\tgoto release_max10_hw;\n+\t*value = data * sensor->multiplier;\n+\tsensor->flags |= flags;\n+\n+\treturn 0;\n+}\n+\n+static int max10_parse_sensor_data(struct intel_max10_device *dev,\n+\t\tconst struct max10_sensor_data *sdata)\n+{\n+\tstruct opae_sensor_info *sensor;\n+\tconst struct max10_sensor_raw_data *raw;\n+\tconst struct max10_sensor_raw_data *table =\n+\t\t(const struct max10_sensor_raw_data *)sdata->table;\n+\tunsigned int i;\n+\tstatic unsigned int sensor_id;\n+\tint ret = 0;\n+\n+\tfor (i = 0; i < sdata->number; i++) {\n+\t\traw = &table[i];\n+\n+\t\tsensor = opae_zmalloc(sizeof(*sensor));\n+\t\tif (!sensor) {\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto free_sensor;\n+\t\t}\n+\n+\t\tsensor->type = sdata->type;\n+\t\tsensor->id = sensor_id++;\n+\n+\t\tif (!raw->reg_input)\n+\t\t\tcontinue;\n+\n+\t\tsensor->value_reg = raw->reg_input;\n+\t\tsensor->multiplier = raw->multiplier;\n+\t\tsensor->name = raw->label;\n+\n+\t\tret = get_sensor_data(dev, sensor,\n+\t\t\t\t&sensor->high_warn,\n+\t\t\t\traw->reg_high_warn,\n+\t\t\t\tOPAE_SENSOR_HIGH_WARN_VALID);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tret = get_sensor_data(dev, sensor,\n+\t\t\t\t&sensor->high_fatal,\n+\t\t\t\traw->reg_high_fatal,\n+\t\t\t\tOPAE_SENSOR_HIGH_FATAL_VALID);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tret = get_sensor_data(dev, sensor,\n+\t\t\t\t&sensor->hysteresis,\n+\t\t\t\traw->reg_hyst,\n+\t\t\t\tOPAE_SENSOR_HYSTERESIS_VALID);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tret = get_sensor_data(dev, sensor,\n+\t\t\t\t&sensor->low_warn,\n+\t\t\t\traw->reg_low_warn,\n+\t\t\t\tOPAE_SENSOR_LOW_WARN_VALID);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tsensor->flags |= OPAE_SENSOR_VALID;\n+\n+\t\tTAILQ_INSERT_TAIL(&dev->opae_sensor_list, sensor, node);\n+\t\tdev_info(dev, \"found valid sensor: %s\\n\", sensor->name);\n \t}\n-\tdev_info(dev, \"FPGA loaded from %s Image\\n\", val ? \"User\" : \"Factory\");\n \n-\treturn dev;\n+\treturn ret;\n \n-release_max10_hw:\n+free_sensor:\n \tmax10_sensor_uinit(dev);\n-free_dtb:\n-\tif (dev->fdt_root)\n-\t\topae_free(dev->fdt_root);\n-\tif (dev->spi_tran_dev)\n-\t\tspi_transaction_remove(dev->spi_tran_dev);\n-free_dev:\n-\topae_free(dev);\n+\treturn ret;\n+}\n \n-\treturn NULL;\n+static int max10_sensor_init_table(struct intel_max10_device *dev,\n+\t\tconst struct max10_sensor_board_data *data)\n+{\n+\tint ret = 0;\n+\tunsigned int i;\n+\tconst struct max10_sensor_data *sdata;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(data->tables); i++) {\n+\t\tsdata = data->tables[i];\n+\t\tif (!sdata)\n+\t\t\tcontinue;\n+\t\tret = max10_parse_sensor_data(dev, sdata);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int\n+intel_max10_device_init(struct intel_max10_device *dev)\n+{\n+\tint ret = 0;\n+\n+\tTAILQ_INIT(&dev->opae_sensor_list);\n+\n+\n+\tif (dev->type == M10_N3000) {\n+\t\tdev->ops = &m10bmc_n3000_regmap;\n+\t\tdev->csr = &m10bmc_spi_csr;\n+\n+\t\tdev->raw_blk_ops.write_blk = n3000_bulk_raw_write;\n+\t\tdev->raw_blk_ops.read_blk = n3000_bulk_raw_read;\n+\t\tdev->bmc_ops.flash_read = n3000_flash_read;\n+\t\tdev->bmc_ops.flash_write = n3000_flash_write;\n+\n+\t\t/* check the max10 version */\n+\t\tret = check_max10_version(dev);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to find max10 hardware!\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* load the MAX10 device table */\n+\t\tret = init_max10_device_table(dev);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Init max10 device table fail\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* init max10 devices, like sensor*/\n+\t\tif (dev->flags & MAX10_FLAGS_SECURE)\n+\t\t\tret = max10_secure_hw_init(dev);\n+\t\telse\n+\t\t\tret = max10_non_secure_hw_init(dev);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to init max10 hardware!\\n\");\n+\t\t\topae_free(dev->fdt_root);\n+\t\t\treturn ret;\n+\t\t}\n+\t} else if (dev->type == M10_N6000) {\n+\t\tdev->ops = &m10bmc_pmci_regmap;\n+\t\tdev->csr = &m10bmc_pmci_csr;\n+\t\tdev->staging_area_size = MAX_STAGING_AREA_SIZE;\n+\t\tdev->flags |= MAX10_FLAGS_SECURE;\n+\n+\t\tdev->bmc_ops.flash_read = pmci_flash_bulk_read;\n+\t\tdev->bmc_ops.flash_write = pmci_flash_bulk_write;\n+\t\tdev->bmc_ops.check_flash_range = pmci_check_flash_address;\n+\n+\t\tret = max10_sensor_init_table(dev, &n6010bmc_sensor_board_data);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = pthread_mutex_init(&dev->bmc_ops.lock, NULL);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (!dev->bmc_ops.mutex)\n+\t\t\tdev->bmc_ops.mutex = &dev->bmc_ops.lock;\n+\t}\n+\n+\treturn ret;\n }\n \n int intel_max10_device_remove(struct intel_max10_device *dev)\n@@ -722,15 +1489,14 @@ int intel_max10_device_remove(struct intel_max10_device *dev)\n \tif (!dev)\n \t\treturn 0;\n \n-\tmax10_sensor_uinit(dev);\n+\tpthread_mutex_destroy(&dev->bmc_ops.lock);\n \n-\tif (dev->spi_tran_dev)\n-\t\tspi_transaction_remove(dev->spi_tran_dev);\n+\tif (dev->type == M10_N3000) {\n+\t\tmax10_sensor_uinit(dev);\n \n-\tif (dev->fdt_root)\n-\t\topae_free(dev->fdt_root);\n-\n-\topae_free(dev);\n+\t\tif (dev->fdt_root)\n+\t\t\topae_free(dev->fdt_root);\n+\t}\n \n \treturn 0;\n }\ndiff --git a/drivers/raw/ifpga/base/opae_intel_max10.h b/drivers/raw/ifpga/base/opae_intel_max10.h\nindex e761d7e..ead48ea 100644\n--- a/drivers/raw/ifpga/base/opae_intel_max10.h\n+++ b/drivers/raw/ifpga/base/opae_intel_max10.h\n@@ -7,6 +7,9 @@\n \n #include \"opae_osdep.h\"\n #include \"opae_spi.h\"\n+#include \"ifpga_compat.h\"\n+\n+struct intel_max10_device;\n \n struct max10_compatible_id {\n \tchar compatible[128];\n@@ -29,6 +32,64 @@ struct max10_compatible_id {\n /** List of opae sensors */\n TAILQ_HEAD(opae_sensor_list, opae_sensor_info);\n \n+/* Supported MAX10 BMC types */\n+enum m10bmc_type {\n+\tM10_N3000,\n+\tM10_N6000\n+};\n+\n+struct regmap_range {\n+\tunsigned int min;\n+\tunsigned int max;\n+};\n+\n+struct m10bmc_regmap {\n+\tint (*reg_write)(struct intel_max10_device *dev,\n+\t\t\tunsigned int reg, unsigned int val);\n+\tint (*reg_read)(struct intel_max10_device *dev,\n+\t\t\tunsigned int reg, unsigned int *val);\n+\tconst struct regmap_range *range;\n+\tint num_ranges;\n+};\n+\n+struct m10bmc_csr {\n+\tunsigned int base;\n+\tunsigned int build_version;\n+\tunsigned int fw_version;\n+\tunsigned int fpga_page_info;\n+\tunsigned int doorbell;\n+\tunsigned int auth_result;\n+};\n+\n+/**\n+ * struct flash_raw_blk_ops - device specific operations for flash R/W\n+ * @write_blk: write a block of data to flash\n+ * @read_blk: read a block of data from flash\n+ */\n+struct flash_raw_blk_ops {\n+\tint (*write_blk)(struct intel_max10_device *dev, uint32_t addr,\n+\t\t\tvoid *buf, uint32_t size);\n+\tint (*read_blk)(struct intel_max10_device *dev, uint32_t addr,\n+\t\t\tvoid *buf, uint32_t size);\n+};\n+\n+/**\n+ * struct m10bmc_ops - device specific operations\n+ * @lock: prevent concurrent flash read/write\n+ * @mutex: prevent concurrent bmc read/write\n+ * @flash_read: read a block of data from flash\n+ * @flash_write: write a block of data to flash\n+ */\n+struct m10bmc_ops {\n+\tpthread_mutex_t lock;\n+\tpthread_mutex_t *mutex;\n+\tint (*check_flash_range)(u32 start, u32 end);\n+\tint (*flash_read)(struct intel_max10_device *dev, u32 addr,\n+\t\t\tvoid *buf, u32 size);\n+\tint (*flash_write)(struct intel_max10_device *dev, u32 addr,\n+\t\t\tvoid *buf, u32 size);\n+};\n+\n struct intel_max10_device {\n \tunsigned int flags; /*max10 hardware capability*/\n \tstruct altera_spi_device *spi_master;\n@@ -40,6 +101,12 @@ struct intel_max10_device {\n \tstruct opae_sensor_list opae_sensor_list;\n \tu32 staging_area_base;\n \tu32 staging_area_size;\n+\tenum m10bmc_type type;\n+\tconst struct m10bmc_regmap *ops;\n+\tconst struct m10bmc_csr *csr;\n+\tstruct flash_raw_blk_ops raw_blk_ops;\n+\tstruct m10bmc_ops bmc_ops;\n+\tu8 *mmio; /* mmio address for PMCI */\n };\n \n /* retimer speed */\n@@ -87,6 +154,7 @@ struct opae_retimer_status {\n /* System Registers */\n #define MAX10_BASE_ADDR\t\t0x300400\n #define MAX10_SEC_BASE_ADDR\t0x300800\n+\n /* Register offset of system registers */\n #define NIOS2_FW_VERSION\t0x0\n #define MAX10_MACADDR1\t\t0x10\n@@ -151,6 +219,32 @@ struct opae_retimer_status {\n #define   SEC_STATUS_NON_INC\t\t0x6\n #define   SEC_STATUS_ERASE_FAIL\t\t0x7\n #define   SEC_STATUS_WEAROUT\t\t0x8\n+#define   SEC_STATUS_PMCI_SS_FAIL           0x9\n+#define   SEC_STATUS_FLASH_CMD              0xa\n+#define   SEC_STATUS_FACTORY_UNVERITY       0xb\n+#define   SEC_STATUS_FACTORY_ACTIVE         0xc\n+#define   SEC_STATUS_POWER_DOWN             0xd\n+#define   SEC_STATUS_CANCELLATION           0xe\n+#define   SEC_STATUS_HASH                   0xf\n+#define   SEC_STATUS_FLASH_ACCESS           0x10\n+#define   SEC_STATUS_SDM_PR_CERT            0x20\n+#define   SEC_STATUS_SDM_PR_NIOS_BUSY       0x21\n+#define   SEC_STATUS_SDM_PR_TIMEOUT         0x22\n+#define   SEC_STATUS_SDM_PR_FAILED          0x23\n+#define   SEC_STATUS_SDM_PR_MISMATCH        0x24\n+#define   SEC_STATUS_SDM_PR_FLUSH           0x25\n+#define   SEC_STATUS_SDM_SR_CERT            0x30\n+#define   SEC_STATUS_SDM_SR_NIOS_BUSY       0x31\n+#define   SEC_STATUS_SDM_SR_TIMEOUT         0x32\n+#define   SEC_STATUS_SDM_SR_FAILED          0x33\n+#define   SEC_STATUS_SDM_SR_MISMATCH        0x34\n+#define   SEC_STATUS_SDM_SR_FLUSH           0x35\n+#define   SEC_STATUS_SDM_KEY_CERT           0x40\n+#define   SEC_STATUS_SDM_KEY_NIOS_BUSY      0x41\n+#define   SEC_STATUS_SDM_KEY_TIMEOUT        0x42\n+#define   SEC_STATUS_SDM_KEY_FAILED         0x43\n+#define   SEC_STATUS_SDM_KEY_MISMATCH       0x44\n+#define   SEC_STATUS_SDM_KEY_FLUSH          0x45\n #define   SEC_STATUS_NIOS_OK\t\t0x80\n #define   SEC_STATUS_USER_OK\t\t0x81\n #define   SEC_STATUS_FACTORY_OK\t\t0x82\n@@ -158,9 +252,65 @@ struct opae_retimer_status {\n #define   SEC_STATUS_FACTORY_FAIL\t0x84\n #define   SEC_STATUS_NIOS_FLASH_ERR\t0x85\n #define   SEC_STATUS_FPGA_FLASH_ERR\t0x86\n+#define   SEC_STATUS_MAX   SEC_STATUS_FPGA_FLASH_ERR\n+\n+/* Authentication status */\n+#define SEC_AUTH_G(v)\t((v) & 0xff)\n+#define AUTH_STAT_PASS    0x0\n+#define AUTH_STAT_B0_MAGIC   0x1\n+#define AUTH_STAT_CONLEN  0x2\n+#define AUTH_STAT_CONTYPE 0x3\n+#define AUTH_STAT_B1_MAGIC 0x4\n+#define AUTH_STAT_ROOT_MAGIC 0x5\n+#define AUTH_STAT_CURVE_MAGIC 0x6\n+#define AUTH_STAT_PERMISSION 0x7\n+#define AUTH_STAT_KEY_ID    0x8\n+#define AUTH_STAT_CSK_MAGIC 0x9\n+#define AUTH_STAT_CSK_CURVE 0xa\n+#define AUTH_STAT_CSK_PERMISSION 0xb\n+#define AUTH_STAT_CSK_ID    0xc\n+#define AUTH_STAT_CSK_SM 0xd\n+#define AUTH_STAT_B0_E_MAGIC 0xe\n+#define AUTH_STAT_B0_E_SIGN 0xf\n+#define AUTH_STAT_RK_P      0x10\n+#define AUTH_STAT_RE_SHA    0x11\n+#define AUTH_STAT_CSK_SHA   0x12\n+#define AUTH_STAT_B0_SHA    0x13\n+#define AUTH_STAT_KEY_INV   0x14\n+#define AUTH_STAT_KEY_CAN   0x15\n+#define AUTH_STAT_UP_SHA    0x16\n+#define AUTH_STAT_CAN_SHA   0x17\n+#define AUTH_STAT_HASH      0x18\n+#define AUTH_STAT_INV_ID    0x19\n+#define AUTH_STAT_KEY_PROG  0x1a\n+#define AUTH_STAT_INV_BC    0x1b\n+#define AUTH_STAT_INV_SLOT  0x1c\n+#define AUTH_STAT_IN_OP     0x1d\n+#define AUTH_STAT_TIME_OUT  0X1e\n+#define AUTH_STAT_SHA_TO    0x1f\n+#define AUTH_STAT_CSK_TO    0x20\n+#define AUTH_STAT_B0_TO     0x21\n+#define AUTH_STAT_UP_TO     0x22\n+#define AUTH_STAT_CAN_TO    0x23\n+#define AUTH_STAT_HASH_TO   0x24\n+#define AUTH_STAT_AUTH_IDLE 0xfe\n+#define AUTH_STAT_GA_FAIL   0xff\n+#define AUTH_STAT_S_ERR     0x8000\n+#define AUTH_STAT_S_MN      0x8001\n+#define AUTH_STAT_SH_CRC     0x8002\n+#define AUTH_STAT_SD_CRC    0x8003\n+#define AUTH_STAT_SD_LEN    0x8004\n+#define AUTH_STAT_S_ID      0x8005\n+#define AUTH_STAT_S_THR    0x8006\n+#define AUTH_STAT_S_TO      0x8007\n+#define AUTH_STAT_S_EN     0x8008\n+#define AUTH_STAT_SF       0x8009\n+#define AUTH_STAT_MAX    AUTH_STAT_SF\n+\n #define   CONFIG_SEL\t\tBIT(28)\n #define   CONFIG_SEL_S(v)\t(((v) & 0x1) << 28)\n #define   REBOOT_REQ\t\tBIT(29)\n+#define   REBOOT_DISABLED\tBIT(30)\n #define MAX10_AUTH_RESULT\t0x404\n \n /* PKVL related registers, in system register region */\n@@ -185,22 +335,26 @@ struct opae_retimer_status {\n #define MAX_STAGING_AREA_BASE\t0xffffffff\n #define MAX_STAGING_AREA_SIZE\t0x3800000\n \n-int max10_reg_read(struct intel_max10_device *dev,\n-\tunsigned int reg, unsigned int *val);\n-int max10_reg_write(struct intel_max10_device *dev,\n-\tunsigned int reg, unsigned int val);\n+#define m10bmc_base(max10) ((max10)->csr->base)\n+#define doorbell_reg(max10) ((max10)->csr->doorbell)\n+#define auth_result_reg(max10) ((max10)->csr->auth_result)\n+\n int max10_sys_read(struct intel_max10_device *dev,\n \tunsigned int offset, unsigned int *val);\n int max10_sys_write(struct intel_max10_device *dev,\n \tunsigned int offset, unsigned int val);\n+int max10_sys_raw_read(struct intel_max10_device *dev,\n+\tunsigned int offset, unsigned int *val);\n+int max10_sys_raw_write(struct intel_max10_device *dev,\n+\tunsigned int offset, unsigned int val);\n int max10_sys_update_bits(struct intel_max10_device *dev,\n \tunsigned int offset, unsigned int msk, unsigned int val);\n-struct intel_max10_device *\n-intel_max10_device_probe(struct altera_spi_device *spi,\n-\t\tint chipselect);\n+int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned int *val);\n+int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int *val);\n+int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned int *val);\n+int intel_max10_device_init(struct intel_max10_device *dev);\n int intel_max10_device_remove(struct intel_max10_device *dev);\n \n-\n #define SENSOR_REG_VALUE 0x0\n #define SENSOR_REG_HIGH_WARN 0x1\n #define SENSOR_REG_HIGH_FATAL 0x2\n@@ -254,4 +408,147 @@ struct opae_sensor_info {\n \tunsigned int value_reg;\n };\n \n+#define SENSOR_INVALID 0xdeadbeef\n+\n+struct max10_sensor_raw_data {\n+\tunsigned int reg_input;\n+\tunsigned int reg_high_warn;\n+\tunsigned int reg_high_fatal;\n+\tunsigned int reg_hyst;\n+\tunsigned int reg_low_warn;\n+\tunsigned int multiplier;\n+\tconst char *label;\n+};\n+\n+struct max10_sensor_data {\n+\tconst char *type;\n+\tunsigned int number;\n+\tconst struct max10_sensor_raw_data *table;\n+};\n+\n+enum max10_sensor_types {\n+\tsensor_temp,\n+\tsensor_in,\n+\tsensor_curr,\n+\tsensor_power,\n+\tsensor_max,\n+};\n+\n+#define SENSOR_TMP_NAME \"Temperature\"\n+#define SENSOR_IN_NAME \"Voltage\"\n+#define SENSOR_CURR_NAME \"Current\"\n+#define SENSOR_POWER_NAME \"Power\"\n+\n+struct max10_sensor_board_data {\n+\tconst struct max10_sensor_data *tables[sensor_max];\n+};\n+\n+/* indirect access for PMCI */\n+#define PMCI_INDIRECT_BASE 0x400\n+#define INDIRECT_CMD_OFF   (PMCI_INDIRECT_BASE + 0x0)\n+#define INDIRECT_CMD_RD\tBIT(0)\n+#define INDIRECT_CMD_WR\tBIT(1)\n+#define INDIRECT_CMD_ACK\tBIT(2)\n+\n+#define INDIRECT_ADDR_OFF\t (PMCI_INDIRECT_BASE + 0x4)\n+#define INDIRECT_RD_OFF\t         (PMCI_INDIRECT_BASE + 0x8)\n+#define INDIRECT_WR_OFF\t (PMCI_INDIRECT_BASE + 0xc)\n+\n+#define INDIRECT_INT_US\t1\n+#define INDIRECT_TIMEOUT_US\t10000\n+\n+#define M10BMC_PMCI_SYS_BASE 0x0\n+#define M10BMC_PMCI_SYS_END  0xfff\n+\n+#define M10BMC_PMCI_BUILD_VER   0x0\n+#define NIOS2_PMCI_FW_VERSION   0x4\n+\n+#define M10BMC_PMCI_PWR_STATE 0xb4\n+#define PMCI_PRIMARY_IMAGE_PAGE GENMASK(10, 8)\n+\n+#define M10BMC_PMCI_DOORBELL 0x1c0\n+#define PMCI_DRBL_REBOOT_DISABLED BIT(1)\n+#define M10BMC_PMCI_AUTH_RESULT 0x1c4\n+\n+#define M10BMC_PMCI_MAX10_RECONF 0xfc\n+#define PMCI_MAX10_REBOOT_REQ BIT(0)\n+#define PMCI_MAX10_REBOOT_PAGE BIT(1)\n+\n+#define M10BMC_PMCI_FPGA_RECONF 0xb8\n+#define PMCI_FPGA_RECONF_PAGE  GENMASK(22, 20)\n+#define PMCI_FPGA_RP_LOAD      BIT(23)\n+\n+#define PMCI_FLASH_CTRL 0x40\n+#define PMCI_FLASH_WR_MODE BIT(0)\n+#define PMCI_FLASH_RD_MODE BIT(1)\n+#define PMCI_FLASH_BUSY    BIT(2)\n+#define PMCI_FLASH_FIFO_SPACE GENMASK(13, 4)\n+#define PMCI_FLASH_READ_COUNT GENMASK(25, 16)\n+\n+#define PMCI_FLASH_INT_US       1\n+#define PMCI_FLASH_TIMEOUT_US   10000\n+\n+#define PMCI_FLASH_ADDR 0x44\n+#define PMCI_FLASH_FIFO 0x800\n+#define PMCI_READ_BLOCK_SIZE 0x800\n+#define PMCI_FIFO_MAX_BYTES 0x800\n+#define PMCI_FIFO_MAX_WORDS (PMCI_FIFO_MAX_BYTES / 4)\n+\n+#define M10BMC_PMCI_FPGA_POC\t0xb0\n+#define PMCI_FPGA_POC\t\tBIT(0)\n+#define PMCI_NIOS_REQ_CLEAR\tBIT(1)\n+#define PMCI_NIOS_STATUS\tGENMASK(5, 4)\n+#define NIOS_STATUS_IDLE\t0\n+#define NIOS_STATUS_SUCCESS\t1\n+#define NIOS_STATUS_FAIL\t2\n+#define PMCI_USER_IMAGE_PAGE\tGENMASK(10, 8)\n+#define POC_USER_IMAGE_1\t1\n+#define POC_USER_IMAGE_2\t2\n+#define PMCI_FACTORY_IMAGE_SEL\tBIT(31)\n+\n+#define M10BMC_PMCI_FPGA_CONF_STS 0xa0\n+#define PMCI_FPGA_BOOT_PAGE  GENMASK(2, 0)\n+#define PMCI_FPGA_CONFIGED   BIT(3)\n+\n+#define M10BMC_PMCI_FLASH_CTRL 0x1d0\n+#define FLASH_MUX_SELECTION GENMASK(2, 0)\n+#define FLASH_MUX_IDLE 0\n+#define FLASH_MUX_NIOS 1\n+#define FLASH_MUX_HOST 2\n+#define FLASH_MUX_PFL  4\n+#define get_flash_mux(mux)  GET_FIELD(FLASH_MUX_SELECTION, mux)\n+#define FLASH_NIOS_REQUEST BIT(4)\n+#define FLASH_HOST_REQUEST BIT(5)\n+\n+#define M10BMC_PMCI_SDM_CTRL_STS 0x230\n+#define PMCI_SDM_IMG_REQ\tBIT(0)\n+#define PMCI_SDM_STAT GENMASK(23, 16)\n+\n+#define SDM_STAT_DONE    0x0\n+#define SDM_STAT_PROV    0x1\n+#define SDM_STAT_BUSY    0x2\n+#define SDM_STAT_INV     0x3\n+#define SDM_STAT_FAIL    0x4\n+#define SDM_STAT_BMC_BUSY 0x5\n+#define SDM_STAT_TO      0x6\n+#define SDM_STAT_DB      0x7\n+#define SDM_STAT_CON_R    0x8\n+#define SDM_STAT_CON_E    0x9\n+#define SDM_STAT_WAIT     0xa\n+#define SDM_STAT_RTO      0xb\n+#define SDM_STAT_SB       0xc\n+#define SDM_STAT_RE       0xd\n+#define SDM_STAT_PDD     0xe\n+#define SDM_STAT_ISC     0xf\n+#define SDM_STAT_SIC     0x10\n+#define SDM_STAT_NO_PROV  0x11\n+#define SDM_STAT_CS_MIS   0x12\n+#define SDM_STAT_PR_MIS   0x13\n+#define SDM_STAT_MAX SDM_STAT_PR_MIS\n+\n+#define PMCI_FLASH_START 0x10000\n+#define PMCI_FLASH_END 0xC7FFFFF\n+\n+int opae_read_flash(struct intel_max10_device *dev, u32 addr,\n+\t\tu32 size, void *buf);\n #endif\ndiff --git a/drivers/raw/ifpga/base/opae_osdep.h b/drivers/raw/ifpga/base/opae_osdep.h\nindex 18e6a11..033b7e0 100644\n--- a/drivers/raw/ifpga/base/opae_osdep.h\n+++ b/drivers/raw/ifpga/base/opae_osdep.h\n@@ -79,15 +79,38 @@ struct uuid {\n #define time_before(a, b)\ttime_after(b, a)\n #define opae_memset(a, b, c)    memset((a), (b), (c))\n \n-#define opae_readq_poll_timeout(addr, val, cond, invl, timeout)\\\n-({\t\t\t\t\t\t\t\t\t     \\\n-\tint wait = 0;\t\t\t\t\t\t\t     \\\n-\tfor (; wait <= timeout; wait += invl) {\t\t\t     \\\n-\t\t(val) = opae_readq(addr);\t\t\t\t     \\\n-\t\tif (cond)                  \\\n-\t\t\tbreak;\t\t\t\t\t\t     \\\n-\t\tudelay(invl);\t\t\t\t\t\t     \\\n-\t}\t\t\t\t\t\t\t\t     \\\n-\t(cond) ? 0 : -ETIMEDOUT;\t  \\\n+#define readx_poll_timeout(op, val, cond, invl, timeout, args...) \\\n+({                                                                \\\n+\tunsigned long __wait = 0;                                     \\\n+\tunsigned long __invl = (invl);                                \\\n+\tunsigned long __timeout = (timeout);                          \\\n+\tfor (; __wait <= __timeout; __wait += __invl) {               \\\n+\t\t(val) = op(args);                                         \\\n+\t\tif (cond)                                                 \\\n+\t\t\tbreak;                                                \\\n+\t\tudelay(__invl);                                           \\\n+\t}                                                             \\\n+\t(cond) ? 0 : -ETIMEDOUT;                                      \\\n })\n+\n+#define opae_readq_poll_timeout(addr, val, cond, invl, timeout) \\\n+\treadx_poll_timeout(opae_readq, val, cond, invl, timeout, addr)\n+\n+#define opae_readl_poll_timeout(addr, val, cond, invl, timeout) \\\n+\treadx_poll_timeout(opae_readl, val, cond, invl, timeout, addr)\n+\n+#define opae_readw_poll_timeout(addr, val, cond, invl, timeout) \\\n+\treadx_poll_timeout(opae_readw, val, cond, invl, timeout, addr)\n+\n+#define opae_readb_poll_timeout(addr, val, cond, invl, timeout) \\\n+\treadx_poll_timeout(opae_readb, val, cond, invl, timeout, addr)\n+\n+#define opae_max10_read_poll_timeout(dev, addr, value, cond, invl, timeout) \\\n+({ \\\n+\tint __ret, __tmp; \\\n+\t__tmp = readx_poll_timeout(max10_sys_read, __ret, __ret || (cond), \\\n+\t\t\tinvl, timeout, (dev), (addr), &(value)); \\\n+\t__ret?:__tmp; \\\n+})\n+\n #endif\ndiff --git a/drivers/raw/ifpga/base/osdep_rte/osdep_generic.h b/drivers/raw/ifpga/base/osdep_rte/osdep_generic.h\nindex 3ff49a8..68499e6 100644\n--- a/drivers/raw/ifpga/base/osdep_rte/osdep_generic.h\n+++ b/drivers/raw/ifpga/base/osdep_rte/osdep_generic.h\n@@ -39,6 +39,16 @@\n #define min(a, b) RTE_MIN(a, b)\n #define max(a, b) RTE_MAX(a, b)\n \n+#define min_t(type, x, y) ({                    \\\n+\ttype __min1 = (x);                      \\\n+\ttype __min2 = (y);                      \\\n+\t__min1 < __min2 ? __min1 : __min2; })\n+\n+#define max_t(type, x, y) ({                    \\\n+\ttype __max1 = (x);                      \\\n+\ttype __max2 = (y);                      \\\n+\t__max1 > __max2 ? __max1 : __max2; })\n+\n #define spinlock_t rte_spinlock_t\n #define spinlock_init(x) rte_spinlock_init(x)\n #define spinlock_lock(x) rte_spinlock_lock(x)\n",
    "prefixes": [
        "v1",
        "1/2"
    ]
}