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GET /api/patches/111067/?format=api
{ "id": 111067, "url": "https://patches.dpdk.org/api/patches/111067/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220512131036.507178-1-marcinx.danilewicz@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220512131036.507178-1-marcinx.danilewicz@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220512131036.507178-1-marcinx.danilewicz@intel.com", "date": "2022-05-12T13:10:36", "name": "[v2] sched: enable CMAN at runtime", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a6fbae7236b75210824e5c01b65029568cee3db6", "submitter": { "id": 1988, "url": "https://patches.dpdk.org/api/people/1988/?format=api", "name": "Danilewicz, MarcinX", "email": "marcinx.danilewicz@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220512131036.507178-1-marcinx.danilewicz@intel.com/mbox/", "series": [ { "id": 22914, "url": "https://patches.dpdk.org/api/series/22914/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22914", "date": "2022-05-12T13:10:36", "name": "[v2] sched: enable CMAN at runtime", "version": 2, "mbox": "https://patches.dpdk.org/series/22914/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/111067/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/111067/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 26F1BA00C3;\n\tThu, 12 May 2022 15:10:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09A17410EF;\n\tThu, 12 May 2022 15:10:46 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 7AAB240E64\n for <dev@dpdk.org>; Thu, 12 May 2022 15:10:44 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 May 2022 06:10:43 -0700", "from silpixa00400629.ir.intel.com ([10.237.213.88])\n by orsmga006.jf.intel.com with ESMTP; 12 May 2022 06:10:41 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1652361044; x=1683897044;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=nvPDEHo96+etNui8Fd5ykiC81Ed7vKi31ftFYytPuz0=;\n b=Axm9oQM1zGw6lRxDSCnWDAlC2ZRHurmKwNxV5QtJfQSuSs9FG+/VjrKt\n LitvLiFl6Z9vXcj7RkNDVTt4Fdg/P5ctHBpWnIGQxxLLNt7rd3lMRZsHW\n 1C0bfRi0kL0fGEFbL2BYBZ4eivJlFeBW0lbBb2USIXY9hLIiibiwxNFu5\n sARQHN+mVPzHxQRnk01nSFSCyk373MW0ds4qYhI9yXNH/Ov+nllGz3H+t\n SQvvzwdGtsyBpwfgKWx+77N77a7wxe0Af75shangLd2MA65IgNfCmWUf9\n 8vlCs4MC0pDOtby6cFyytnIKmCbHP+r2C8WjH+OXEHq1RJAMYnbsj3VPr g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10344\"; a=\"268828929\"", "E=Sophos;i=\"5.91,219,1647327600\"; d=\"scan'208\";a=\"268828929\"", "E=Sophos;i=\"5.91,219,1647327600\"; d=\"scan'208\";a=\"542763828\"" ], "X-ExtLoop1": "1", "From": "Marcin Danilewicz <marcinx.danilewicz@intel.com>", "To": "dev@dpdk.org,\n\tjasvinder.singh@intel.com,\n\tcristian.dumitrescu@intel.com", "Cc": "megha.ajmera@intel.com", "Subject": "[PATCH v2] sched: enable CMAN at runtime", "Date": "Thu, 12 May 2022 13:10:36 +0000", "Message-Id": "<20220512131036.507178-1-marcinx.danilewicz@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220511135304.258809-1-marcinx.danilewicz@intel.com>", "References": "<20220511135304.258809-1-marcinx.danilewicz@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added changes to enable CMAN (RED or PIE) at init\nfrom profile configuration file.\n\nBy default CMAN code is enable but not in use, when\nthere is no RED or PIE profile configured.\n\nLog: v2 change in rte_sched.h to avoid ABI breakage.\n\nSigned-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>\n---\n config/rte_config.h | 3 -\n drivers/net/softnic/rte_eth_softnic_tm.c | 12 --\n examples/ip_pipeline/tmgr.c | 4 -\n examples/qos_sched/cfg_file.c | 14 +--\n examples/qos_sched/cfg_file.h | 2 -\n examples/qos_sched/init.c | 4 -\n examples/qos_sched/main.h | 2 -\n examples/qos_sched/profile.cfg | 130 ++++++++++-----------\n examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++\n examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++\n lib/sched/rte_sched.c | 53 ++-------\n lib/sched/rte_sched.h | 2 +\n 12 files changed, 371 insertions(+), 140 deletions(-)\n create mode 100644 examples/qos_sched/profile_pie.cfg\n create mode 100644 examples/qos_sched/profile_red.cfg", "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex 8eb29c1525..1740a1d053 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -88,9 +88,6 @@\n /* rte_power defines */\n #define RTE_MAX_LCORE_FREQS 64\n \n-/* rte_sched defines */\n-#undef RTE_SCHED_CMAN\n-\n /* rte_graph defines */\n #define RTE_GRAPH_BURST_SIZE 256\n #define RTE_LIBRTE_GRAPH_STATS 1\ndiff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c\nindex 6a7766ba1c..3a5fd676e9 100644\n--- a/drivers/net/softnic/rte_eth_softnic_tm.c\n+++ b/drivers/net/softnic/rte_eth_softnic_tm.c\n@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n-#ifdef RTE_SCHED_CMAN\n #define WRED_SUPPORTED\t\t\t\t\t\t1\n-#else\n-#define WRED_SUPPORTED\t\t\t\t\t\t0\n-#endif\n \n #define STATS_MASK_DEFAULT\t\t\t\t\t\\\n \t(RTE_TM_STATS_N_PKTS |\t\t\t\t\t\\\n@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)\n \treturn NULL;\n }\n \n-#ifdef RTE_SCHED_CMAN\n-\n static void\n wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)\n {\n@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)\n \t\t}\n }\n \n-#else\n-\n-#define wred_profiles_set(dev, subport_id)\n-\n-#endif\n-\n static struct tm_shared_shaper *\n tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)\n {\ndiff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c\nindex b138e885cf..e68e9961be 100644\n--- a/examples/ip_pipeline/tmgr.c\n+++ b/examples/ip_pipeline/tmgr.c\n@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;\n static struct rte_sched_pipe_params\n \tpipe_profile[TMGR_PIPE_PROFILE_MAX];\n \n-#ifdef RTE_SCHED_CMAN\n static struct rte_sched_cman_params cman_params = {\n \t.red_params = {\n \t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {\n \t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t\t},\n };\n-#endif /* RTE_SCHED_CMAN */\n \n static uint32_t n_pipe_profiles;\n \n@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {\n \t.pipe_profiles = pipe_profile,\n \t.n_pipe_profiles = 0, /* filled at run time */\n \t.n_max_pipe_profiles = RTE_DIM(pipe_profile),\n-#ifdef RTE_SCHED_CMAN\n \t.cman_params = &cman_params,\n-#endif /* RTE_SCHED_CMAN */\n };\n \n static struct tmgr_port_list tmgr_port_list;\ndiff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c\nindex 450482f07d..efff1dbb01 100644\n--- a/examples/qos_sched/cfg_file.c\n+++ b/examples/qos_sched/cfg_file.c\n@@ -229,13 +229,15 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,\n \treturn 0;\n }\n \n-#ifdef RTE_SCHED_CMAN\n void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n \t\t\t\t\tstruct rte_sched_cman_params cman_p)\n {\n \tint j, k;\n \tsubport_p->cman_params->cman_mode = cman_p.cman_mode;\n \n+\tif (subport_p->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)\n+\t\treturn;\n+\n \tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n \t\tif (subport_p->cman_params->cman_mode ==\n \t\t\t\t\tRTE_SCHED_CMAN_RED) {\n@@ -261,7 +263,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n \t\t}\n \t}\n }\n-#endif\n \n int\n cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)\n@@ -276,12 +277,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \tmemset(active_queues, 0, sizeof(active_queues));\n \tn_active_queues = 0;\n \n-#ifdef RTE_SCHED_CMAN\n \tstruct rte_sched_cman_params cman_params = {\n-\t\t.cman_mode = RTE_SCHED_CMAN_RED,\n \t\t.red_params = { },\n \t};\n \n+\tif (cman_params.cman_mode != RTE_SCHED_CMAN_NONE) {\n+\t\tcman_params.cman_mode = RTE_SCHED_CMAN_NONE;\n+\t}\n+\n \tif (rte_cfgfile_has_section(cfg, \"red\")) {\n \t\tcman_params.cman_mode = RTE_SCHED_CMAN_RED;\n \n@@ -387,7 +390,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \n \t\t}\n \t}\n-#endif /* RTE_SCHED_CMAN */\n \n \tfor (i = 0; i < MAX_SCHED_SUBPORTS; i++) {\n \t\tchar sec_name[CFG_NAME_LEN];\n@@ -465,9 +467,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t}\n-#ifdef RTE_SCHED_CMAN\n \t\t\tset_subport_cman_params(subport_params+i, cman_params);\n-#endif\n \t\t}\n \t}\n \ndiff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h\nindex 1a9dce9db5..19df91e7ba 100644\n--- a/examples/qos_sched/cfg_file.h\n+++ b/examples/qos_sched/cfg_file.h\n@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);\n \n int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);\n \n-#ifdef RTE_SCHED_CMAN\n void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n \t\t\t\t\tstruct rte_sched_cman_params cman_p);\n-#endif\n \n int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);\n \ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 8a0fb8a374..0afd553283 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params\n \t},\n };\n \n-#ifdef RTE_SCHED_CMAN\n struct rte_sched_cman_params cman_params = {\n \t.cman_mode = RTE_SCHED_CMAN_RED,\n \t.red_params = {\n@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {\n \t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t},\n };\n-#endif /* RTE_SCHED_CMAN */\n \n struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t{\n@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t\t.n_pipe_profiles = sizeof(pipe_profiles) /\n \t\t\tsizeof(struct rte_sched_pipe_params),\n \t\t.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,\n-#ifdef RTE_SCHED_CMAN\n \t\t.cman_params = &cman_params,\n-#endif /* RTE_SCHED_CMAN */\n \t},\n };\n \ndiff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h\nindex 915311bac8..76a68f585f 100644\n--- a/examples/qos_sched/main.h\n+++ b/examples/qos_sched/main.h\n@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];\n extern uint32_t n_active_queues;\n \n extern struct rte_sched_port_params port_params;\n-#ifdef RTE_SCHED_CMAN\n extern struct rte_sched_cman_params cman_params;\n-#endif\n extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];\n \n int app_parse_args(int argc, char **argv);\ndiff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg\nindex d4b21c0170..db65b0ed01 100644\n--- a/examples/qos_sched/profile.cfg\n+++ b/examples/qos_sched/profile.cfg\n@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1\n ;tc 12 wred inv prob = 10 10 10\n ;tc 12 wred weight = 9 9 9\n \n-[pie]\n-tc 0 qdelay ref = 15\n-tc 0 max burst = 150\n-tc 0 update interval = 15\n-tc 0 tailq th = 64\n-\n-tc 1 qdelay ref = 15\n-tc 1 max burst = 150\n-tc 1 update interval = 15\n-tc 1 tailq th = 64\n-\n-tc 2 qdelay ref = 15\n-tc 2 max burst = 150\n-tc 2 update interval = 15\n-tc 2 tailq th = 64\n-\n-tc 3 qdelay ref = 15\n-tc 3 max burst = 150\n-tc 3 update interval = 15\n-tc 3 tailq th = 64\n-\n-tc 4 qdelay ref = 15\n-tc 4 max burst = 150\n-tc 4 update interval = 15\n-tc 4 tailq th = 64\n-\n-tc 5 qdelay ref = 15\n-tc 5 max burst = 150\n-tc 5 update interval = 15\n-tc 5 tailq th = 64\n-\n-tc 6 qdelay ref = 15\n-tc 6 max burst = 150\n-tc 6 update interval = 15\n-tc 6 tailq th = 64\n-\n-tc 7 qdelay ref = 15\n-tc 7 max burst = 150\n-tc 7 update interval = 15\n-tc 7 tailq th = 64\n-\n-tc 8 qdelay ref = 15\n-tc 8 max burst = 150\n-tc 8 update interval = 15\n-tc 8 tailq th = 64\n-\n-tc 9 qdelay ref = 15\n-tc 9 max burst = 150\n-tc 9 update interval = 15\n-tc 9 tailq th = 64\n-\n-tc 10 qdelay ref = 15\n-tc 10 max burst = 150\n-tc 10 update interval = 15\n-tc 10 tailq th = 64\n-\n-tc 11 qdelay ref = 15\n-tc 11 max burst = 150\n-tc 11 update interval = 15\n-tc 11 tailq th = 64\n-\n-tc 12 qdelay ref = 15\n-tc 12 max burst = 150\n-tc 12 update interval = 15\n-tc 12 tailq th = 64\n+;[pie]\n+;tc 0 qdelay ref = 15\n+;tc 0 max burst = 150\n+;tc 0 update interval = 15\n+;tc 0 tailq th = 64\n+\n+;tc 1 qdelay ref = 15\n+;tc 1 max burst = 150\n+;tc 1 update interval = 15\n+;tc 1 tailq th = 64\n+\n+;tc 2 qdelay ref = 15\n+;tc 2 max burst = 150\n+;tc 2 update interval = 15\n+;tc 2 tailq th = 64\n+\n+;tc 3 qdelay ref = 15\n+;tc 3 max burst = 150\n+;tc 3 update interval = 15\n+;tc 3 tailq th = 64\n+\n+;tc 4 qdelay ref = 15\n+;tc 4 max burst = 150\n+;tc 4 update interval = 15\n+;tc 4 tailq th = 64\n+\n+;tc 5 qdelay ref = 15\n+;tc 5 max burst = 150\n+;tc 5 update interval = 15\n+;tc 5 tailq th = 64\n+\n+;tc 6 qdelay ref = 15\n+;tc 6 max burst = 150\n+;tc 6 update interval = 15\n+;tc 6 tailq th = 64\n+\n+;tc 7 qdelay ref = 15\n+;tc 7 max burst = 150\n+;tc 7 update interval = 15\n+;tc 7 tailq th = 64\n+\n+;tc 8 qdelay ref = 15\n+;tc 8 max burst = 150\n+;tc 8 update interval = 15\n+;tc 8 tailq th = 64\n+\n+;tc 9 qdelay ref = 15\n+;tc 9 max burst = 150\n+;tc 9 update interval = 15\n+;tc 9 tailq th = 64\n+\n+;tc 10 qdelay ref = 15\n+;tc 10 max burst = 150\n+;tc 10 update interval = 15\n+;tc 10 tailq th = 64\n+\n+;tc 11 qdelay ref = 15\n+;tc 11 max burst = 150\n+;tc 11 update interval = 15\n+;tc 11 tailq th = 64\n+\n+;tc 12 qdelay ref = 15\n+;tc 12 max burst = 150\n+;tc 12 update interval = 15\n+;tc 12 tailq th = 64\ndiff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg\nnew file mode 100644\nindex 0000000000..241f748b33\n--- /dev/null\n+++ b/examples/qos_sched/profile_pie.cfg\n@@ -0,0 +1,142 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2019 Intel Corporation.\n+\n+; This file enables the following hierarchical scheduler configuration for each\n+; 10GbE output port:\n+;\t* Single subport (subport 0):\n+;\t\t- Subport rate set to 100% of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of port rate\n+;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n+;\t\t- Pipe rate set to 1/4K of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of pipe rate\n+;\t\t- Within lowest priority traffic class (best-effort), the byte-level\n+;\t\t WRR weights for the 4 queues of best effort traffic class are set\n+;\t\t to 1:1:1:1\n+;\n+; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n+; of Data Plane Development Kit (DPDK) Programmer's Guide.\n+\n+; Port configuration\n+[port]\n+frame overhead = 24\n+number of subports per port = 1\n+\n+; Subport configuration\n+[subport 0]\n+number of pipes per subport = 4096\n+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64\n+\n+subport 0-8 = 0 ; These subports are configured with subport profile 0\n+\n+[subport profile 0]\n+tb rate = 1250000000 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 1250000000 ; Bytes per second\n+tc 1 rate = 1250000000 ; Bytes per second\n+tc 2 rate = 1250000000 ; Bytes per second\n+tc 3 rate = 1250000000 ; Bytes per second\n+tc 4 rate = 1250000000 ; Bytes per second\n+tc 5 rate = 1250000000 ; Bytes per second\n+tc 6 rate = 1250000000 ; Bytes per second\n+tc 7 rate = 1250000000 ; Bytes per second\n+tc 8 rate = 1250000000 ; Bytes per second\n+tc 9 rate = 1250000000 ; Bytes per second\n+tc 10 rate = 1250000000 ; Bytes per second\n+tc 11 rate = 1250000000 ; Bytes per second\n+tc 12 rate = 1250000000 ; Bytes per second\n+\n+tc period = 10 ; Milliseconds\n+\n+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n+\n+; Pipe configuration\n+[pipe profile 0]\n+tb rate = 305175 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 305175 ; Bytes per second\n+tc 1 rate = 305175 ; Bytes per second\n+tc 2 rate = 305175 ; Bytes per second\n+tc 3 rate = 305175 ; Bytes per second\n+tc 4 rate = 305175 ; Bytes per second\n+tc 5 rate = 305175 ; Bytes per second\n+tc 6 rate = 305175 ; Bytes per second\n+tc 7 rate = 305175 ; Bytes per second\n+tc 8 rate = 305175 ; Bytes per second\n+tc 9 rate = 305175 ; Bytes per second\n+tc 10 rate = 305175 ; Bytes per second\n+tc 11 rate = 305175 ; Bytes per second\n+tc 12 rate = 305175 ; Bytes per second\n+\n+tc period = 40 ; Milliseconds\n+\n+tc 12 oversubscription weight = 1\n+\n+tc 12 wrr weights = 1 1 1 1\n+\n+[pie]\n+tc 0 qdelay ref = 15\n+tc 0 max burst = 150\n+tc 0 update interval = 15\n+tc 0 tailq th = 64\n+\n+tc 1 qdelay ref = 15\n+tc 1 max burst = 150\n+tc 1 update interval = 15\n+tc 1 tailq th = 64\n+\n+tc 2 qdelay ref = 15\n+tc 2 max burst = 150\n+tc 2 update interval = 15\n+tc 2 tailq th = 64\n+\n+tc 3 qdelay ref = 15\n+tc 3 max burst = 150\n+tc 3 update interval = 15\n+tc 3 tailq th = 64\n+\n+tc 4 qdelay ref = 15\n+tc 4 max burst = 150\n+tc 4 update interval = 15\n+tc 4 tailq th = 64\n+\n+tc 5 qdelay ref = 15\n+tc 5 max burst = 150\n+tc 5 update interval = 15\n+tc 5 tailq th = 64\n+\n+tc 6 qdelay ref = 15\n+tc 6 max burst = 150\n+tc 6 update interval = 15\n+tc 6 tailq th = 64\n+\n+tc 7 qdelay ref = 15\n+tc 7 max burst = 150\n+tc 7 update interval = 15\n+tc 7 tailq th = 64\n+\n+tc 8 qdelay ref = 15\n+tc 8 max burst = 150\n+tc 8 update interval = 15\n+tc 8 tailq th = 64\n+\n+tc 9 qdelay ref = 15\n+tc 9 max burst = 150\n+tc 9 update interval = 15\n+tc 9 tailq th = 64\n+\n+tc 10 qdelay ref = 15\n+tc 10 max burst = 150\n+tc 10 update interval = 15\n+tc 10 tailq th = 64\n+\n+tc 11 qdelay ref = 15\n+tc 11 max burst = 150\n+tc 11 update interval = 15\n+tc 11 tailq th = 64\n+\n+tc 12 qdelay ref = 15\n+tc 12 max burst = 150\n+tc 12 update interval = 15\n+tc 12 tailq th = 64\ndiff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg\nnew file mode 100644\nindex 0000000000..4486d2799e\n--- /dev/null\n+++ b/examples/qos_sched/profile_red.cfg\n@@ -0,0 +1,143 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2019 Intel Corporation.\n+\n+; This file enables the following hierarchical scheduler configuration for each\n+; 10GbE output port:\n+;\t* Single subport (subport 0):\n+;\t\t- Subport rate set to 100% of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of port rate\n+;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n+;\t\t- Pipe rate set to 1/4K of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of pipe rate\n+;\t\t- Within lowest priority traffic class (best-effort), the byte-level\n+;\t\t WRR weights for the 4 queues of best effort traffic class are set\n+;\t\t to 1:1:1:1\n+;\n+; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n+; of Data Plane Development Kit (DPDK) Programmer's Guide.\n+\n+; Port configuration\n+[port]\n+frame overhead = 24\n+number of subports per port = 1\n+\n+; Subport configuration\n+[subport 0]\n+number of pipes per subport = 4096\n+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64\n+\n+subport 0-8 = 0 ; These subports are configured with subport profile 0\n+\n+[subport profile 0]\n+tb rate = 1250000000 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 1250000000 ; Bytes per second\n+tc 1 rate = 1250000000 ; Bytes per second\n+tc 2 rate = 1250000000 ; Bytes per second\n+tc 3 rate = 1250000000 ; Bytes per second\n+tc 4 rate = 1250000000 ; Bytes per second\n+tc 5 rate = 1250000000 ; Bytes per second\n+tc 6 rate = 1250000000 ; Bytes per second\n+tc 7 rate = 1250000000 ; Bytes per second\n+tc 8 rate = 1250000000 ; Bytes per second\n+tc 9 rate = 1250000000 ; Bytes per second\n+tc 10 rate = 1250000000 ; Bytes per second\n+tc 11 rate = 1250000000 ; Bytes per second\n+tc 12 rate = 1250000000 ; Bytes per second\n+\n+tc period = 10 ; Milliseconds\n+\n+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n+\n+; Pipe configuration\n+[pipe profile 0]\n+tb rate = 305175 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 305175 ; Bytes per second\n+tc 1 rate = 305175 ; Bytes per second\n+tc 2 rate = 305175 ; Bytes per second\n+tc 3 rate = 305175 ; Bytes per second\n+tc 4 rate = 305175 ; Bytes per second\n+tc 5 rate = 305175 ; Bytes per second\n+tc 6 rate = 305175 ; Bytes per second\n+tc 7 rate = 305175 ; Bytes per second\n+tc 8 rate = 305175 ; Bytes per second\n+tc 9 rate = 305175 ; Bytes per second\n+tc 10 rate = 305175 ; Bytes per second\n+tc 11 rate = 305175 ; Bytes per second\n+tc 12 rate = 305175 ; Bytes per second\n+\n+tc period = 40 ; Milliseconds\n+\n+tc 12 oversubscription weight = 1\n+\n+tc 12 wrr weights = 1 1 1 1\n+\n+; RED params per traffic class and color (Green / Yellow / Red)\n+[red]\n+tc 0 wred min = 48 40 32\n+tc 0 wred max = 64 64 64\n+tc 0 wred inv prob = 10 10 10\n+tc 0 wred weight = 9 9 9\n+\n+tc 1 wred min = 48 40 32\n+tc 1 wred max = 64 64 64\n+tc 1 wred inv prob = 10 10 10\n+tc 1 wred weight = 9 9 9\n+\n+tc 2 wred min = 48 40 32\n+tc 2 wred max = 64 64 64\n+tc 2 wred inv prob = 10 10 10\n+tc 2 wred weight = 9 9 9\n+\n+tc 3 wred min = 48 40 32\n+tc 3 wred max = 64 64 64\n+tc 3 wred inv prob = 10 10 10\n+tc 3 wred weight = 9 9 9\n+\n+tc 4 wred min = 48 40 32\n+tc 4 wred max = 64 64 64\n+tc 4 wred inv prob = 10 10 10\n+tc 4 wred weight = 9 9 9\n+\n+tc 5 wred min = 48 40 32\n+tc 5 wred max = 64 64 64\n+tc 5 wred inv prob = 10 10 10\n+tc 5 wred weight = 9 9 9\n+\n+tc 6 wred min = 48 40 32\n+tc 6 wred max = 64 64 64\n+tc 6 wred inv prob = 10 10 10\n+tc 6 wred weight = 9 9 9\n+\n+tc 7 wred min = 48 40 32\n+tc 7 wred max = 64 64 64\n+tc 7 wred inv prob = 10 10 10\n+tc 7 wred weight = 9 9 9\n+\n+tc 8 wred min = 48 40 32\n+tc 8 wred max = 64 64 64\n+tc 8 wred inv prob = 10 10 10\n+tc 8 wred weight = 9 9 9\n+\n+tc 9 wred min = 48 40 32\n+tc 9 wred max = 64 64 64\n+tc 9 wred inv prob = 10 10 10\n+tc 9 wred weight = 9 9 9\n+\n+tc 10 wred min = 48 40 32\n+tc 10 wred max = 64 64 64\n+tc 10 wred inv prob = 10 10 10\n+tc 10 wred weight = 9 9 9\n+\n+tc 11 wred min = 48 40 32\n+tc 11 wred max = 64 64 64\n+tc 11 wred inv prob = 10 10 10\n+tc 11 wred weight = 9 9 9\n+\n+tc 12 wred min = 48 40 32\n+tc 12 wred max = 64 64 64\n+tc 12 wred inv prob = 10 10 10\n+tc 12 wred weight = 9 9 9\ndiff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c\nindex ec74bee939..db14934832 100644\n--- a/lib/sched/rte_sched.c\n+++ b/lib/sched/rte_sched.c\n@@ -81,13 +81,11 @@ struct rte_sched_queue {\n \n struct rte_sched_queue_extra {\n \tstruct rte_sched_queue_stats stats;\n-#ifdef RTE_SCHED_CMAN\n \tRTE_STD_C11\n \tunion {\n \t\tstruct rte_red red;\n \t\tstruct rte_pie pie;\n \t};\n-#endif\n };\n \n enum grinder_state {\n@@ -179,7 +177,6 @@ struct rte_sched_subport {\n \t/* Pipe queues size */\n \tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \n-#ifdef RTE_SCHED_CMAN\n \tbool cman_enabled;\n \tenum rte_sched_cman_mode cman;\n \n@@ -188,7 +185,6 @@ struct rte_sched_subport {\n \t\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n \t\tstruct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \t};\n-#endif\n \n \t/* Scheduling loop detection */\n \tuint32_t pipe_loop;\n@@ -1081,7 +1077,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)\n \trte_free(port);\n }\n \n-#ifdef RTE_SCHED_CMAN\n static int\n rte_sched_red_config(struct rte_sched_port *port,\n \tstruct rte_sched_subport *s,\n@@ -1161,9 +1156,11 @@ rte_sched_cman_config(struct rte_sched_port *port,\n \telse if (params->cman_params->cman_mode == RTE_SCHED_CMAN_PIE)\n \t\treturn rte_sched_pie_config(port, s, params, n_subports);\n \n+\telse if (params->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)\n+\t\treturn 1;\n+\n \treturn -EINVAL;\n }\n-#endif\n \n int\n rte_sched_subport_config(struct rte_sched_port *port,\n@@ -1254,19 +1251,20 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\ts->n_pipe_profiles = params->n_pipe_profiles;\n \t\ts->n_max_pipe_profiles = params->n_max_pipe_profiles;\n \n-#ifdef RTE_SCHED_CMAN\n+\t\ts->cman_enabled = false;\n+\n \t\tif (params->cman_params != NULL) {\n-\t\t\ts->cman_enabled = true;\n \t\t\tstatus = rte_sched_cman_config(port, s, params, n_subports);\n \t\t\tif (status) {\n-\t\t\t\tRTE_LOG(NOTICE, SCHED,\n-\t\t\t\t\t\"%s: CMAN configuration fails\\n\", __func__);\n-\t\t\t\treturn status;\n+\t\t\t\tif (status != 1) {\n+\t\t\t\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\t\t\t\"%s: CMAN configuration fails\\n\", __func__);\n+\t\t\t\t\treturn status;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\ts->cman_enabled = true;\n \t\t\t}\n-\t\t} else {\n-\t\t\ts->cman_enabled = false;\n \t\t}\n-#endif\n \n \t\t/* Scheduling loop detection */\n \t\ts->pipe_loop = RTE_SCHED_PIPE_INVALID;\n@@ -1825,14 +1823,10 @@ rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,\n \n \tqe->stats.n_pkts_dropped += 1;\n \tqe->stats.n_bytes_dropped += pkt_len;\n-#ifdef RTE_SCHED_CMAN\n \tif (subport->cman_enabled)\n \t\tqe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;\n-#endif\n }\n \n-#ifdef RTE_SCHED_CMAN\n-\n static inline int\n rte_sched_port_cman_drop(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport,\n@@ -1902,29 +1896,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {\n \t}\n }\n \n-#else\n-\n-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,\n-\tstruct rte_sched_subport *subport __rte_unused,\n-\tstruct rte_mbuf *pkt __rte_unused,\n-\tuint32_t qindex __rte_unused,\n-\tuint16_t qlen __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)\n-\n-static inline void\n-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,\n-\tuint32_t qindex __rte_unused,\n-\tuint32_t pkt_len __rte_unused,\n-\tuint64_t time __rte_unused) {\n-\t/* do-nothing when RTE_SCHED_CMAN not defined */\n-}\n-\n-#endif /* RTE_SCHED_CMAN */\n-\n #ifdef RTE_SCHED_DEBUG\n \n static inline void\ndiff --git a/lib/sched/rte_sched.h b/lib/sched/rte_sched.h\nindex 5ece64e527..82aa73ff5b 100644\n--- a/lib/sched/rte_sched.h\n+++ b/lib/sched/rte_sched.h\n@@ -128,6 +128,8 @@ extern \"C\" {\n enum rte_sched_cman_mode {\n \tRTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */\n \tRTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller Enhanced (PIE) */\n+\t/* New enum RTE_SCHED_CMAN_NONE added at the end to avoid ABI breakage */\n+\tRTE_SCHED_CMAN_NONE, /**< no RED|PIE cfg available */\n };\n \n /*\n", "prefixes": [ "v2" ] }