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{
    "id": 110224,
    "url": "https://patches.dpdk.org/api/patches/110224/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220425053446.921528-6-robinx.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220425053446.921528-6-robinx.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220425053446.921528-6-robinx.zhang@intel.com",
    "date": "2022-04-25T05:34:46",
    "name": "[v4,5/5] ethdev: format module EEPROM for SFF-8636",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "272af54cef4ffb01041180bdbd69c02ff5f4a674",
    "submitter": {
        "id": 2004,
        "url": "https://patches.dpdk.org/api/people/2004/?format=api",
        "name": "Robin Zhang",
        "email": "robinx.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220425053446.921528-6-robinx.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 22654,
            "url": "https://patches.dpdk.org/api/series/22654/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22654",
            "date": "2022-04-25T05:34:41",
            "name": "add telemetry command for show module EEPROM",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/22654/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/110224/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/110224/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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            "from intel-cd-odc-robin.cd.intel.com ([10.240.178.191])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2022 22:39:43 -0700"
        ],
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        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10327\"; a=\"247070555\"",
            "E=Sophos;i=\"5.90,287,1643702400\"; d=\"scan'208\";a=\"247070555\"",
            "E=Sophos;i=\"5.90,287,1643702400\"; d=\"scan'208\";a=\"579087367\""
        ],
        "From": "Robin Zhang <robinx.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com,\n thomas@monjalon.net, andrew.rybchenko@oktetlabs.ru,\n bruce.richardson@intel.com, david.marchand@redhat.com,\n Robin Zhang <robinx.zhang@intel.com>",
        "Subject": "[PATCH v4 5/5] ethdev: format module EEPROM for SFF-8636",
        "Date": "Mon, 25 Apr 2022 05:34:46 +0000",
        "Message-Id": "<20220425053446.921528-6-robinx.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20220425053446.921528-1-robinx.zhang@intel.com>",
        "References": "<20220215101853.919735-1-robinx.zhang@intel.com>\n <20220425053446.921528-1-robinx.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This patch implements format module EEPROM information for\nSFF-8636 Rev 2.7\n\nSigned-off-by: Robin Zhang <robinx.zhang@intel.com>\n---\n lib/ethdev/ethdev_sff_telemetry.c |   4 +\n lib/ethdev/meson.build            |   1 +\n lib/ethdev/sff_8636.c             | 775 ++++++++++++++++++++++++++++++\n lib/ethdev/sff_8636.h             | 592 +++++++++++++++++++++++\n 4 files changed, 1372 insertions(+)\n create mode 100644 lib/ethdev/sff_8636.c\n create mode 100644 lib/ethdev/sff_8636.h",
    "diff": "diff --git a/lib/ethdev/ethdev_sff_telemetry.c b/lib/ethdev/ethdev_sff_telemetry.c\nindex fa93b35275..241ca28743 100644\n--- a/lib/ethdev/ethdev_sff_telemetry.c\n+++ b/lib/ethdev/ethdev_sff_telemetry.c\n@@ -71,6 +71,10 @@ sff_port_module_eeprom_display(uint16_t port_id, struct sff_item *items)\n \t\tsff_8079_show_all(einfo.data, items);\n \t\tsff_8472_show_all(einfo.data, items);\n \t\tbreak;\n+\tcase RTE_ETH_MODULE_SFF_8436:\n+\tcase RTE_ETH_MODULE_SFF_8636:\n+\t\tsff_8636_show_all(einfo.data, einfo.length, items);\n+\t\tbreak;\n \tdefault:\n \t\tRTE_ETHDEV_LOG(NOTICE, \"Unsupported module type: %u\\n\", minfo.type);\n \t\tbreak;\ndiff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build\nindex 4d81a35c09..88ceeb12b9 100644\n--- a/lib/ethdev/meson.build\n+++ b/lib/ethdev/meson.build\n@@ -15,6 +15,7 @@ sources = files(\n         'sff_common.c',\n         'sff_8079.c',\n         'sff_8472.c',\n+        'sff_8636.c',\n )\n \n headers = files(\ndiff --git a/lib/ethdev/sff_8636.c b/lib/ethdev/sff_8636.c\nnew file mode 100644\nindex 0000000000..290b31e973\n--- /dev/null\n+++ b/lib/ethdev/sff_8636.c\n@@ -0,0 +1,775 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ *\n+ * Implements SFF-8636 based QSFP+/QSFP28 Diagnostics Memory map.\n+ *\n+ */\n+\n+#include <stdio.h>\n+#include <math.h>\n+#include <rte_mbuf.h>\n+#include <rte_ethdev.h>\n+#include <rte_flow.h>\n+#include \"sff_common.h\"\n+#include \"sff_8636.h\"\n+#include \"ethdev_sff_telemetry.h\"\n+\n+#define MAX_DESC_SIZE\t42\n+\n+static struct sff_8636_aw_flags {\n+\tconst char *str;        /* Human-readable string, null at the end */\n+\tint offset;             /* A2-relative address offset */\n+\tuint8_t value;             /* Alarm is on if (offset & value) != 0. */\n+} sff_8636_aw_flags[] = {\n+\t{ \"Laser bias current high alarm   (Chan 1)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_HALARM) },\n+\t{ \"Laser bias current low alarm    (Chan 1)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_LALARM) },\n+\t{ \"Laser bias current high warning (Chan 1)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_HWARN) },\n+\t{ \"Laser bias current low warning  (Chan 1)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_1_LWARN) },\n+\n+\t{ \"Laser bias current high alarm   (Chan 2)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_HALARM) },\n+\t{ \"Laser bias current low alarm    (Chan 2)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_LALARM) },\n+\t{ \"Laser bias current high warning (Chan 2)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_HWARN) },\n+\t{ \"Laser bias current low warning  (Chan 2)\",\n+\t\tSFF_8636_TX_BIAS_12_AW_OFFSET, (SFF_8636_TX_BIAS_2_LWARN) },\n+\n+\t{ \"Laser bias current high alarm   (Chan 3)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_HALARM) },\n+\t{ \"Laser bias current low alarm    (Chan 3)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_LALARM) },\n+\t{ \"Laser bias current high warning (Chan 3)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_HWARN) },\n+\t{ \"Laser bias current low warning  (Chan 3)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_3_LWARN) },\n+\n+\t{ \"Laser bias current high alarm   (Chan 4)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_HALARM) },\n+\t{ \"Laser bias current low alarm    (Chan 4)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_LALARM) },\n+\t{ \"Laser bias current high warning (Chan 4)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_HWARN) },\n+\t{ \"Laser bias current low warning  (Chan 4)\",\n+\t\tSFF_8636_TX_BIAS_34_AW_OFFSET, (SFF_8636_TX_BIAS_4_LWARN) },\n+\n+\t{ \"Module temperature high alarm\",\n+\t\tSFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_HALARM_STATUS) },\n+\t{ \"Module temperature low alarm\",\n+\t\tSFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_LALARM_STATUS) },\n+\t{ \"Module temperature high warning\",\n+\t\tSFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_HWARN_STATUS) },\n+\t{ \"Module temperature low warning\",\n+\t\tSFF_8636_TEMP_AW_OFFSET, (SFF_8636_TEMP_LWARN_STATUS) },\n+\n+\t{ \"Module voltage high alarm\",\n+\t\tSFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_HALARM_STATUS) },\n+\t{ \"Module voltage low alarm\",\n+\t\tSFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_LALARM_STATUS) },\n+\t{ \"Module voltage high warning\",\n+\t\tSFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_HWARN_STATUS) },\n+\t{ \"Module voltage low warning\",\n+\t\tSFF_8636_VCC_AW_OFFSET, (SFF_8636_VCC_LWARN_STATUS) },\n+\n+\t{ \"Laser tx power high alarm   (Channel 1)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_HALARM) },\n+\t{ \"Laser tx power low alarm    (Channel 1)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_LALARM) },\n+\t{ \"Laser tx power high warning (Channel 1)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_HWARN) },\n+\t{ \"Laser tx power low warning  (Channel 1)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_1_LWARN) },\n+\n+\t{ \"Laser tx power high alarm   (Channel 2)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_HALARM) },\n+\t{ \"Laser tx power low alarm    (Channel 2)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_LALARM) },\n+\t{ \"Laser tx power high warning (Channel 2)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_HWARN) },\n+\t{ \"Laser tx power low warning  (Channel 2)\",\n+\t\tSFF_8636_TX_PWR_12_AW_OFFSET, (SFF_8636_TX_PWR_2_LWARN) },\n+\n+\t{ \"Laser tx power high alarm   (Channel 3)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_HALARM) },\n+\t{ \"Laser tx power low alarm    (Channel 3)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_LALARM) },\n+\t{ \"Laser tx power high warning (Channel 3)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_HWARN) },\n+\t{ \"Laser tx power low warning  (Channel 3)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_3_LWARN) },\n+\n+\t{ \"Laser tx power high alarm   (Channel 4)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_HALARM) },\n+\t{ \"Laser tx power low alarm    (Channel 4)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_LALARM) },\n+\t{ \"Laser tx power high warning (Channel 4)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_HWARN) },\n+\t{ \"Laser tx power low warning  (Channel 4)\",\n+\t\tSFF_8636_TX_PWR_34_AW_OFFSET, (SFF_8636_TX_PWR_4_LWARN) },\n+\n+\t{ \"Laser rx power high alarm   (Channel 1)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_HALARM) },\n+\t{ \"Laser rx power low alarm    (Channel 1)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_LALARM) },\n+\t{ \"Laser rx power high warning (Channel 1)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_HWARN) },\n+\t{ \"Laser rx power low warning  (Channel 1)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_1_LWARN) },\n+\n+\t{ \"Laser rx power high alarm   (Channel 2)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_HALARM) },\n+\t{ \"Laser rx power low alarm    (Channel 2)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_LALARM) },\n+\t{ \"Laser rx power high warning (Channel 2)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_HWARN) },\n+\t{ \"Laser rx power low warning  (Channel 2)\",\n+\t\tSFF_8636_RX_PWR_12_AW_OFFSET, (SFF_8636_RX_PWR_2_LWARN) },\n+\n+\t{ \"Laser rx power high alarm   (Channel 3)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_HALARM) },\n+\t{ \"Laser rx power low alarm    (Channel 3)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_LALARM) },\n+\t{ \"Laser rx power high warning (Channel 3)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_HWARN) },\n+\t{ \"Laser rx power low warning  (Channel 3)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_3_LWARN) },\n+\n+\t{ \"Laser rx power high alarm   (Channel 4)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_HALARM) },\n+\t{ \"Laser rx power low alarm    (Channel 4)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_LALARM) },\n+\t{ \"Laser rx power high warning (Channel 4)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_HWARN) },\n+\t{ \"Laser rx power low warning  (Channel 4)\",\n+\t\tSFF_8636_RX_PWR_34_AW_OFFSET, (SFF_8636_RX_PWR_4_LWARN) },\n+\n+\t{ NULL, 0, 0 },\n+};\n+\n+static void sff_8636_show_identifier(const uint8_t *data, struct sff_item *items)\n+{\n+\tsff_8024_show_identifier(data, SFF_8636_ID_OFFSET, items);\n+}\n+\n+static void sff_8636_show_ext_identifier(const uint8_t *data, struct sff_item *items)\n+{\n+\tstatic const char *name = \"Extended identifier description\";\n+\tchar val_string[SFF_ITEM_VAL_COMPOSE_SIZE];\n+\tsnprintf(val_string, sizeof(val_string), \"0x%02x\", data[SFF_8636_EXT_ID_OFFSET]);\n+\tadd_item_string(items, \"Extended identifier\", val_string);\n+\n+\tswitch (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_PWR_CLASS_MASK) {\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_1:\n+\t\tadd_item_string(items, name, \"1.5W max. Power consumption\");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_2:\n+\t\tadd_item_string(items, name, \"2.0W max. Power consumption\");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_3:\n+\t\tadd_item_string(items, name, \"2.5W max. Power consumption\");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_4:\n+\t\tadd_item_string(items, name, \"3.5W max. Power consumption\");\n+\t\tbreak;\n+\t}\n+\n+\tif (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_CDR_TX_MASK)\n+\t\tadd_item_string(items, name, \"CDR present in TX\");\n+\telse\n+\t\tadd_item_string(items, name, \"No CDR in TX\");\n+\n+\tif (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_CDR_RX_MASK)\n+\t\tadd_item_string(items, name, \"CDR present in RX\");\n+\telse\n+\t\tadd_item_string(items, name, \"No CDR in RX\");\n+\n+\tswitch (data[SFF_8636_EXT_ID_OFFSET] & SFF_8636_EXT_ID_EPWR_CLASS_MASK) {\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_LEGACY:\n+\t\tsnprintf(val_string, sizeof(val_string), \"%s\", \"\");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_5:\n+\t\tsnprintf(val_string, sizeof(val_string), \"%s\", \"4.0W max. Power consumption, \");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_6:\n+\t\tsnprintf(val_string, sizeof(val_string), \"%s\", \"4.5W max. Power consumption, \");\n+\t\tbreak;\n+\tcase SFF_8636_EXT_ID_PWR_CLASS_7:\n+\t\tsnprintf(val_string, sizeof(val_string), \"%s\", \"5.0W max. Power consumption, \");\n+\t\tbreak;\n+\t}\n+\n+\tif (data[SFF_8636_PWR_MODE_OFFSET] & SFF_8636_HIGH_PWR_ENABLE)\n+\t\tstrlcat(val_string, \"High Power Class (> 3.5 W) enabled\", sizeof(val_string));\n+\telse\n+\t\tstrlcat(val_string, \"High Power Class (> 3.5 W) not enabled\", sizeof(val_string));\n+\n+\tadd_item_string(items, name, val_string);\n+}\n+\n+static void sff_8636_show_connector(const uint8_t *data, struct sff_item *items)\n+{\n+\tsff_8024_show_connector(data, SFF_8636_CTOR_OFFSET, items);\n+}\n+\n+static void sff_8636_show_transceiver(const uint8_t *data, struct sff_item *items)\n+{\n+\tstatic const char *name = \"Transceiver type\";\n+\tchar val_string[SFF_ITEM_VAL_COMPOSE_SIZE];\n+\n+\tsnprintf(val_string, sizeof(val_string), \"0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\",\n+\t\tdata[SFF_8636_ETHERNET_COMP_OFFSET],\n+\t\tdata[SFF_8636_SONET_COMP_OFFSET],\n+\t\tdata[SFF_8636_SAS_COMP_OFFSET],\n+\t\tdata[SFF_8636_GIGE_COMP_OFFSET],\n+\t\tdata[SFF_8636_FC_LEN_OFFSET],\n+\t\tdata[SFF_8636_FC_TECH_OFFSET],\n+\t\tdata[SFF_8636_FC_TRANS_MEDIA_OFFSET],\n+\t\tdata[SFF_8636_FC_SPEED_OFFSET]);\n+\tadd_item_string(items, \"Transceiver codes\", val_string);\n+\n+\t/* 10G/40G Ethernet Compliance Codes */\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_LRM)\n+\t\tadd_item_string(items, name, \"10G Ethernet: 10G Base-LRM\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_LR)\n+\t\tadd_item_string(items, name, \"10G Ethernet: 10G Base-LR\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_10G_SR)\n+\t\tadd_item_string(items, name, \"10G Ethernet: 10G Base-SR\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_CR4)\n+\t\tadd_item_string(items, name, \"40G Ethernet: 40G Base-CR4\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_SR4)\n+\t\tadd_item_string(items, name, \"40G Ethernet: 40G Base-SR4\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_LR4)\n+\t\tadd_item_string(items, name, \"40G Ethernet: 40G Base-LR4\");\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_40G_ACTIVE)\n+\t\tadd_item_string(items, name, \"40G Ethernet: 40G Active Cable (XLPPI)\");\n+\n+\t/* Extended Specification Compliance Codes from SFF-8024 */\n+\tif (data[SFF_8636_ETHERNET_COMP_OFFSET] & SFF_8636_ETHERNET_RSRVD) {\n+\t\tswitch (data[SFF_8636_OPTION_1_OFFSET]) {\n+\t\tcase SFF_8636_ETHERNET_UNSPECIFIED:\n+\t\t\tadd_item_string(items, name, \"(reserved or unknown)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_AOC:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\"100G Ethernet: 100G AOC or 25GAUI C2M AOC with worst BER of 5x10^(-5)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_SR4:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\t\"100G Ethernet: 100G Base-SR4 or 25GBase-SR\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_LR4:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G Base-LR4\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_ER4:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G Base-ER4\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_SR10:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G Base-SR10\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_CWDM4_FEC:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G CWDM4 MSA with FEC\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_PSM4:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G PSM4 Parallel SMF\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_ACC:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\"100G Ethernet: 100G ACC or 25GAUI C2M ACC with worst BER of 5x10^(-5)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_CWDM4_NO_FEC:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\t\"100G Ethernet: 100G CWDM4 MSA without FEC\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_RSVD1:\n+\t\t\tadd_item_string(items, name, \"(reserved or unknown)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_CR4:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\t\"100G Ethernet: 100G Base-CR4 or 25G Base-CR CA-L\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_25G_CR_CA_S:\n+\t\t\tadd_item_string(items, name, \"25G Ethernet: 25G Base-CR CA-S\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_25G_CR_CA_N:\n+\t\t\tadd_item_string(items, name, \"25G Ethernet: 25G Base-CR CA-N\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_40G_ER4:\n+\t\t\tadd_item_string(items, name, \"40G Ethernet: 40G Base-ER4\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_4X10_SR:\n+\t\t\tadd_item_string(items, name, \"4x10G Ethernet: 10G Base-SR\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_40G_PSM4:\n+\t\t\tadd_item_string(items, name, \"40G Ethernet: 40G PSM4 Parallel SMF\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_G959_P1I1_2D1:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\"Ethernet: G959.1 profile P1I1-2D1 (10709 MBd, 2km, 1310nm SM)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_G959_P1S1_2D2:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\"Ethernet: G959.1 profile P1S1-2D2 (10709 MBd, 40km, 1550nm SM)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_G959_P1L1_2D2:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\"Ethernet: G959.1 profile P1L1-2D2 (10709 MBd, 80km, 1550nm SM)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_10GT_SFI:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\t\"10G Ethernet: 10G Base-T with SFI electrical interface\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_CLR4:\n+\t\t\tadd_item_string(items, name, \"100G Ethernet: 100G CLR4\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_AOC2:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\"100G Ethernet: 100G AOC or 25GAUI C2M AOC with worst BER of 10^(-12)\");\n+\t\t\tbreak;\n+\t\tcase SFF_8636_ETHERNET_100G_ACC2:\n+\t\t\tadd_item_string(items, name,\n+\t\t\t\"100G Ethernet: 100G ACC or 25GAUI C2M ACC with worst BER of 10^(-12)\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tadd_item_string(items, name, \"(reserved or unknown)\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* SONET Compliance Codes */\n+\tif (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_40G_OTN)\n+\t\tadd_item_string(items, name, \"40G OTN (OTU3B/OTU3C)\");\n+\tif (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_LR)\n+\t\tadd_item_string(items, name, \"SONET: OC-48, long reach\");\n+\tif (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_IR)\n+\t\tadd_item_string(items, name, \"SONET: OC-48, intermediate reach\");\n+\tif (data[SFF_8636_SONET_COMP_OFFSET] & SFF_8636_SONET_OC48_SR)\n+\t\tadd_item_string(items, name, \"SONET: OC-48, short reach\");\n+\n+\t/* SAS/SATA Compliance Codes */\n+\tif (data[SFF_8636_SAS_COMP_OFFSET] & SFF_8636_SAS_6G)\n+\t\tadd_item_string(items, name, \"SAS 6.0G\");\n+\tif (data[SFF_8636_SAS_COMP_OFFSET] & SFF_8636_SAS_3G)\n+\t\tadd_item_string(items, name, \"SAS 3.0G\");\n+\n+\t/* Ethernet Compliance Codes */\n+\tif (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_T)\n+\t\tadd_item_string(items, name, \"Ethernet: 1000BASE-T\");\n+\tif (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_CX)\n+\t\tadd_item_string(items, name, \"Ethernet: 1000BASE-CX\");\n+\tif (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_LX)\n+\t\tadd_item_string(items, name, \"Ethernet: 1000BASE-LX\");\n+\tif (data[SFF_8636_GIGE_COMP_OFFSET] & SFF_8636_GIGE_1000_BASE_SX)\n+\t\tadd_item_string(items, name, \"Ethernet: 1000BASE-SX\");\n+\n+\t/* Fibre Channel link length */\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_VERY_LONG)\n+\t\tadd_item_string(items, name, \"FC: very long distance (V)\");\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_SHORT)\n+\t\tadd_item_string(items, name, \"FC: short distance (S)\");\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_INT)\n+\t\tadd_item_string(items, name, \"FC: intermediate distance (I)\");\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_LONG)\n+\t\tadd_item_string(items, name, \"FC: long distance (L)\");\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_LEN_MED)\n+\t\tadd_item_string(items, name, \"FC: medium distance (M)\");\n+\n+\t/* Fibre Channel transmitter technology */\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_TECH_LONG_LC)\n+\t\tadd_item_string(items, name, \"FC: Longwave laser (LC)\");\n+\tif (data[SFF_8636_FC_LEN_OFFSET] & SFF_8636_FC_TECH_ELEC_INTER)\n+\t\tadd_item_string(items, name, \"FC: Electrical inter-enclosure (EL)\");\n+\tif (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_ELEC_INTRA)\n+\t\tadd_item_string(items, name, \"FC: Electrical intra-enclosure (EL)\");\n+\tif (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_SHORT_WO_OFC)\n+\t\tadd_item_string(items, name, \"FC: Shortwave laser w/o OFC (SN)\");\n+\tif (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_SHORT_W_OFC)\n+\t\tadd_item_string(items, name, \"FC: Shortwave laser with OFC (SL)\");\n+\tif (data[SFF_8636_FC_TECH_OFFSET] & SFF_8636_FC_TECH_LONG_LL)\n+\t\tadd_item_string(items, name, \"FC: Longwave laser (LL)\");\n+\n+\t/* Fibre Channel transmission media */\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TW)\n+\t\tadd_item_string(items, name, \"FC: Twin Axial Pair (TW)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TP)\n+\t\tadd_item_string(items, name, \"FC: Twisted Pair (TP)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_MI)\n+\t\tadd_item_string(items, name, \"FC: Miniature Coax (MI)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_TV)\n+\t\tadd_item_string(items, name, \"FC: Video Coax (TV)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_M6)\n+\t\tadd_item_string(items, name, \"FC: Multimode, 62.5m (M6)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_M5)\n+\t\tadd_item_string(items, name, \"FC: Multimode, 50m (M5)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_OM3)\n+\t\tadd_item_string(items, name, \"FC: Multimode, 50um (OM3)\");\n+\tif (data[SFF_8636_FC_TRANS_MEDIA_OFFSET] & SFF_8636_FC_TRANS_MEDIA_SM)\n+\t\tadd_item_string(items, name, \"FC: Single Mode (SM)\");\n+\n+\t/* Fibre Channel speed */\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_1200_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 1200 MBytes/sec\");\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_800_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 800 MBytes/sec\");\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_1600_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 1600 MBytes/sec\");\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_400_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 400 MBytes/sec\");\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_200_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 200 MBytes/sec\");\n+\tif (data[SFF_8636_FC_SPEED_OFFSET] & SFF_8636_FC_SPEED_100_MBPS)\n+\t\tadd_item_string(items, name, \"FC: 100 MBytes/sec\");\n+}\n+\n+static void sff_8636_show_encoding(const uint8_t *data, struct sff_item *items)\n+{\n+\tsff_8024_show_encoding(data, SFF_8636_ENCODING_OFFSET,\n+\t\t\t       RTE_ETH_MODULE_SFF_8636, items);\n+}\n+\n+static void sff_8636_show_rate_identifier(const uint8_t *data, struct sff_item *items)\n+{\n+\tchar val_string[20];\n+\n+\tsnprintf(val_string, sizeof(val_string), \"0x%02x\", data[SFF_8636_EXT_RS_OFFSET]);\n+\tadd_item_string(items, \"Rate identifier\", val_string);\n+}\n+\n+static void sff_8636_show_oui(const uint8_t *data, struct sff_item *items)\n+{\n+\tsff_8024_show_oui(data, SFF_8636_VENDOR_OUI_OFFSET, items);\n+}\n+\n+static void sff_8636_show_wavelength_or_copper_compliance(const uint8_t *data,\n+\t\t\t\t\t\t\t  struct sff_item *items)\n+{\n+\tchar val_string[SFF_ITEM_VAL_COMPOSE_SIZE];\n+\tsnprintf(val_string, sizeof(val_string), \"0x%02x\",\n+\t\t(data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK));\n+\n+\tswitch (data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK) {\n+\tcase SFF_8636_TRANS_850_VCSEL:\n+\t\tstrlcat(val_string, \" (850 nm VCSEL)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1310_VCSEL:\n+\t\tstrlcat(val_string, \" (1310 nm VCSEL)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1550_VCSEL:\n+\t\tstrlcat(val_string, \" (1550 nm VCSEL)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1310_FP:\n+\t\tstrlcat(val_string, \" (1310 nm FP)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1310_DFB:\n+\t\tstrlcat(val_string, \" (1310 nm DFB)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1550_DFB:\n+\t\tstrlcat(val_string, \" (1550 nm DFB)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1310_EML:\n+\t\tstrlcat(val_string, \" (1310 nm EML)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1550_EML:\n+\t\tstrlcat(val_string, \" (1550 nm EML)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_OTHERS:\n+\t\tstrlcat(val_string, \" (Others/Undefined)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_1490_DFB:\n+\t\tstrlcat(val_string, \" (1490 nm DFB)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_PAS_UNEQUAL:\n+\t\tstrlcat(val_string, \" (Copper cable unequalized)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_PAS_EQUAL:\n+\t\tstrlcat(val_string, \" (Copper cable passive equalized)\", sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_LNR_FAR_EQUAL:\n+\t\tstrlcat(val_string,\n+\t\t       \" (Copper cable, near and far end limiting active equalizers)\",\n+\t\t       sizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_FAR_EQUAL:\n+\t\tstrlcat(val_string,\n+\t\t\t\" (Copper cable, far end limiting active equalizers)\",\n+\t\t\tsizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_NEAR_EQUAL:\n+\t\tstrlcat(val_string,\n+\t\t\t\" (Copper cable, near end limiting active equalizers)\",\n+\t\t\tsizeof(val_string));\n+\t\tbreak;\n+\tcase SFF_8636_TRANS_COPPER_LNR_EQUAL:\n+\t\tstrlcat(val_string,\n+\t\t\t\" (Copper cable, linear active equalizers)\",\n+\t\t\tsizeof(val_string));\n+\t\tbreak;\n+\t}\n+\tadd_item_string(items, \"Transmitter technology\", val_string);\n+\n+\tif ((data[SFF_8636_DEVICE_TECH_OFFSET] & SFF_8636_TRANS_TECH_MASK)\n+\t\t\t>= SFF_8636_TRANS_COPPER_PAS_UNEQUAL) {\n+\t\tsnprintf(val_string, sizeof(val_string), \"%udb\",\n+\t\t\t data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]);\n+\t\tadd_item_string(items, \"Attenuation at 2.5GHz\", val_string);\n+\n+\t\tsnprintf(val_string, sizeof(val_string), \"%udb\",\n+\t\t\t data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]);\n+\t\tadd_item_string(items, \"Attenuation at 5.0GHz\", val_string);\n+\n+\t\tsnprintf(val_string, sizeof(val_string), \"%udb\",\n+\t\t\t data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]);\n+\t\tadd_item_string(items, \"Attenuation at 7.0GHz\", val_string);\n+\n+\t\tsnprintf(val_string, sizeof(val_string), \"%udb\",\n+\t\t\t data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET]);\n+\t\tadd_item_string(items, \"Attenuation at 12.9GHz\", val_string);\n+\t} else {\n+\t\tsnprintf(val_string, sizeof(val_string), \"%.3lfnm\",\n+\t\t\t(((data[SFF_8636_WAVELEN_HIGH_BYTE_OFFSET] << 8) |\n+\t\t\tdata[SFF_8636_WAVELEN_LOW_BYTE_OFFSET])*0.05));\n+\t\tadd_item_string(items, \"Laser wavelength\", val_string);\n+\n+\t\tsnprintf(val_string, sizeof(val_string), \"%.3lfnm\",\n+\t\t\t(((data[SFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET] << 8) |\n+\t\t\tdata[SFF_8636_WAVE_TOL_LOW_BYTE_OFFSET])*0.005));\n+\t\tadd_item_string(items, \"Laser wavelength tolerance\", val_string);\n+\t}\n+}\n+\n+static void sff_8636_show_revision_compliance(const uint8_t *data, struct sff_item *items)\n+{\n+\tstatic const char *name = \"Revision Compliance\";\n+\n+\tswitch (data[SFF_8636_REV_COMPLIANCE_OFFSET]) {\n+\tcase SFF_8636_REV_UNSPECIFIED:\n+\t\tadd_item_string(items, name, \"Revision not specified\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8436_48:\n+\t\tadd_item_string(items, name, \"SFF-8436 Rev 4.8 or earlier\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8436_8636:\n+\t\tadd_item_string(items, name, \"SFF-8436 Rev 4.8 or earlier\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8636_13:\n+\t\tadd_item_string(items, name, \"SFF-8636 Rev 1.3 or earlier\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8636_14:\n+\t\tadd_item_string(items, name, \"SFF-8636 Rev 1.4\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8636_15:\n+\t\tadd_item_string(items, name, \"SFF-8636 Rev 1.5\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8636_20:\n+\t\tadd_item_string(items, name, \"SFF-8636 Rev 2.0\");\n+\t\tbreak;\n+\tcase SFF_8636_REV_8636_27:\n+\t\tadd_item_string(items, name, \"SFF-8636 Rev 2.5/2.6/2.7\");\n+\t\tbreak;\n+\tdefault:\n+\t\tadd_item_string(items, name, \"Unallocated\");\n+\t\tbreak;\n+\t}\n+}\n+\n+/*\n+ * 2-byte internal temperature conversions:\n+ * First byte is a signed 8-bit integer, which is the temp decimal part\n+ * Second byte are 1/256th of degree, which are added to the dec part.\n+ */\n+#define SFF_8636_OFFSET_TO_TEMP(offset) ((int16_t)OFFSET_TO_U16(offset))\n+\n+static void sff_8636_dom_parse(const uint8_t *data, struct sff_diags *sd)\n+{\n+\tint i = 0;\n+\n+\t/* Monitoring Thresholds for Alarms and Warnings */\n+\tsd->sfp_voltage[MCURR] = OFFSET_TO_U16(SFF_8636_VCC_CURR);\n+\tsd->sfp_voltage[HALRM] = OFFSET_TO_U16(SFF_8636_VCC_HALRM);\n+\tsd->sfp_voltage[LALRM] = OFFSET_TO_U16(SFF_8636_VCC_LALRM);\n+\tsd->sfp_voltage[HWARN] = OFFSET_TO_U16(SFF_8636_VCC_HWARN);\n+\tsd->sfp_voltage[LWARN] = OFFSET_TO_U16(SFF_8636_VCC_LWARN);\n+\n+\tsd->sfp_temp[MCURR] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_CURR);\n+\tsd->sfp_temp[HALRM] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_HALRM);\n+\tsd->sfp_temp[LALRM] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_LALRM);\n+\tsd->sfp_temp[HWARN] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_HWARN);\n+\tsd->sfp_temp[LWARN] = SFF_8636_OFFSET_TO_TEMP(SFF_8636_TEMP_LWARN);\n+\n+\tsd->bias_cur[HALRM] = OFFSET_TO_U16(SFF_8636_TX_BIAS_HALRM);\n+\tsd->bias_cur[LALRM] = OFFSET_TO_U16(SFF_8636_TX_BIAS_LALRM);\n+\tsd->bias_cur[HWARN] = OFFSET_TO_U16(SFF_8636_TX_BIAS_HWARN);\n+\tsd->bias_cur[LWARN] = OFFSET_TO_U16(SFF_8636_TX_BIAS_LWARN);\n+\n+\tsd->tx_power[HALRM] = OFFSET_TO_U16(SFF_8636_TX_PWR_HALRM);\n+\tsd->tx_power[LALRM] = OFFSET_TO_U16(SFF_8636_TX_PWR_LALRM);\n+\tsd->tx_power[HWARN] = OFFSET_TO_U16(SFF_8636_TX_PWR_HWARN);\n+\tsd->tx_power[LWARN] = OFFSET_TO_U16(SFF_8636_TX_PWR_LWARN);\n+\n+\tsd->rx_power[HALRM] = OFFSET_TO_U16(SFF_8636_RX_PWR_HALRM);\n+\tsd->rx_power[LALRM] = OFFSET_TO_U16(SFF_8636_RX_PWR_LALRM);\n+\tsd->rx_power[HWARN] = OFFSET_TO_U16(SFF_8636_RX_PWR_HWARN);\n+\tsd->rx_power[LWARN] = OFFSET_TO_U16(SFF_8636_RX_PWR_LWARN);\n+\n+\n+\t/* Channel Specific Data */\n+\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\n+\t\tuint8_t rx_power_offset, tx_bias_offset;\n+\t\tuint8_t tx_power_offset;\n+\n+\t\tswitch (i) {\n+\t\tcase 0:\n+\t\t\trx_power_offset = SFF_8636_RX_PWR_1_OFFSET;\n+\t\t\ttx_power_offset = SFF_8636_TX_PWR_1_OFFSET;\n+\t\t\ttx_bias_offset = SFF_8636_TX_BIAS_1_OFFSET;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\trx_power_offset = SFF_8636_RX_PWR_2_OFFSET;\n+\t\t\ttx_power_offset = SFF_8636_TX_PWR_2_OFFSET;\n+\t\t\ttx_bias_offset = SFF_8636_TX_BIAS_2_OFFSET;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\trx_power_offset = SFF_8636_RX_PWR_3_OFFSET;\n+\t\t\ttx_power_offset = SFF_8636_TX_PWR_3_OFFSET;\n+\t\t\ttx_bias_offset = SFF_8636_TX_BIAS_3_OFFSET;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\trx_power_offset = SFF_8636_RX_PWR_4_OFFSET;\n+\t\t\ttx_power_offset = SFF_8636_TX_PWR_4_OFFSET;\n+\t\t\ttx_bias_offset = SFF_8636_TX_BIAS_4_OFFSET;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsd->scd[i].bias_cur = OFFSET_TO_U16(tx_bias_offset);\n+\t\tsd->scd[i].rx_power = OFFSET_TO_U16(rx_power_offset);\n+\t\tsd->scd[i].tx_power = OFFSET_TO_U16(tx_power_offset);\n+\t}\n+\n+}\n+\n+static void sff_8636_show_dom(const uint8_t *data, uint32_t eeprom_len, struct sff_item *items)\n+{\n+\tstruct sff_diags sd = {0};\n+\tconst char *rx_power_string = NULL;\n+\tchar power_string[MAX_DESC_SIZE];\n+\tchar val_string[SFF_ITEM_VAL_COMPOSE_SIZE];\n+\tint i;\n+\n+\t/*\n+\t * There is no clear identifier to signify the existence of\n+\t * optical diagnostics similar to SFF-8472. So checking existence\n+\t * of page 3, will provide the gurantee for existence of alarms\n+\t * and thresholds\n+\t * If pagging support exists, then supports_alarms is marked as 1\n+\t */\n+\n+\tif (eeprom_len == RTE_ETH_MODULE_SFF_8636_MAX_LEN) {\n+\t\tif (!(data[SFF_8636_STATUS_2_OFFSET] &\n+\t\t\t\t\tSFF_8636_STATUS_PAGE_3_PRESENT)) {\n+\t\t\tsd.supports_alarms = 1;\n+\t\t}\n+\t}\n+\n+\tsd.rx_power_type = data[SFF_8636_DIAG_TYPE_OFFSET] &\n+\t\t\t\t\t\tSFF_8636_RX_PWR_TYPE_MASK;\n+\tsd.tx_power_type = data[SFF_8636_DIAG_TYPE_OFFSET] &\n+\t\t\t\t\t\tSFF_8636_RX_PWR_TYPE_MASK;\n+\n+\tsff_8636_dom_parse(data, &sd);\n+\n+\tSPRINT_TEMP(val_string, sd.sfp_temp[MCURR]);\n+\tadd_item_string(items, \"Module temperature\", val_string);\n+\n+\tSPRINT_VCC(val_string, sd.sfp_voltage[MCURR]);\n+\tadd_item_string(items, \"Module voltage\", val_string);\n+\n+\t/*\n+\t * SFF-8636/8436 spec is not clear whether RX power/ TX bias\n+\t * current fields are supported or not. A valid temperature\n+\t * reading is used as existence for TX/RX power.\n+\t */\n+\tif ((sd.sfp_temp[MCURR] == 0x0) ||\n+\t    (sd.sfp_temp[MCURR] == (int16_t)0xFFFF))\n+\t\treturn;\n+\n+\tadd_item_string(items, \"Alarm/warning flags implemented\",\n+\t\t\t(sd.supports_alarms ? \"Yes\" : \"No\"));\n+\n+\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\n+\t\tsnprintf(power_string, MAX_DESC_SIZE, \"%s (Channel %d)\",\n+\t\t\t\t\t\"Laser tx bias current\", i+1);\n+\t\tSPRINT_BIAS(val_string, sd.scd[i].bias_cur);\n+\t\tadd_item_string(items, power_string, val_string);\n+\t}\n+\n+\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\n+\t\tsnprintf(power_string, MAX_DESC_SIZE, \"%s (Channel %d)\",\n+\t\t\t\t\t\"Transmit avg optical power\", i+1);\n+\t\tSPRINT_xX_PWR(val_string, sd.scd[i].tx_power);\n+\t\tadd_item_string(items, power_string, val_string);\n+\t}\n+\n+\tif (!sd.rx_power_type)\n+\t\trx_power_string = \"Receiver signal OMA\";\n+\telse\n+\t\trx_power_string = \"Rcvr signal avg optical power\";\n+\n+\tfor (i = 0; i < MAX_CHANNEL_NUM; i++) {\n+\t\tsnprintf(power_string, MAX_DESC_SIZE, \"%s(Channel %d)\",\n+\t\t\t\t\trx_power_string, i+1);\n+\t\tSPRINT_xX_PWR(val_string, sd.scd[i].rx_power);\n+\t\tadd_item_string(items, power_string, val_string);\n+\t}\n+\n+\tif (sd.supports_alarms) {\n+\t\tfor (i = 0; sff_8636_aw_flags[i].str; ++i) {\n+\t\t\tadd_item_string(items, sff_8636_aw_flags[i].str,\n+\t\t\t\t\tdata[sff_8636_aw_flags[i].offset]\n+\t\t\t\t\t& sff_8636_aw_flags[i].value ? \"On\" : \"Off\");\n+\t\t}\n+\n+\t\tsff_show_thresholds(sd, items);\n+\t}\n+\n+}\n+void sff_8636_show_all(const uint8_t *data, uint32_t eeprom_len, struct sff_item *items)\n+{\n+\tsff_8636_show_identifier(data, items);\n+\tif ((data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP) ||\n+\t\t(data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP_PLUS) ||\n+\t\t(data[SFF_8636_ID_OFFSET] == SFF_8024_ID_QSFP28)) {\n+\t\tsff_8636_show_ext_identifier(data, items);\n+\t\tsff_8636_show_connector(data, items);\n+\t\tsff_8636_show_transceiver(data, items);\n+\t\tsff_8636_show_encoding(data, items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_BR_NOMINAL_OFFSET,\n+\t\t\t\t\"BR, Nominal\", 100, \"Mbps\", items);\n+\t\tsff_8636_show_rate_identifier(data, items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_SM_LEN_OFFSET,\n+\t\t\t     \"Length (SMF,km)\", 1, \"km\", items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_OM3_LEN_OFFSET,\n+\t\t\t\t\"Length (OM3 50um)\", 2, \"m\", items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_OM2_LEN_OFFSET,\n+\t\t\t\t\"Length (OM2 50um)\", 1, \"m\", items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_OM1_LEN_OFFSET,\n+\t\t\t     \"Length (OM1 62.5um)\", 1, \"m\", items);\n+\t\tsff_show_value_with_unit(data, SFF_8636_CBL_LEN_OFFSET,\n+\t\t\t     \"Length (Copper or Active cable)\", 1, \"m\", items);\n+\t\tsff_8636_show_wavelength_or_copper_compliance(data, items);\n+\t\tsff_show_ascii(data, SFF_8636_VENDOR_NAME_START_OFFSET,\n+\t\t\t     SFF_8636_VENDOR_NAME_END_OFFSET, \"Vendor name\", items);\n+\t\tsff_8636_show_oui(data, items);\n+\t\tsff_show_ascii(data, SFF_8636_VENDOR_PN_START_OFFSET,\n+\t\t\t     SFF_8636_VENDOR_PN_END_OFFSET, \"Vendor PN\", items);\n+\t\tsff_show_ascii(data, SFF_8636_VENDOR_REV_START_OFFSET,\n+\t\t\t     SFF_8636_VENDOR_REV_END_OFFSET, \"Vendor rev\", items);\n+\t\tsff_show_ascii(data, SFF_8636_VENDOR_SN_START_OFFSET,\n+\t\t\t     SFF_8636_VENDOR_SN_END_OFFSET, \"Vendor SN\", items);\n+\t\tsff_show_ascii(data, SFF_8636_DATE_YEAR_OFFSET,\n+\t\t\t     SFF_8636_DATE_VENDOR_LOT_OFFSET + 1, \"Date code\", items);\n+\t\tsff_8636_show_revision_compliance(data, items);\n+\t\tsff_8636_show_dom(data, eeprom_len, items);\n+\t}\n+}\ndiff --git a/lib/ethdev/sff_8636.h b/lib/ethdev/sff_8636.h\nnew file mode 100644\nindex 0000000000..fc656775f9\n--- /dev/null\n+++ b/lib/ethdev/sff_8636.h\n@@ -0,0 +1,592 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ *\n+ * SFF-8636 standards based QSFP EEPROM Field Definitions\n+ *\n+ */\n+\n+#ifndef _SFF_8636_H_\n+#define _SFF_8636_H_\n+\n+/*------------------------------------------------------------------------------\n+ *\n+ * QSFP EEPROM data structures\n+ *\n+ * register info from SFF-8636 Rev 2.7\n+ */\n+\n+/*------------------------------------------------------------------------------\n+ *\n+ * Lower Memory Page 00h\n+ * Measurement, Diagnostic and Control Functions\n+ *\n+ */\n+/* Identifier - 0 */\n+/* Values are defined under SFF_8024_ID_OFFSET */\n+#define\tSFF_8636_ID_OFFSET\t0x00\n+\n+#define\tSFF_8636_REV_COMPLIANCE_OFFSET\t0x01\n+#define\tSFF_8636_REV_UNSPECIFIED\t\t0x00\n+#define\tSFF_8636_REV_8436_48\t\t\t0x01\n+#define\tSFF_8636_REV_8436_8636\t\t\t0x02\n+#define\tSFF_8636_REV_8636_13\t\t\t0x03\n+#define\tSFF_8636_REV_8636_14\t\t\t0x04\n+#define\tSFF_8636_REV_8636_15\t\t\t0x05\n+#define\tSFF_8636_REV_8636_20\t\t\t0x06\n+#define\tSFF_8636_REV_8636_27\t\t\t0x07\n+\n+#define\tSFF_8636_STATUS_2_OFFSET\t0x02\n+/* Flat Memory:0- Paging, 1- Page 0 only */\n+#define\tSFF_8636_STATUS_PAGE_3_PRESENT\t\t(1 << 2)\n+#define\tSFF_8636_STATUS_INTL_OUTPUT\t\t(1 << 1)\n+#define\tSFF_8636_STATUS_DATA_NOT_READY\t\t(1 << 0)\n+\n+/* Channel Status Interrupt Flags - 3-5 */\n+#define\tSFF_8636_LOS_AW_OFFSET\t0x03\n+#define\tSFF_8636_TX4_LOS_AW\t\t(1 << 7)\n+#define\tSFF_8636_TX3_LOS_AW\t\t(1 << 6)\n+#define\tSFF_8636_TX2_LOS_AW\t\t(1 << 5)\n+#define\tSFF_8636_TX1_LOS_AW\t\t(1 << 4)\n+#define\tSFF_8636_RX4_LOS_AW\t\t(1 << 3)\n+#define\tSFF_8636_RX3_LOS_AW\t\t(1 << 2)\n+#define\tSFF_8636_RX2_LOS_AW\t\t(1 << 1)\n+#define\tSFF_8636_RX1_LOS_AW\t\t(1 << 0)\n+\n+#define\tSFF_8636_FAULT_AW_OFFSET\t0x04\n+#define\tSFF_8636_TX4_FAULT_AW\t(1 << 3)\n+#define\tSFF_8636_TX3_FAULT_AW\t(1 << 2)\n+#define\tSFF_8636_TX2_FAULT_AW\t(1 << 1)\n+#define\tSFF_8636_TX1_FAULT_AW\t(1 << 0)\n+\n+/* Module Monitor Interrupt Flags - 6-8 */\n+#define\tSFF_8636_TEMP_AW_OFFSET\t0x06\n+#define\tSFF_8636_TEMP_HALARM_STATUS\t\t(1 << 7)\n+#define\tSFF_8636_TEMP_LALARM_STATUS\t\t(1 << 6)\n+#define\tSFF_8636_TEMP_HWARN_STATUS\t\t(1 << 5)\n+#define\tSFF_8636_TEMP_LWARN_STATUS\t\t(1 << 4)\n+\n+#define\tSFF_8636_VCC_AW_OFFSET\t0x07\n+#define\tSFF_8636_VCC_HALARM_STATUS\t\t(1 << 7)\n+#define\tSFF_8636_VCC_LALARM_STATUS\t\t(1 << 6)\n+#define\tSFF_8636_VCC_HWARN_STATUS\t\t(1 << 5)\n+#define\tSFF_8636_VCC_LWARN_STATUS\t\t(1 << 4)\n+\n+/* Channel Monitor Interrupt Flags - 9-21 */\n+#define\tSFF_8636_RX_PWR_12_AW_OFFSET\t0x09\n+#define\tSFF_8636_RX_PWR_1_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_RX_PWR_1_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_RX_PWR_1_HWARN\t\t\t(1 << 5)\n+#define\tSFF_8636_RX_PWR_1_LWARN\t\t\t(1 << 4)\n+#define\tSFF_8636_RX_PWR_2_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_RX_PWR_2_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_RX_PWR_2_HWARN\t\t\t(1 << 1)\n+#define\tSFF_8636_RX_PWR_2_LWARN\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_RX_PWR_34_AW_OFFSET\t0x0A\n+#define\tSFF_8636_RX_PWR_3_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_RX_PWR_3_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_RX_PWR_3_HWARN\t\t\t(1 << 5)\n+#define\tSFF_8636_RX_PWR_3_LWARN\t\t\t(1 << 4)\n+#define\tSFF_8636_RX_PWR_4_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_RX_PWR_4_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_RX_PWR_4_HWARN\t\t\t(1 << 1)\n+#define\tSFF_8636_RX_PWR_4_LWARN\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_TX_BIAS_12_AW_OFFSET\t0x0B\n+#define\tSFF_8636_TX_BIAS_1_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_TX_BIAS_1_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_TX_BIAS_1_HWARN\t\t(1 << 5)\n+#define\tSFF_8636_TX_BIAS_1_LWARN\t\t(1 << 4)\n+#define\tSFF_8636_TX_BIAS_2_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_TX_BIAS_2_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_TX_BIAS_2_HWARN\t\t(1 << 1)\n+#define\tSFF_8636_TX_BIAS_2_LWARN\t\t(1 << 0)\n+\n+#define\tSFF_8636_TX_BIAS_34_AW_OFFSET\t0xC\n+#define\tSFF_8636_TX_BIAS_3_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_TX_BIAS_3_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_TX_BIAS_3_HWARN\t\t(1 << 5)\n+#define\tSFF_8636_TX_BIAS_3_LWARN\t\t(1 << 4)\n+#define\tSFF_8636_TX_BIAS_4_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_TX_BIAS_4_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_TX_BIAS_4_HWARN\t\t(1 << 1)\n+#define\tSFF_8636_TX_BIAS_4_LWARN\t\t(1 << 0)\n+\n+#define\tSFF_8636_TX_PWR_12_AW_OFFSET\t0x0D\n+#define\tSFF_8636_TX_PWR_1_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_TX_PWR_1_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_TX_PWR_1_HWARN\t\t\t(1 << 5)\n+#define\tSFF_8636_TX_PWR_1_LWARN\t\t\t(1 << 4)\n+#define\tSFF_8636_TX_PWR_2_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_TX_PWR_2_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_TX_PWR_2_HWARN\t\t\t(1 << 1)\n+#define\tSFF_8636_TX_PWR_2_LWARN\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_TX_PWR_34_AW_OFFSET\t0x0E\n+#define\tSFF_8636_TX_PWR_3_HALARM\t\t(1 << 7)\n+#define\tSFF_8636_TX_PWR_3_LALARM\t\t(1 << 6)\n+#define\tSFF_8636_TX_PWR_3_HWARN\t\t\t(1 << 5)\n+#define\tSFF_8636_TX_PWR_3_LWARN\t\t\t(1 << 4)\n+#define\tSFF_8636_TX_PWR_4_HALARM\t\t(1 << 3)\n+#define\tSFF_8636_TX_PWR_4_LALARM\t\t(1 << 2)\n+#define\tSFF_8636_TX_PWR_4_HWARN\t\t\t(1 << 1)\n+#define\tSFF_8636_TX_PWR_4_LWARN\t\t\t(1 << 0)\n+\n+/* Module Monitoring Values - 22-33 */\n+#define\tSFF_8636_TEMP_CURR\t\t0x16\n+#define\tSFF_8636_TEMP_MSB_OFFSET\t\t0x16\n+#define\tSFF_8636_TEMP_LSB_OFFSET\t\t0x17\n+\n+#define\tSFF_8636_VCC_CURR\t\t0x1A\n+#define\tSFF_8636_VCC_MSB_OFFSET\t\t0x1A\n+#define\tSFF_8636_VCC_LSB_OFFSET\t\t0x1B\n+\n+/* Channel Monitoring Values - 34-81 */\n+#define\tSFF_8636_RX_PWR_1_OFFSET\t\t0x22\n+#define\tSFF_8636_RX_PWR_2_OFFSET\t\t0x24\n+#define\tSFF_8636_RX_PWR_3_OFFSET\t\t0x26\n+#define\tSFF_8636_RX_PWR_4_OFFSET\t\t0x28\n+\n+#define\tSFF_8636_TX_BIAS_1_OFFSET\t0x2A\n+#define\tSFF_8636_TX_BIAS_2_OFFSET\t0x2C\n+#define\tSFF_8636_TX_BIAS_3_OFFSET\t0x2E\n+#define\tSFF_8636_TX_BIAS_4_OFFSET\t0x30\n+\n+#define\tSFF_8636_TX_PWR_1_OFFSET\t\t0x32\n+#define\tSFF_8636_TX_PWR_2_OFFSET\t\t0x34\n+#define\tSFF_8636_TX_PWR_3_OFFSET\t\t0x36\n+#define\tSFF_8636_TX_PWR_4_OFFSET\t\t0x38\n+\n+/* Control Bytes - 86 - 99 */\n+#define\tSFF_8636_TX_DISABLE_OFFSET\t0x56\n+#define\tSFF_8636_TX_DISABLE_4\t\t\t(1 << 3)\n+#define\tSFF_8636_TX_DISABLE_3\t\t\t(1 << 2)\n+#define\tSFF_8636_TX_DISABLE_2\t\t\t(1 << 1)\n+#define\tSFF_8636_TX_DISABLE_1\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_RX_RATE_SELECT_OFFSET\t0x57\n+#define\tSFF_8636_RX_RATE_SELECT_4_MASK\t\t(3 << 6)\n+#define\tSFF_8636_RX_RATE_SELECT_3_MASK\t\t(3 << 4)\n+#define\tSFF_8636_RX_RATE_SELECT_2_MASK\t\t(3 << 2)\n+#define\tSFF_8636_RX_RATE_SELECT_1_MASK\t\t(3 << 0)\n+\n+#define\tSFF_8636_TX_RATE_SELECT_OFFSET\t0x58\n+#define\tSFF_8636_TX_RATE_SELECT_4_MASK\t\t(3 << 6)\n+#define\tSFF_8636_TX_RATE_SELECT_3_MASK\t\t(3 << 4)\n+#define\tSFF_8636_TX_RATE_SELECT_2_MASK\t\t(3 << 2)\n+#define\tSFF_8636_TX_RATE_SELECT_1_MASK\t\t(3 << 0)\n+\n+#define\tSFF_8636_RX_APP_SELECT_4_OFFSET\t0x58\n+#define\tSFF_8636_RX_APP_SELECT_3_OFFSET\t0x59\n+#define\tSFF_8636_RX_APP_SELECT_2_OFFSET\t0x5A\n+#define\tSFF_8636_RX_APP_SELECT_1_OFFSET\t0x5B\n+\n+#define\tSFF_8636_PWR_MODE_OFFSET\t\t0x5D\n+#define\tSFF_8636_HIGH_PWR_ENABLE\t\t(1 << 2)\n+#define\tSFF_8636_LOW_PWR_MODE\t\t\t(1 << 1)\n+#define\tSFF_8636_PWR_OVERRIDE\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_TX_APP_SELECT_4_OFFSET\t0x5E\n+#define\tSFF_8636_TX_APP_SELECT_3_OFFSET\t0x5F\n+#define\tSFF_8636_TX_APP_SELECT_2_OFFSET\t0x60\n+#define\tSFF_8636_TX_APP_SELECT_1_OFFSET\t0x61\n+\n+#define\tSFF_8636_LOS_MASK_OFFSET\t\t0x64\n+#define\tSFF_8636_TX_LOS_4_MASK\t\t\t(1 << 7)\n+#define\tSFF_8636_TX_LOS_3_MASK\t\t\t(1 << 6)\n+#define\tSFF_8636_TX_LOS_2_MASK\t\t\t(1 << 5)\n+#define\tSFF_8636_TX_LOS_1_MASK\t\t\t(1 << 4)\n+#define\tSFF_8636_RX_LOS_4_MASK\t\t\t(1 << 3)\n+#define\tSFF_8636_RX_LOS_3_MASK\t\t\t(1 << 2)\n+#define\tSFF_8636_RX_LOS_2_MASK\t\t\t(1 << 1)\n+#define\tSFF_8636_RX_LOS_1_MASK\t\t\t(1 << 0)\n+\n+#define\tSFF_8636_FAULT_MASK_OFFSET\t0x65\n+#define\tSFF_8636_TX_FAULT_1_MASK\t\t(1 << 3)\n+#define\tSFF_8636_TX_FAULT_2_MASK\t\t(1 << 2)\n+#define\tSFF_8636_TX_FAULT_3_MASK\t\t(1 << 1)\n+#define\tSFF_8636_TX_FAULT_4_MASK\t\t(1 << 0)\n+\n+#define\tSFF_8636_TEMP_MASK_OFFSET\t0x67\n+#define\tSFF_8636_TEMP_HALARM_MASK\t\t(1 << 7)\n+#define\tSFF_8636_TEMP_LALARM_MASK\t\t(1 << 6)\n+#define\tSFF_8636_TEMP_HWARN_MASK\t\t(1 << 5)\n+#define\tSFF_8636_TEMP_LWARN_MASK\t\t(1 << 4)\n+\n+#define\tSFF_8636_VCC_MASK_OFFSET\t\t0x68\n+#define\tSFF_8636_VCC_HALARM_MASK\t\t(1 << 7)\n+#define\tSFF_8636_VCC_LALARM_MASK\t\t(1 << 6)\n+#define\tSFF_8636_VCC_HWARN_MASK\t\t\t(1 << 5)\n+#define\tSFF_8636_VCC_LWARN_MASK\t\t\t(1 << 4)\n+\n+/*------------------------------------------------------------------------------\n+ *\n+ * Upper Memory Page 00h\n+ * Serial ID - Base ID, Extended ID and Vendor Specific ID fields\n+ *\n+ */\n+/* Identifier - 128 */\n+/* Identifier values same as Lower Memory Page 00h */\n+#define\tSFF_8636_UPPER_PAGE_0_ID_OFFSET\t\t0x80\n+\n+/* Extended Identifier - 128 */\n+#define SFF_8636_EXT_ID_OFFSET\t\t0x81\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_MASK\t\t0xC0\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_1\t\t(0 << 6)\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_2\t\t(1 << 6)\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_3\t\t(2 << 6)\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_4\t\t(3 << 6)\n+#define\tSFF_8636_EXT_ID_CLIE_MASK\t\t0x10\n+#define\tSFF_8636_EXT_ID_CLIEI_CODE_PRESENT\t(1 << 4)\n+#define\tSFF_8636_EXT_ID_CDR_TX_MASK\t\t0x08\n+#define\tSFF_8636_EXT_ID_CDR_TX_PRESENT\t\t(1 << 3)\n+#define\tSFF_8636_EXT_ID_CDR_RX_MASK\t\t0x04\n+#define\tSFF_8636_EXT_ID_CDR_RX_PRESENT\t\t(1 << 2)\n+#define\tSFF_8636_EXT_ID_EPWR_CLASS_MASK\t\t0x03\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_LEGACY\t0\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_5\t\t1\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_6\t\t2\n+#define\tSFF_8636_EXT_ID_PWR_CLASS_7\t\t3\n+\n+/* Connector Values offset - 130 */\n+/* Values are defined under SFF_8024_CTOR */\n+#define\tSFF_8636_CTOR_OFFSET\t\t0x82\n+#define\tSFF_8636_CTOR_UNKNOWN\t\t\t0x00\n+#define\tSFF_8636_CTOR_SC\t\t\t0x01\n+#define\tSFF_8636_CTOR_FC_STYLE_1\t\t0x02\n+#define\tSFF_8636_CTOR_FC_STYLE_2\t\t0x03\n+#define\tSFF_8636_CTOR_BNC_TNC\t\t\t0x04\n+#define\tSFF_8636_CTOR_FC_COAX\t\t\t0x05\n+#define\tSFF_8636_CTOR_FIBER_JACK\t\t0x06\n+#define\tSFF_8636_CTOR_LC\t\t\t0x07\n+#define\tSFF_8636_CTOR_MT_RJ\t\t\t0x08\n+#define\tSFF_8636_CTOR_MU\t\t\t0x09\n+#define\tSFF_8636_CTOR_SG\t\t\t0x0A\n+#define\tSFF_8636_CTOR_OPT_PT\t\t\t0x0B\n+#define\tSFF_8636_CTOR_MPO\t\t\t0x0C\n+/* 0D-1Fh --- Reserved */\n+#define\tSFF_8636_CTOR_HSDC_II\t\t\t0x20\n+#define\tSFF_8636_CTOR_COPPER_PT\t\t\t0x21\n+#define\tSFF_8636_CTOR_RJ45\t\t\t0x22\n+#define\tSFF_8636_CTOR_NO_SEPARABLE\t\t0x23\n+#define\tSFF_8636_CTOR_MXC_2X16\t\t\t0x24\n+\n+/* Specification Compliance - 131-138 */\n+/* Ethernet Compliance Codes - 131 */\n+#define\tSFF_8636_ETHERNET_COMP_OFFSET\t0x83\n+#define\tSFF_8636_ETHERNET_RSRVD\t\t\t(1 << 7)\n+#define\tSFF_8636_ETHERNET_10G_LRM\t\t(1 << 6)\n+#define\tSFF_8636_ETHERNET_10G_LR\t\t(1 << 5)\n+#define\tSFF_8636_ETHERNET_10G_SR\t\t(1 << 4)\n+#define\tSFF_8636_ETHERNET_40G_CR4\t\t(1 << 3)\n+#define\tSFF_8636_ETHERNET_40G_SR4\t\t(1 << 2)\n+#define\tSFF_8636_ETHERNET_40G_LR4\t\t(1 << 1)\n+#define\tSFF_8636_ETHERNET_40G_ACTIVE\t(1 << 0)\n+\n+/* SONET Compliance Codes - 132 */\n+#define\tSFF_8636_SONET_COMP_OFFSET\t0x84\n+#define\tSFF_8636_SONET_40G_OTN\t\t\t(1 << 3)\n+#define\tSFF_8636_SONET_OC48_LR\t\t\t(1 << 2)\n+#define\tSFF_8636_SONET_OC48_IR\t\t\t(1 << 1)\n+#define\tSFF_8636_SONET_OC48_SR\t\t\t(1 << 0)\n+\n+/* SAS/SATA Complaince Codes - 133 */\n+#define\tSFF_8636_SAS_COMP_OFFSET\t\t0x85\n+#define\tSFF_8636_SAS_12G\t\t\t(1 << 6)\n+#define\tSFF_8636_SAS_6G\t\t\t\t(1 << 5)\n+#define\tSFF_8636_SAS_3G\t\t\t\t(1 << 4)\n+\n+/* Gigabit Ethernet Compliance Codes - 134 */\n+#define\tSFF_8636_GIGE_COMP_OFFSET\t0x86\n+#define\tSFF_8636_GIGE_1000_BASE_T\t\t(1 << 3)\n+#define\tSFF_8636_GIGE_1000_BASE_CX\t\t(1 << 2)\n+#define\tSFF_8636_GIGE_1000_BASE_LX\t\t(1 << 1)\n+#define\tSFF_8636_GIGE_1000_BASE_SX\t\t(1 << 0)\n+\n+/* Fibre Channel Link length/Transmitter Tech. - 135,136 */\n+#define\tSFF_8636_FC_LEN_OFFSET\t\t0x87\n+#define\tSFF_8636_FC_LEN_VERY_LONG\t\t(1 << 7)\n+#define\tSFF_8636_FC_LEN_SHORT\t\t\t(1 << 6)\n+#define\tSFF_8636_FC_LEN_INT\t\t\t(1 << 5)\n+#define\tSFF_8636_FC_LEN_LONG\t\t\t(1 << 4)\n+#define\tSFF_8636_FC_LEN_MED\t\t\t(1 << 3)\n+#define\tSFF_8636_FC_TECH_LONG_LC\t\t(1 << 1)\n+#define\tSFF_8636_FC_TECH_ELEC_INTER\t\t(1 << 0)\n+\n+#define\tSFF_8636_FC_TECH_OFFSET\t\t0x88\n+#define\tSFF_8636_FC_TECH_ELEC_INTRA\t\t(1 << 7)\n+#define\tSFF_8636_FC_TECH_SHORT_WO_OFC\t\t(1 << 6)\n+#define\tSFF_8636_FC_TECH_SHORT_W_OFC\t\t(1 << 5)\n+#define\tSFF_8636_FC_TECH_LONG_LL\t\t(1 << 4)\n+\n+/* Fibre Channel Transmitter Media - 137 */\n+#define\tSFF_8636_FC_TRANS_MEDIA_OFFSET\t0x89\n+/* Twin Axial Pair */\n+#define\tSFF_8636_FC_TRANS_MEDIA_TW\t\t(1 << 7)\n+/* Shielded Twisted Pair */\n+#define\tSFF_8636_FC_TRANS_MEDIA_TP\t\t(1 << 6)\n+/* Miniature Coax */\n+#define\tSFF_8636_FC_TRANS_MEDIA_MI\t\t(1 << 5)\n+/* Video Coax */\n+#define\tSFF_8636_FC_TRANS_MEDIA_TV\t\t(1 << 4)\n+/* Multi-mode 62.5m */\n+#define\tSFF_8636_FC_TRANS_MEDIA_M6\t\t(1 << 3)\n+/* Multi-mode 50m */\n+#define\tSFF_8636_FC_TRANS_MEDIA_M5\t\t(1 << 2)\n+/* Multi-mode 50um */\n+#define\tSFF_8636_FC_TRANS_MEDIA_OM3\t\t(1 << 1)\n+/* Single Mode */\n+#define\tSFF_8636_FC_TRANS_MEDIA_SM\t\t(1 << 0)\n+\n+/* Fibre Channel Speed - 138 */\n+#define\tSFF_8636_FC_SPEED_OFFSET\t\t0x8A\n+#define\tSFF_8636_FC_SPEED_1200_MBPS\t\t(1 << 7)\n+#define\tSFF_8636_FC_SPEED_800_MBPS\t\t(1 << 6)\n+#define\tSFF_8636_FC_SPEED_1600_MBPS\t\t(1 << 5)\n+#define\tSFF_8636_FC_SPEED_400_MBPS\t\t(1 << 4)\n+#define\tSFF_8636_FC_SPEED_200_MBPS\t\t(1 << 2)\n+#define\tSFF_8636_FC_SPEED_100_MBPS\t\t(1 << 0)\n+\n+/* Encoding - 139 */\n+/* Values are defined under SFF_8024_ENCODING */\n+#define\tSFF_8636_ENCODING_OFFSET\t\t0x8B\n+#define\tSFF_8636_ENCODING_MANCHESTER\t0x06\n+#define\tSFF_8636_ENCODING_64B66B\t\t0x05\n+#define\tSFF_8636_ENCODING_SONET\t\t\t0x04\n+#define\tSFF_8636_ENCODING_NRZ\t\t\t0x03\n+#define\tSFF_8636_ENCODING_4B5B\t\t\t0x02\n+#define\tSFF_8636_ENCODING_8B10B\t\t\t0x01\n+#define\tSFF_8636_ENCODING_UNSPEC\t\t0x00\n+\n+/* BR, Nominal - 140 */\n+#define\tSFF_8636_BR_NOMINAL_OFFSET\t0x8C\n+\n+/* Extended RateSelect - 141 */\n+#define\tSFF_8636_EXT_RS_OFFSET\t\t0x8D\n+#define\tSFF_8636_EXT_RS_V1\t\t\t(1 << 0)\n+\n+/* Length (Standard SM Fiber)-km - 142 */\n+#define\tSFF_8636_SM_LEN_OFFSET\t\t0x8E\n+\n+/* Length (OM3)-Unit 2m - 143 */\n+#define\tSFF_8636_OM3_LEN_OFFSET\t\t0x8F\n+\n+/* Length (OM2)-Unit 1m - 144 */\n+#define\tSFF_8636_OM2_LEN_OFFSET\t\t0x90\n+\n+/* Length (OM1)-Unit 1m - 145 */\n+#define\tSFF_8636_OM1_LEN_OFFSET\t\t0x91\n+\n+/* Cable Assembly Length -Unit 1m - 146 */\n+#define\tSFF_8636_CBL_LEN_OFFSET\t\t0x92\n+\n+/* Device Technology - 147 */\n+#define\tSFF_8636_DEVICE_TECH_OFFSET\t0x93\n+/* Transmitter Technology */\n+#define\tSFF_8636_TRANS_TECH_MASK\t\t0xF0\n+/* Copper cable, linear active equalizers */\n+#define\tSFF_8636_TRANS_COPPER_LNR_EQUAL\t\t(15 << 4)\n+/* Copper cable, near end limiting active equalizers */\n+#define\tSFF_8636_TRANS_COPPER_NEAR_EQUAL\t(14 << 4)\n+/* Copper cable, far end limiting active equalizers */\n+#define\tSFF_8636_TRANS_COPPER_FAR_EQUAL\t\t(13 << 4)\n+/* Copper cable, near & far end limiting active equalizers */\n+#define\tSFF_8636_TRANS_COPPER_LNR_FAR_EQUAL\t(12 << 4)\n+/* Copper cable, passive equalized */\n+#define\tSFF_8636_TRANS_COPPER_PAS_EQUAL\t\t(11 << 4)\n+/* Copper cable, unequalized */\n+#define\tSFF_8636_TRANS_COPPER_PAS_UNEQUAL\t(10 << 4)\n+/* 1490 nm DFB */\n+#define\tSFF_8636_TRANS_1490_DFB\t\t\t(9 << 4)\n+/* Others */\n+#define\tSFF_8636_TRANS_OTHERS\t\t\t(8 << 4)\n+/* 1550 nm EML */\n+#define\tSFF_8636_TRANS_1550_EML\t\t\t(7 << 4)\n+/* 1310 nm EML */\n+#define\tSFF_8636_TRANS_1310_EML\t\t\t(6 << 4)\n+/* 1550 nm DFB */\n+#define\tSFF_8636_TRANS_1550_DFB\t\t\t(5 << 4)\n+/* 1310 nm DFB */\n+#define\tSFF_8636_TRANS_1310_DFB\t\t\t(4 << 4)\n+/* 1310 nm FP */\n+#define\tSFF_8636_TRANS_1310_FP\t\t\t(3 << 4)\n+/* 1550 nm VCSEL */\n+#define\tSFF_8636_TRANS_1550_VCSEL\t\t(2 << 4)\n+/* 1310 nm VCSEL */\n+#define\tSFF_8636_TRANS_1310_VCSEL\t\t(1 << 4)\n+/* 850 nm VCSEL */\n+#define\tSFF_8636_TRANS_850_VCSEL\t\t(0 << 4)\n+\n+ /* Active/No wavelength control */\n+#define\tSFF_8636_DEV_TECH_ACTIVE_WAVE_LEN\t(1 << 3)\n+/* Cooled transmitter */\n+#define\tSFF_8636_DEV_TECH_COOL_TRANS\t\t(1 << 2)\n+/* APD/Pin Detector */\n+#define\tSFF_8636_DEV_TECH_APD_DETECTOR\t\t(1 << 1)\n+/* Transmitter tunable */\n+#define\tSFF_8636_DEV_TECH_TUNABLE\t\t(1 << 0)\n+\n+/* Vendor Name - 148-163 */\n+#define\tSFF_8636_VENDOR_NAME_START_OFFSET\t0x94\n+#define\tSFF_8636_VENDOR_NAME_END_OFFSET\t\t0xA3\n+\n+/* Extended Module Codes - 164 */\n+#define\tSFF_8636_EXT_MOD_CODE_OFFSET\t0xA4\n+#define\tSFF_8636_EXT_MOD_INFINIBAND_EDR\t(1 << 4)\n+#define\tSFF_8636_EXT_MOD_INFINIBAND_FDR\t(1 << 3)\n+#define\tSFF_8636_EXT_MOD_INFINIBAND_QDR\t(1 << 2)\n+#define\tSFF_8636_EXT_MOD_INFINIBAND_DDR\t(1 << 1)\n+#define\tSFF_8636_EXT_MOD_INFINIBAND_SDR\t(1 << 0)\n+\n+/* Vendor OUI - 165-167 */\n+#define\tSFF_8636_VENDOR_OUI_OFFSET\t\t0xA5\n+#define\tSFF_8636_VENDOR_OUI_LEN\t\t3\n+\n+/* Vendor OUI - 165-167 */\n+#define\tSFF_8636_VENDOR_PN_START_OFFSET\t\t0xA8\n+#define\tSFF_8636_VENDOR_PN_END_OFFSET\t\t0xB7\n+\n+/* Vendor Revision - 184-185 */\n+#define\tSFF_8636_VENDOR_REV_START_OFFSET\t0xB8\n+#define\tSFF_8636_VENDOR_REV_END_OFFSET\t\t0xB9\n+\n+/* Wavelength - 186-187 */\n+#define\tSFF_8636_WAVELEN_HIGH_BYTE_OFFSET\t0xBA\n+#define\tSFF_8636_WAVELEN_LOW_BYTE_OFFSET\t0xBB\n+\n+/* Wavelength  Tolerance- 188-189 */\n+#define\tSFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET\t0xBC\n+#define\tSFF_8636_WAVE_TOL_LOW_BYTE_OFFSET\t0xBD\n+\n+/* Max case temp - Other than 70 C - 190 */\n+#define\tSFF_8636_MAXCASE_TEMP_OFFSET\t0xBE\n+\n+/* CC_BASE - 191 */\n+#define\tSFF_8636_CC_BASE_OFFSET\t\t0xBF\n+\n+/* Option Values - 192-195 */\n+#define\tSFF_8636_OPTION_1_OFFSET\t0xC0\n+#define\tSFF_8636_ETHERNET_UNSPECIFIED\t\t0x00\n+#define\tSFF_8636_ETHERNET_100G_AOC\t\t0x01\n+#define\tSFF_8636_ETHERNET_100G_SR4\t\t0x02\n+#define\tSFF_8636_ETHERNET_100G_LR4\t\t0x03\n+#define\tSFF_8636_ETHERNET_100G_ER4\t\t0x04\n+#define\tSFF_8636_ETHERNET_100G_SR10\t\t0x05\n+#define\tSFF_8636_ETHERNET_100G_CWDM4_FEC\t0x06\n+#define\tSFF_8636_ETHERNET_100G_PSM4\t\t0x07\n+#define\tSFF_8636_ETHERNET_100G_ACC\t\t0x08\n+#define\tSFF_8636_ETHERNET_100G_CWDM4_NO_FEC\t0x09\n+#define\tSFF_8636_ETHERNET_100G_RSVD1\t\t0x0A\n+#define\tSFF_8636_ETHERNET_100G_CR4\t\t0x0B\n+#define\tSFF_8636_ETHERNET_25G_CR_CA_S\t\t0x0C\n+#define\tSFF_8636_ETHERNET_25G_CR_CA_N\t\t0x0D\n+#define\tSFF_8636_ETHERNET_40G_ER4\t\t0x10\n+#define\tSFF_8636_ETHERNET_4X10_SR\t\t0x11\n+#define\tSFF_8636_ETHERNET_40G_PSM4\t\t0x12\n+#define\tSFF_8636_ETHERNET_G959_P1I1_2D1\t\t0x13\n+#define\tSFF_8636_ETHERNET_G959_P1S1_2D2\t\t0x14\n+#define\tSFF_8636_ETHERNET_G959_P1L1_2D2\t\t0x15\n+#define\tSFF_8636_ETHERNET_10GT_SFI\t\t0x16\n+#define\tSFF_8636_ETHERNET_100G_CLR4\t\t0x17\n+#define\tSFF_8636_ETHERNET_100G_AOC2\t\t0x18\n+#define\tSFF_8636_ETHERNET_100G_ACC2\t\t0x19\n+\n+#define\tSFF_8636_OPTION_2_OFFSET\t0xC1\n+/* Rx output amplitude */\n+#define\tSFF_8636_O2_RX_OUTPUT_AMP\t(1 << 0)\n+#define\tSFF_8636_OPTION_3_OFFSET\t0xC2\n+/* Rx Squelch Disable */\n+#define\tSFF_8636_O3_RX_SQL_DSBL\t(1 << 3)\n+/* Rx Output Disable capable */\n+#define\tSFF_8636_O3_RX_OUTPUT_DSBL\t(1 << 2)\n+/* Tx Squelch Disable */\n+#define\tSFF_8636_O3_TX_SQL_DSBL\t(1 << 1)\n+/* Tx Squelch Impl */\n+#define\tSFF_8636_O3_TX_SQL_IMPL\t(1 << 0)\n+#define\tSFF_8636_OPTION_4_OFFSET\t0xC3\n+/* Memory Page 02 present */\n+#define\tSFF_8636_O4_PAGE_02_PRESENT\t(1 << 7)\n+/* Memory Page 01 present */\n+#define\tSFF_8636_O4_PAGE_01_PRESENT\t(1 << 6)\n+/* Rate Select implemented */\n+#define\tSFF_8636_O4_RATE_SELECT\t(1 << 5)\n+/* Tx_DISABLE implemented */\n+#define\tSFF_8636_O4_TX_DISABLE\t\t(1 << 4)\n+/* Tx_FAULT implemented */\n+#define\tSFF_8636_O4_TX_FAULT\t\t(1 << 3)\n+/* Tx Squelch implemented */\n+#define\tSFF_8636_O4_TX_SQUELCH\t\t(1 << 2)\n+/* Tx Loss of Signal */\n+#define\tSFF_8636_O4_TX_LOS\t\t(1 << 1)\n+\n+/* Vendor SN - 196-211 */\n+#define\tSFF_8636_VENDOR_SN_START_OFFSET\t0xC4\n+#define\tSFF_8636_VENDOR_SN_END_OFFSET\t0xD3\n+\n+/* Vendor Date - 212-219 */\n+#define\tSFF_8636_DATE_YEAR_OFFSET\t0xD4\n+#define\tSFF_8636_DATE_YEAR_LEN\t\t\t2\n+#define\tSFF_8636_DATE_MONTH_OFFSET\t0xD6\n+#define\tSFF_8636_DATE_MONTH_LEN\t\t2\n+#define\tSFF_8636_DATE_DAY_OFFSET\t0xD8\n+#define\tSFF_8636_DATE_DAY_LEN\t\t\t2\n+#define\tSFF_8636_DATE_VENDOR_LOT_OFFSET 0xDA\n+#define\tSFF_8636_DATE_VENDOR_LOT_LEN\t\t2\n+\n+/* Diagnostic Monitoring Type - 220 */\n+#define\tSFF_8636_DIAG_TYPE_OFFSET\t0xDC\n+#define\tSFF_8636_RX_PWR_TYPE_MASK\t0x8\n+#define\t SFF_8636_RX_PWR_TYPE_AVG_PWR\t(1 << 3)\n+#define\t SFF_8636_RX_PWR_TYPE_OMA\t(0 << 3)\n+#define\tSFF_8636_TX_PWR_TYPE_MASK\t0x4\n+#define\t SFF_8636_TX_PWR_TYPE_AVG_PWR\t(1 << 2)\n+\n+/* Enhanced Options - 221 */\n+#define\tSFF_8636_ENH_OPTIONS_OFFSET\t0xDD\n+#define\tSFF_8636_RATE_SELECT_EXT_SUPPORT\t(1 << 3)\n+#define\tSFF_8636_RATE_SELECT_APP_TABLE_SUPPORT\t(1 << 2)\n+\n+/* Check code - 223 */\n+#define\tSFF_8636_CC_EXT_OFFSET\t\t0xDF\n+#define\tSFF_8636_CC_EXT_LEN\t\t1\n+\n+/*------------------------------------------------------------------------------\n+ *\n+ * Upper Memory Page 03h\n+ * Contains module thresholds, channel thresholds and masks,\n+ * and optional channel controls\n+ *\n+ * Offset - Page Num(3) * PageSize(0x80) + Page offset\n+ */\n+\n+/* Module Thresholds (48 Bytes) 128-175 */\n+/* MSB at low address, LSB at high address */\n+#define\tSFF_8636_TEMP_HALRM\t\t0x200\n+#define\tSFF_8636_TEMP_LALRM\t\t0x202\n+#define\tSFF_8636_TEMP_HWARN\t\t0x204\n+#define\tSFF_8636_TEMP_LWARN\t\t0x206\n+\n+#define\tSFF_8636_VCC_HALRM\t\t0x210\n+#define\tSFF_8636_VCC_LALRM\t\t0x212\n+#define\tSFF_8636_VCC_HWARN\t\t0x214\n+#define\tSFF_8636_VCC_LWARN\t\t0x216\n+\n+#define\tSFF_8636_RX_PWR_HALRM\t\t0x230\n+#define\tSFF_8636_RX_PWR_LALRM\t\t0x232\n+#define\tSFF_8636_RX_PWR_HWARN\t\t0x234\n+#define\tSFF_8636_RX_PWR_LWARN\t\t0x236\n+\n+#define\tSFF_8636_TX_BIAS_HALRM\t\t0x238\n+#define\tSFF_8636_TX_BIAS_LALRM\t\t0x23A\n+#define\tSFF_8636_TX_BIAS_HWARN\t\t0x23C\n+#define\tSFF_8636_TX_BIAS_LWARN\t\t0x23E\n+\n+#define\tSFF_8636_TX_PWR_HALRM\t\t0x240\n+#define\tSFF_8636_TX_PWR_LALRM\t\t0x242\n+#define\tSFF_8636_TX_PWR_HWARN\t\t0x244\n+#define\tSFF_8636_TX_PWR_LWARN\t\t0x246\n+\n+#define\tETH_MODULE_SFF_8636_MAX_LEN\t640\n+#define\tETH_MODULE_SFF_8436_MAX_LEN\t640\n+\n+#endif /* _SFF_8636_H_ */\n",
    "prefixes": [
        "v4",
        "5/5"
    ]
}