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GET /api/patches/110058/?format=api
{ "id": 110058, "url": "https://patches.dpdk.org/api/patches/110058/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220422014300.2380259-4-wenjun1.wu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220422014300.2380259-4-wenjun1.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220422014300.2380259-4-wenjun1.wu@intel.com", "date": "2022-04-22T01:43:00", "name": "[v6,3/3] net/iavf: support quanta size configuration", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e2ac37206811d7c5662a7f368f762fc6aee46a80", "submitter": { "id": 2083, "url": "https://patches.dpdk.org/api/people/2083/?format=api", "name": "Wenjun Wu", "email": "wenjun1.wu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220422014300.2380259-4-wenjun1.wu@intel.com/mbox/", "series": [ { "id": 22606, "url": "https://patches.dpdk.org/api/series/22606/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22606", "date": "2022-04-22T01:42:58", "name": "Enable queue rate limit and quanta size configuration", "version": 6, "mbox": "https://patches.dpdk.org/series/22606/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/110058/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/110058/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8412A0093;\n\tFri, 22 Apr 2022 04:05:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 56D7C427F2;\n\tFri, 22 Apr 2022 04:05:05 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 0843440040\n for <dev@dpdk.org>; Fri, 22 Apr 2022 04:05:00 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2022 19:04:51 -0700", "from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2022 19:04:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1650593101; x=1682129101;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=166l1B3uCTtVbFIUJJHqXO98udf0uochzfENNGCyH8E=;\n b=BE6+AqCQb01+e4K1G60E1y0X0md+aaQwQ3lxAvpUYs1Dc+Oqj80fgPEG\n I4oEV3yhBC2MNO1UC8Zhu6hJJ8fFBo0xl8YZNhlB59veceKLdji1aoLVj\n 5nrNqVOncXYkj9fSPGjjRr6Ed/Z9LFVFh5azGZzFU5r2vfwFeWoCEDahW\n ebgUtjZtnPdNWOth8VOcOvVwroQQ9p2mg1p4+ODf3YbuGrIUw8LIW7qdf\n pZydH4mzp2uugk7Tzx+7M+ClBHZfabr2ik7zVXDzPhouiZ1UTBFKN92ze\n 0ZGf+XOMQ6Q4OSgwRBEpQL5ubcg6VrQF8f3dlGLiOWxBDIHewOsVhVlkH g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10324\"; a=\"251865603\"", "E=Sophos;i=\"5.90,280,1643702400\"; d=\"scan'208\";a=\"251865603\"", "E=Sophos;i=\"5.90,280,1643702400\"; d=\"scan'208\";a=\"577596612\"" ], "X-ExtLoop1": "1", "From": "Wenjun Wu <wenjun1.wu@intel.com>", "To": "dev@dpdk.org, jingjing.wu@intel.com, beilei.xing@intel.com,\n qi.z.zhang@intel.com", "Subject": "[PATCH v6 3/3] net/iavf: support quanta size configuration", "Date": "Fri, 22 Apr 2022 09:43:00 +0800", "Message-Id": "<20220422014300.2380259-4-wenjun1.wu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220422014300.2380259-1-wenjun1.wu@intel.com>", "References": "<20220329020717.1101263-1-wenjun1.wu@intel.com>\n <20220422014300.2380259-1-wenjun1.wu@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds quanta size configuration support.\nQuanta size should between 256 and 4096, and be a product of 64.\n\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\n---\n doc/guides/nics/intel_vf.rst | 4 +++\n doc/guides/rel_notes/release_22_07.rst | 1 +\n drivers/net/iavf/iavf.h | 3 ++\n drivers/net/iavf/iavf_ethdev.c | 38 ++++++++++++++++++++++++++\n drivers/net/iavf/iavf_vchnl.c | 31 +++++++++++++++++++++\n 5 files changed, 77 insertions(+)", "diff": "diff --git a/doc/guides/nics/intel_vf.rst b/doc/guides/nics/intel_vf.rst\nindex 648af39c22..6498135655 100644\n--- a/doc/guides/nics/intel_vf.rst\n+++ b/doc/guides/nics/intel_vf.rst\n@@ -92,6 +92,10 @@ For more detail on SR-IOV, please refer to the following documents:\n available for IAVF PMD. The same devargs with the same parameters can be applied to IAVF PMD, for detail please reference\n the section ``Protocol extraction for per queue`` of ice.rst.\n \n+ Quanta size configuration is also supported when IAVF is backed by an Intel® E810 device by setting ``devargs``\n+ parameter ``quanta_size`` like ``-a 18:00.0,quanta_size=2048``. The default value is 1024, and quanta size should be\n+ set as the product of 64 in legacy host interface mode.\n+\n The PCIE host-interface of Intel Ethernet Switch FM10000 Series VF infrastructure\n ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n \ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex ff379ace67..f1b4057d70 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -58,6 +58,7 @@ New Features\n * **Updated Intel iavf driver.**\n \n * Added Tx QoS queue rate limitation support.\n+ * Added quanta size configuration support.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h\nindex 96515a3ee9..c0a4a47b04 100644\n--- a/drivers/net/iavf/iavf.h\n+++ b/drivers/net/iavf/iavf.h\n@@ -292,6 +292,7 @@ enum iavf_proto_xtr_type {\n struct iavf_devargs {\n \tuint8_t proto_xtr_dflt;\n \tuint8_t proto_xtr[IAVF_MAX_QUEUE_NUM];\n+\tuint16_t quanta_size;\n };\n \n struct iavf_security_ctx;\n@@ -467,6 +468,8 @@ int iavf_set_q_bw(struct rte_eth_dev *dev,\n int iavf_set_q_tc_map(struct rte_eth_dev *dev,\n \t\t\tstruct virtchnl_queue_tc_mapping *q_tc_mapping,\n \t\t\tuint16_t size);\n+int iavf_set_vf_quanta_size(struct iavf_adapter *adapter, u16 start_queue_id,\n+\t\t\t u16 num_queues);\n void iavf_tm_conf_init(struct rte_eth_dev *dev);\n void iavf_tm_conf_uninit(struct rte_eth_dev *dev);\n int iavf_ipsec_crypto_request(struct iavf_adapter *adapter,\ndiff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c\nindex d6190ac24a..7d093bdc24 100644\n--- a/drivers/net/iavf/iavf_ethdev.c\n+++ b/drivers/net/iavf/iavf_ethdev.c\n@@ -34,9 +34,11 @@\n \n /* devargs */\n #define IAVF_PROTO_XTR_ARG \"proto_xtr\"\n+#define IAVF_QUANTA_SIZE_ARG \"quanta_size\"\n \n static const char * const iavf_valid_args[] = {\n \tIAVF_PROTO_XTR_ARG,\n+\tIAVF_QUANTA_SIZE_ARG,\n \tNULL\n };\n \n@@ -950,6 +952,9 @@ iavf_dev_start(struct rte_eth_dev *dev)\n \t\treturn -1;\n \t}\n \n+\tif (iavf_set_vf_quanta_size(adapter, index, num_queue_pairs) != 0)\n+\t\tPMD_DRV_LOG(WARNING, \"configure quanta size failed\");\n+\n \t/* If needed, send configure queues msg multiple times to make the\n \t * adminq buffer length smaller than the 4K limitation.\n \t */\n@@ -2092,6 +2097,25 @@ iavf_handle_proto_xtr_arg(__rte_unused const char *key, const char *value,\n \treturn 0;\n }\n \n+static int\n+parse_u16(__rte_unused const char *key, const char *value, void *args)\n+{\n+\tu16 *num = (u16 *)args;\n+\tu16 tmp;\n+\n+\terrno = 0;\n+\ttmp = strtoull(value, NULL, 10);\n+\tif (errno || !tmp) {\n+\t\tPMD_DRV_LOG(WARNING, \"%s: \\\"%s\\\" is not a valid u16\",\n+\t\t\t key, value);\n+\t\treturn -1;\n+\t}\n+\n+\t*num = tmp;\n+\n+\treturn 0;\n+}\n+\n static int iavf_parse_devargs(struct rte_eth_dev *dev)\n {\n \tstruct iavf_adapter *ad =\n@@ -2118,6 +2142,20 @@ static int iavf_parse_devargs(struct rte_eth_dev *dev)\n \tif (ret)\n \t\tgoto bail;\n \n+\tret = rte_kvargs_process(kvlist, IAVF_QUANTA_SIZE_ARG,\n+\t\t\t\t &parse_u16, &ad->devargs.quanta_size);\n+\tif (ret)\n+\t\tgoto bail;\n+\n+\tif (ad->devargs.quanta_size == 0)\n+\t\tad->devargs.quanta_size = 1024;\n+\n+\tif (ad->devargs.quanta_size < 256 || ad->devargs.quanta_size > 4096 ||\n+\t ad->devargs.quanta_size & 0x40) {\n+\t\tPMD_INIT_LOG(ERR, \"invalid quanta size\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n bail:\n \trte_kvargs_free(kvlist);\n \treturn ret;\ndiff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c\nindex 537369f736..f9452d14ae 100644\n--- a/drivers/net/iavf/iavf_vchnl.c\n+++ b/drivers/net/iavf/iavf_vchnl.c\n@@ -1828,3 +1828,34 @@ iavf_ipsec_crypto_request(struct iavf_adapter *adapter,\n \n \treturn 0;\n }\n+\n+int\n+iavf_set_vf_quanta_size(struct iavf_adapter *adapter, u16 start_queue_id, u16 num_queues)\n+{\n+\tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(adapter);\n+\tstruct iavf_cmd_info args;\n+\tstruct virtchnl_quanta_cfg q_quanta;\n+\tint err;\n+\n+\tif (adapter->devargs.quanta_size == 0)\n+\t\treturn 0;\n+\n+\tq_quanta.quanta_size = adapter->devargs.quanta_size;\n+\tq_quanta.queue_select.type = VIRTCHNL_QUEUE_TYPE_TX;\n+\tq_quanta.queue_select.start_queue_id = start_queue_id;\n+\tq_quanta.queue_select.num_queues = num_queues;\n+\n+\targs.ops = VIRTCHNL_OP_CONFIG_QUANTA;\n+\targs.in_args = (uint8_t *)&q_quanta;\n+\targs.in_args_size = sizeof(q_quanta);\n+\targs.out_buffer = vf->aq_resp;\n+\targs.out_size = IAVF_AQ_BUF_SZ;\n+\n+\terr = iavf_execute_vf_cmd(adapter, &args, 0);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command VIRTCHNL_OP_CONFIG_QUANTA\");\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v6", "3/3" ] }