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GET /api/patches/109655/?format=api
{ "id": 109655, "url": "https://patches.dpdk.org/api/patches/109655/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220413160932.2074781-22-kevinx.liu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220413160932.2074781-22-kevinx.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220413160932.2074781-22-kevinx.liu@intel.com", "date": "2022-04-13T16:09:20", "name": "[v2,21/33] net/ice: support IPv4 GRE raw pattern type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4570b793fee5b940506071fece069522fc3176d3", "submitter": { "id": 2440, "url": "https://patches.dpdk.org/api/people/2440/?format=api", "name": "Kevin Liu", "email": "kevinx.liu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220413160932.2074781-22-kevinx.liu@intel.com/mbox/", "series": [ { "id": 22497, "url": "https://patches.dpdk.org/api/series/22497/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22497", "date": "2022-04-13T16:08:59", "name": "support full function of DCF", "version": 2, "mbox": "https://patches.dpdk.org/series/22497/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/109655/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/109655/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D5709A0508;\n\tWed, 13 Apr 2022 10:13:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 13A6142812;\n\tWed, 13 Apr 2022 10:11:42 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 7404540694\n for <dev@dpdk.org>; Wed, 13 Apr 2022 10:11:39 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2022 01:11:39 -0700", "from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195])\n by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2022 01:11:36 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1649837499; x=1681373499;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Z0opagSknuRIvze615JycuONGeoeSUg9ZgewTpQEK+U=;\n b=SHR87mTvdTqjSZRYk7U6RkVSxPL/0lYtG+dAzJDmNwB+Iyo4RulzW0qL\n WagFP21caHmzxCNkED32Qz4oTZv6YfQ8nUI5/T7U5Y3Sh3HekBzYzrtw6\n XXD2v623zxnxzbg0oE/wlfSdnQHvtHrMHxYnTotJ6ARpXK2W73i3z8e68\n +0x5BhwkPwyPZcEgnh/Eonby8+wOGluXyg29QPHKjOJltVyitt/9cC4lU\n fm+MD6nvj6bD78auqWVawoikO1ANuqKKjuCmqh7L+kjj7wwnNFVEHF+zz\n NB57tqlxB1X656nX2GUQ7puZrvk/zdGWydwEiF+TOTNQwQwB/kw2txapk g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10315\"; a=\"287630070\"", "E=Sophos;i=\"5.90,256,1643702400\"; d=\"scan'208\";a=\"287630070\"", "E=Sophos;i=\"5.90,256,1643702400\"; d=\"scan'208\";a=\"526847805\"" ], "From": "Kevin Liu <kevinx.liu@intel.com>", "To": "dev@dpdk.org", "Cc": "qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com,\n Alvin Zhang <alvinx.zhang@intel.com>, Steven Zou <steven.zou@intel.com>,\n Kevin Liu <kevinx.liu@intel.com>", "Subject": "[PATCH v2 21/33] net/ice: support IPv4 GRE raw pattern type", "Date": "Wed, 13 Apr 2022 16:09:20 +0000", "Message-Id": "<20220413160932.2074781-22-kevinx.liu@intel.com>", "X-Mailer": "git-send-email 2.33.1", "In-Reply-To": "<20220413160932.2074781-1-kevinx.liu@intel.com>", "References": "<20220407105706.18889-1-kevinx.liu@intel.com>\n <20220413160932.2074781-1-kevinx.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alvin Zhang <alvinx.zhang@intel.com>\n\nAdd definitions, matching entries, parsers for below patterns:\nETH/IPV4/GRE/RAW/IPV4\nETH/IPV4/GRE/RAW/IPV4/UDP\nETH/IPV4/GRE/RAW/IPV4/TCP\n\nSigned-off-by: Steven Zou <steven.zou@intel.com>\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\nSigned-off-by: Kevin Liu <kevinx.liu@intel.com>\n---\n drivers/net/ice/ice_generic_flow.c | 27 +++++++++\n drivers/net/ice/ice_generic_flow.h | 9 +++\n drivers/net/ice/ice_switch_filter.c | 90 +++++++++++++++++++++++++++++\n 3 files changed, 126 insertions(+)", "diff": "diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c\nindex 1433094ed4..6663a85ed0 100644\n--- a/drivers/net/ice/ice_generic_flow.c\n+++ b/drivers/net/ice/ice_generic_flow.c\n@@ -1084,6 +1084,33 @@ enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_icmp6[] = {\n \tRTE_FLOW_ITEM_TYPE_ICMP6,\n \tRTE_FLOW_ITEM_TYPE_END,\n };\n+/* IPv4 GRE RAW IPv4 */\n+enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4[] = {\n+\tRTE_FLOW_ITEM_TYPE_ETH,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_GRE,\n+\tRTE_FLOW_ITEM_TYPE_RAW,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_END,\n+};\n+enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_udp[] = {\n+\tRTE_FLOW_ITEM_TYPE_ETH,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_GRE,\n+\tRTE_FLOW_ITEM_TYPE_RAW,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_UDP,\n+\tRTE_FLOW_ITEM_TYPE_END,\n+};\n+enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_tcp[] = {\n+\tRTE_FLOW_ITEM_TYPE_ETH,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_GRE,\n+\tRTE_FLOW_ITEM_TYPE_RAW,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_TCP,\n+\tRTE_FLOW_ITEM_TYPE_END,\n+};\n \n /*IPv4 GTPU (EH) */\n enum rte_flow_item_type pattern_eth_ipv4_gtpu[] = {\ndiff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h\nindex def7e2d6d6..12193cbd9d 100644\n--- a/drivers/net/ice/ice_generic_flow.h\n+++ b/drivers/net/ice/ice_generic_flow.h\n@@ -27,6 +27,7 @@\n #define ICE_PROT_L2TPV3OIP\t\tBIT_ULL(16)\n #define ICE_PROT_PFCP\t\t\tBIT_ULL(17)\n #define ICE_PROT_NAT_T_ESP\t\tBIT_ULL(18)\n+#define ICE_PROT_GRE BIT_ULL(19)\n \n /* field */\n \n@@ -54,6 +55,7 @@\n #define ICE_PFCP_SEID\t\t\tBIT_ULL(42)\n #define ICE_PFCP_S_FIELD\t\tBIT_ULL(41)\n #define ICE_IP_PK_ID\t\t BIT_ULL(40)\n+#define ICE_RAW_PATTERN\t\t\tBIT_ULL(39)\n \n /* input set */\n \n@@ -104,6 +106,8 @@\n \t(ICE_PROT_GTPU | ICE_GTPU_TEID)\n #define ICE_INSET_GTPU_QFI \\\n \t(ICE_PROT_GTPU | ICE_GTPU_QFI)\n+#define ICE_INSET_RAW \\\n+\t(ICE_PROT_GRE | ICE_RAW_PATTERN)\n #define ICE_INSET_PPPOE_SESSION \\\n \t(ICE_PROT_PPPOE_S | ICE_PPPOE_SESSION)\n #define ICE_INSET_PPPOE_PROTO \\\n@@ -291,6 +295,11 @@ extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_udp[];\n extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_sctp[];\n extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_icmp6[];\n \n+/* IPv4 GRE RAW IPv4 */\n+extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4[];\n+extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_udp[];\n+extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_tcp[];\n+\n /* IPv4 GTPU (EH) */\n extern enum rte_flow_item_type pattern_eth_ipv4_gtpu[];\n extern enum rte_flow_item_type pattern_eth_ipv4_gtpu_eh[];\ndiff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 44046f803c..435ca5a05c 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -196,6 +196,22 @@\n #define ICE_SW_INSET_GTPU_IPV6_TCP ( \\\n \tICE_SW_INSET_GTPU_IPV6 | ICE_INSET_TCP_SRC_PORT | \\\n \tICE_INSET_TCP_DST_PORT)\n+#define ICE_SW_INSET_DIST_GRE_RAW_IPV4 ( \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_RAW)\n+#define ICE_SW_INSET_DIST_GRE_RAW_IPV4_TCP ( \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \\\n+\tICE_INSET_RAW)\n+#define ICE_SW_INSET_DIST_GRE_RAW_IPV4_UDP ( \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \\\n+\tICE_INSET_RAW)\n+\n+#define CUSTOM_GRE_KEY_OFFSET\t4\n+#define GRE_CFLAG\t\t0x80\n+#define GRE_KFLAG\t\t0x20\n+#define GRE_SFLAG\t\t0x10\n \n struct sw_meta {\n \tstruct ice_adv_lkup_elem *list;\n@@ -317,6 +333,9 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {\n \t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n \t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n \t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gre_raw_ipv4,\t\t\tICE_SW_INSET_DIST_GRE_RAW_IPV4,\t\tICE_INSET_NONE,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gre_raw_ipv4_tcp,\t\tICE_SW_INSET_DIST_GRE_RAW_IPV4_TCP,\t\tICE_INSET_NONE,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gre_raw_ipv4_udp,\t\tICE_SW_INSET_DIST_GRE_RAW_IPV4_UDP,\t\tICE_INSET_NONE,\t\tICE_INSET_NONE},\n };\n \n static struct\n@@ -608,6 +627,11 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[],\n \tbool ipv6_ipv6_valid = 0;\n \tbool any_valid = 0;\n \tuint16_t j, k, t = 0;\n+\tuint16_t c_rsvd0_ver = 0;\n+\tbool gre_valid = 0;\n+\n+#define set_cur_item_einval(msg) \\\n+\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, (msg))\n \n \tif (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n \t *tun_type == ICE_NON_TUN_QINQ)\n@@ -1100,6 +1124,70 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[],\n \t\t\t}\n \t\t\tbreak;\n \n+\t\tcase RTE_FLOW_ITEM_TYPE_GRE: {\n+\t\t\tconst struct rte_flow_item_gre *gre_spec = item->spec;\n+\t\t\tconst struct rte_flow_item_gre *gre_mask = item->mask;\n+\n+\t\t\tgre_valid = 1;\n+\t\t\ttunnel_valid = 1;\n+\t\t\tif (gre_spec && gre_mask) {\n+\t\t\t\tlist[t].type = ICE_GRE;\n+\t\t\t\tif (gre_mask->c_rsvd0_ver) {\n+\t\t\t\t\t/* GRE RFC1701 */\n+\t\t\t\t\tlist[t].h_u.gre_hdr.flags =\n+\t\t\t\t\t\t\tgre_spec->c_rsvd0_ver;\n+\t\t\t\t\tlist[t].m_u.gre_hdr.flags =\n+\t\t\t\t\t\t\tgre_mask->c_rsvd0_ver;\n+\t\t\t\t\tc_rsvd0_ver = gre_spec->c_rsvd0_ver &\n+\t\t\t\t\t\t gre_mask->c_rsvd0_ver;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tcase RTE_FLOW_ITEM_TYPE_RAW: {\n+\t\t\tconst struct rte_flow_item_raw *raw_spec;\n+\t\t\tchar *endp = NULL;\n+\t\t\tunsigned long key;\n+\t\t\tchar s[sizeof(\"0x12345678\")];\n+\n+\t\t\traw_spec = item->spec;\n+\n+\t\t\tif (list[t].type != ICE_GRE)\n+\t\t\t\treturn set_cur_item_einval(\"RAW must follow GRE.\");\n+\n+\t\t\tif (!(c_rsvd0_ver & GRE_KFLAG)) {\n+\t\t\t\tif (!raw_spec)\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\treturn set_cur_item_einval(\"Invalid pattern! k_bit is 0 while raw pattern exists.\");\n+\t\t\t}\n+\n+\t\t\tif (!raw_spec)\n+\t\t\t\treturn set_cur_item_einval(\"Invalid pattern! k_bit is 1 while raw pattern doesn't exist.\");\n+\n+\t\t\tif ((c_rsvd0_ver & GRE_CFLAG) == GRE_CFLAG &&\n+\t\t\t raw_spec->offset != CUSTOM_GRE_KEY_OFFSET)\n+\t\t\t\treturn set_cur_item_einval(\"Invalid pattern! c_bit is 1 while offset is not 4.\");\n+\n+\t\t\tif (raw_spec->length >= sizeof(s))\n+\t\t\t\treturn set_cur_item_einval(\"Invalid key\");\n+\n+\t\t\tmemcpy(s, raw_spec->pattern, raw_spec->length);\n+\t\t\ts[raw_spec->length] = '\\0';\n+\t\t\tkey = strtol(s, &endp, 16);\n+\t\t\tif (*endp != '\\0' || key > UINT32_MAX)\n+\t\t\t\treturn set_cur_item_einval(\"Invalid key\");\n+\n+\t\t\tlist[t].h_u.gre_hdr.key = (uint32_t)key;\n+\t\t\tlist[t].m_u.gre_hdr.key = UINT32_MAX;\n+\t\t\t*input |= ICE_INSET_RAW;\n+\t\t\tinput_set_byte += 2;\n+\t\t\tt++;\n+\n+\t\t\tbreak;\n+\t\t}\n+\n \t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n \t\t\tvlan_spec = item->spec;\n \t\t\tvlan_mask = item->mask;\n@@ -1633,6 +1721,8 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[],\n \tif (*tun_type == ICE_NON_TUN) {\n \t\tif (nvgre_valid)\n \t\t\t*tun_type = ICE_SW_TUN_NVGRE;\n+\t\telse if (gre_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_GRE;\n \t\telse if (ipv4_valid && tcp_valid)\n \t\t\t*tun_type = ICE_SW_IPV4_TCP;\n \t\telse if (ipv4_valid && udp_valid)\n", "prefixes": [ "v2", "21/33" ] }