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GET /api/patches/10765/?format=api
{ "id": 10765, "url": "https://patches.dpdk.org/api/patches/10765/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1456165148-28416-5-git-send-email-adrien.mazarguil@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1456165148-28416-5-git-send-email-adrien.mazarguil@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1456165148-28416-5-git-send-email-adrien.mazarguil@6wind.com", "date": "2016-02-22T18:19:08", "name": "[dpdk-dev,4/4] mlx5: add VLAN insertion offload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b382934cefe4281d6594d4b2515b50363a3117c3", "submitter": { "id": 165, "url": "https://patches.dpdk.org/api/people/165/?format=api", "name": "Adrien Mazarguil", "email": "adrien.mazarguil@6wind.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1456165148-28416-5-git-send-email-adrien.mazarguil@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/10765/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/10765/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DEF085AB8;\n\tMon, 22 Feb 2016 19:19:37 +0100 (CET)", "from mail-wm0-f49.google.com (mail-wm0-f49.google.com\n\t[74.125.82.49]) by dpdk.org (Postfix) with ESMTP id C264B5AB8\n\tfor <dev@dpdk.org>; Mon, 22 Feb 2016 19:19:35 +0100 (CET)", "by mail-wm0-f49.google.com with SMTP id g62so186586768wme.1\n\tfor <dev@dpdk.org>; Mon, 22 Feb 2016 10:19:35 -0800 (PST)", "from 6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tl132sm22204465wmf.7.2016.02.22.10.19.34\n\t(version=TLSv1/SSLv3 cipher=OTHER);\n\tMon, 22 Feb 2016 10:19:35 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=AI/czVbm0WzRQsvbUTjinfO8kRuqEdVD5kU5Q+0c7TU=;\n\tb=UmKorsuReeQm+yKlPCCfoZbRVqPWKV1kDzy4Y9dhFqsu2vmycIIhnBUvZRyDHEGZp/\n\tpyITpfOAUI2C7/25SolMlsvwUB5jWmNfW1/XxYONaV0LTR3HbSSPBN2JExWi0akz53JL\n\to2HYxYbQStjbU0LehpRSgjrRSH9QUkqCVTnq6VdJtQ/Fw4+ONrKunXOn1McxAaFVN6fc\n\tvosPZlLmdtTYGDWAt5EtZjZ2VYKG6Bh1iMSHIpJV+8XSyPzsn4mOs+Wr3RvfZsrW1dYK\n\tddHHXVtFwA50bk6RzfEpVMoMyhBfne608DMZTPxG0zqZOGyTm5RjVKMRrfbitYoM5XVX\n\t+wiA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=AI/czVbm0WzRQsvbUTjinfO8kRuqEdVD5kU5Q+0c7TU=;\n\tb=gBvESZkT20SbnHZSLKCD5wHKSvmYek9kidKflBhAcy1myYwMWGqWbf4p/kQX5tkAD3\n\tTyaUl70n3Vw244kpwveYH02HwjofDXBKJsEfIpvEeesdkZ26Q/oOFCF1eRAeOC2LaCBm\n\tGZGk/0AaYtAh8x0ghm96h67qK+Tp4dbjmxDJxsJzKBNsyjGBS9QxfzHEKGyKfPh0JouM\n\tI9MuGA1cJZZ9PNpCj6RvNDd+nAtC/Hgay/wQ7EnVZoNop63pjp0nfHkOfMaNxOBo+OKb\n\tBSHdtCaFLiNjouFtJ03e0MBtmdOFGpbEqOLVkxPy/+tCDIFEseADTIW0zI377f+Gc5/t\n\t1AJA==", "X-Gm-Message-State": "AG10YORFBpQMwWK7IISncl6jyweUbcXDEXeXUL4rqN4ZVdWr3Zi6OGAGIMKSe/twIqwHQXcw", "X-Received": "by 10.194.186.170 with SMTP id\n\tfl10mr34189063wjc.29.1456165175674; \n\tMon, 22 Feb 2016 10:19:35 -0800 (PST)", "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "To": "dev@dpdk.org", "Date": "Mon, 22 Feb 2016 19:19:08 +0100", "Message-Id": "<1456165148-28416-5-git-send-email-adrien.mazarguil@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1456165148-28416-1-git-send-email-adrien.mazarguil@6wind.com>", "References": "<1456165148-28416-1-git-send-email-adrien.mazarguil@6wind.com>", "Subject": "[dpdk-dev] [PATCH 4/4] mlx5: add VLAN insertion offload", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Yaacov Hazan <yaacovh@mellanox.com>\n\nVLAN insertion is done in software by the PMD by default unless\nCONFIG_RTE_LIBRTE_MLX5_VERBS_VLAN_INSERTION is enabled and Verbs provides\nsupport for hardware insertion.\n\nWhen enabled, this option improves performance when VLAN insertion is\nrequested, however ConnectX-4 Lx boards cannot take advantage of\nmulti-packet send optimizations anymore.\n\nSigned-off-by: Yaacov Hazan <yaacovh@mellanox.com>\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n config/common_linuxapp | 1 +\n doc/guides/nics/mlx5.rst | 8 +++\n doc/guides/rel_notes/release_16_04.rst | 4 ++\n drivers/net/mlx5/Makefile | 9 +++\n drivers/net/mlx5/mlx5_defs.h | 9 +++\n drivers/net/mlx5/mlx5_ethdev.c | 12 ++--\n drivers/net/mlx5/mlx5_rxtx.c | 109 +++++++++++++++++++++++++++------\n drivers/net/mlx5/mlx5_rxtx.h | 13 ++++\n drivers/net/mlx5/mlx5_txq.c | 15 ++++-\n 9 files changed, 155 insertions(+), 25 deletions(-)", "diff": "diff --git a/config/common_linuxapp b/config/common_linuxapp\nindex 7b5e49f..793d262 100644\n--- a/config/common_linuxapp\n+++ b/config/common_linuxapp\n@@ -220,6 +220,7 @@ CONFIG_RTE_LIBRTE_MLX5_DEBUG=n\n CONFIG_RTE_LIBRTE_MLX5_SGE_WR_N=4\n CONFIG_RTE_LIBRTE_MLX5_MAX_INLINE=0\n CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE=8\n+CONFIG_RTE_LIBRTE_MLX5_VERBS_VLAN_INSERTION=n\n \n #\n # Compile burst-oriented Broadcom PMD driver\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 66fe0d9..1ca1534 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -84,6 +84,7 @@ Features\n - Support for multiple MAC addresses.\n - VLAN filtering.\n - RX VLAN stripping.\n+- TX VLAN insertion.\n - Promiscuous mode.\n - Multicast promiscuous mode.\n - Hardware checksum offloads.\n@@ -142,6 +143,13 @@ These options can be modified in the ``.config`` file.\n \n This value is always 1 for RX queues since they use a single MP.\n \n+- ``CONFIG_RTE_LIBRTE_MLX5_VERBS_VLAN_INSERTION`` (default **n**)\n+\n+ Use Verbs instead of PMD implementation for VLAN insertion. Disabled by\n+ default since it prevents ConnectX-4 Lx adapters from taking advantage of\n+ multi-packet send optimizations, otherwise provides better performance\n+ when VLAN insertion is requested.\n+\n Environment variables\n ~~~~~~~~~~~~~~~~~~~~~\n \ndiff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst\nindex a3a30fd..906d835 100644\n--- a/doc/guides/rel_notes/release_16_04.rst\n+++ b/doc/guides/rel_notes/release_16_04.rst\n@@ -92,6 +92,10 @@ This section should contain new features added in this release. Sample format:\n Added an option to make PCI bus transactions rounded to multiple of 64\n bytes for better cache alignment.\n \n+* **mlx5: TX VLAN insertion support.**\n+\n+ Added support for TX VLAN insertion.\n+\n \n Resolved Issues\n ---------------\ndiff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile\nindex 712c0a9..a260c52 100644\n--- a/drivers/net/mlx5/Makefile\n+++ b/drivers/net/mlx5/Makefile\n@@ -101,6 +101,10 @@ ifdef CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE\n CFLAGS += -DMLX5_PMD_TX_MP_CACHE=$(CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE)\n endif\n \n+ifeq ($(CONFIG_RTE_LIBRTE_MLX5_VERBS_VLAN_INSERTION),y)\n+CFLAGS += -DMLX5_VERBS_VLAN_INSERTION\n+endif\n+\n include $(RTE_SDK)/mk/rte.lib.mk\n \n # Generate and clean-up mlx5_autoconf.h.\n@@ -142,6 +146,11 @@ mlx5_autoconf.h: $(RTE_SDK)/scripts/auto-config-h.sh\n \t\tinfiniband/verbs.h \\\n \t\tenum IBV_EXP_CREATE_WQ_FLAG_RX_END_PADDING \\\n \t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_VERBS_VLAN_INSERTION \\\n+\t\tinfiniband/verbs.h \\\n+\t\tenum IBV_EXP_RECEIVE_WQ_CVLAN_INSERTION \\\n+\t\t$(AUTOCONF_OUTPUT)\n \n $(SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD):.c=.o): mlx5_autoconf.h\n \ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 5b00d8e..fb8db2e 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -95,4 +95,13 @@\n #define MLX5_FDIR_SUPPORT 1\n #endif\n \n+/*\n+ * Prevent compilation when HW VLAN insertion is requested by configuration\n+ * but not supported by Verbs.\n+ */\n+#if defined(MLX5_VERBS_VLAN_INSERTION) && !defined(HAVE_VERBS_VLAN_INSERTION)\n+#error CONFIG_RTE_LIBRTE_MLX5_VERBS_VLAN_INSERTION \\\n+\tenabled in configuration but not supported by libibverbs.\n+#endif\n+\n #endif /* RTE_PMD_MLX5_DEFS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 6b674a2..66115d2 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -544,12 +544,12 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n \t\t DEV_RX_OFFLOAD_TCP_CKSUM) :\n \t\t 0);\n-\tinfo->tx_offload_capa =\n-\t\t(priv->hw_csum ?\n-\t\t (DEV_TX_OFFLOAD_IPV4_CKSUM |\n-\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n-\t\t DEV_TX_OFFLOAD_TCP_CKSUM) :\n-\t\t 0);\n+\tinfo->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;\n+\tif (priv->hw_csum)\n+\t\tinfo->tx_offload_capa |=\n+\t\t\t(DEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM);\n \tif (priv_get_ifname(priv, &ifname) == 0)\n \t\tinfo->if_index = if_nametoindex(ifname);\n \t/* FIXME: RETA update/query API expects the callee to know the size of\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 4919189..9fc535e 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -333,6 +333,40 @@ txq_mp2mr_iter(const struct rte_mempool *mp, void *arg)\n \ttxq_mp2mr(txq, mp);\n }\n \n+#ifndef MLX5_VERBS_VLAN_INSERTION\n+\n+/**\n+ * Insert VLAN to specific packet, using the mbuf's headroom space.\n+ *\n+ * @param buf\n+ * Buffer to insert the vlan.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static inline int\n+insert_vlan_sw(struct rte_mbuf *buf)\n+{\n+\tuintptr_t addr;\n+\tuint32_t vlan;\n+\tuint16_t head_room_len = rte_pktmbuf_headroom(buf);\n+\n+\tif (head_room_len < 4)\n+\t\treturn EINVAL;\n+\n+\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n+\tvlan = htonl(0x81000000 | buf->vlan_tci);\n+\tmemmove((void *)(addr - 4), (void *)addr, 12);\n+\tmemcpy((void *)(addr + 8), &vlan, sizeof(vlan));\n+\n+\tSET_DATA_OFF(buf, head_room_len - 4);\n+\tDATA_LEN(buf) += 4;\n+\n+\treturn 0;\n+}\n+\n+#endif /* !MLX5_VERBS_VLAN_INSERTION */\n+\n #if MLX5_PMD_SGE_WR_N > 1\n \n /**\n@@ -554,6 +588,14 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\tif (RTE_ETH_IS_TUNNEL_PKT(buf->packet_type))\n \t\t\t\tsend_flags |= IBV_EXP_QP_BURST_TUNNEL;\n \t\t}\n+#ifndef MLX5_VERBS_VLAN_INSERTION\n+\t\tif (buf->ol_flags & PKT_TX_VLAN_PKT) {\n+\t\t\terr = insert_vlan_sw(buf);\n+\n+\t\t\tif (unlikely(err))\n+\t\t\t\tgoto stop;\n+\t\t}\n+#endif /* !MLX5_VERBS_VLAN_INSERTION */\n \t\tif (likely(segs == 1)) {\n \t\t\tuintptr_t addr;\n \t\t\tuint32_t length;\n@@ -577,13 +619,23 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t}\n \t\t\t/* Put packet into send queue. */\n #if MLX5_PMD_MAX_INLINE > 0\n-\t\t\tif (length <= txq->max_inline)\n-\t\t\t\terr = txq->send_pending_inline\n-\t\t\t\t\t(txq->qp,\n-\t\t\t\t\t (void *)addr,\n-\t\t\t\t\t length,\n-\t\t\t\t\t send_flags);\n-\t\t\telse\n+\t\t\tif (length <= txq->max_inline) {\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\t\t\t\tif (buf->ol_flags & PKT_TX_VLAN_PKT)\n+\t\t\t\t\terr = txq->send_pending_inline_vlan\n+\t\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t\t (void *)addr,\n+\t\t\t\t\t\t length,\n+\t\t\t\t\t\t send_flags,\n+\t\t\t\t\t\t &buf->vlan_tci);\n+\t\t\t\telse\n+#endif /* MLX5_VERBS_VLAN_INSERTION */\n+\t\t\t\t\terr = txq->send_pending_inline\n+\t\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t\t (void *)addr,\n+\t\t\t\t\t\t length,\n+\t\t\t\t\t\t send_flags);\n+\t\t\t} else\n #endif\n \t\t\t{\n \t\t\t\t/* Retrieve Memory Region key for this\n@@ -597,12 +649,23 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t\t\telt->buf = NULL;\n \t\t\t\t\tgoto stop;\n \t\t\t\t}\n-\t\t\t\terr = txq->send_pending\n-\t\t\t\t\t(txq->qp,\n-\t\t\t\t\t addr,\n-\t\t\t\t\t length,\n-\t\t\t\t\t lkey,\n-\t\t\t\t\t send_flags);\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\t\t\t\tif (buf->ol_flags & PKT_TX_VLAN_PKT)\n+\t\t\t\t\terr = txq->send_pending_vlan\n+\t\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t\t addr,\n+\t\t\t\t\t\t length,\n+\t\t\t\t\t\t lkey,\n+\t\t\t\t\t\t send_flags,\n+\t\t\t\t\t\t &buf->vlan_tci);\n+\t\t\t\telse\n+#endif /* MLX5_VERBS_VLAN_INSERTION */\n+\t\t\t\t\terr = txq->send_pending\n+\t\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t\t addr,\n+\t\t\t\t\t\t length,\n+\t\t\t\t\t\t lkey,\n+\t\t\t\t\t\t send_flags);\n \t\t\t}\n \t\t\tif (unlikely(err))\n \t\t\t\tgoto stop;\n@@ -619,11 +682,21 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\tif (ret.length == (unsigned int)-1)\n \t\t\t\tgoto stop;\n \t\t\t/* Put SG list into send queue. */\n-\t\t\terr = txq->send_pending_sg_list\n-\t\t\t\t(txq->qp,\n-\t\t\t\t sges,\n-\t\t\t\t ret.num,\n-\t\t\t\t send_flags);\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\t\t\tif (buf->ol_flags & PKT_TX_VLAN_PKT)\n+\t\t\t\terr = txq->send_pending_sg_list_vlan\n+\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t sges,\n+\t\t\t\t\t ret.num,\n+\t\t\t\t\t send_flags,\n+\t\t\t\t\t &buf->vlan_tci);\n+\t\t\telse\n+#endif /* MLX5_VERBS_VLAN_INSERTION */\n+\t\t\t\terr = txq->send_pending_sg_list\n+\t\t\t\t\t(txq->qp,\n+\t\t\t\t\t sges,\n+\t\t\t\t\t ret.num,\n+\t\t\t\t\t send_flags);\n \t\t\tif (unlikely(err))\n \t\t\t\tgoto stop;\n #ifdef MLX5_PMD_SOFT_COUNTERS\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 6a0087e..7306d18 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -254,11 +254,20 @@ struct txq {\n \tstruct priv *priv; /* Back pointer to private data. */\n \tint32_t (*poll_cnt)(struct ibv_cq *cq, uint32_t max);\n \tint (*send_pending)();\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\tint (*send_pending_vlan)();\n+#endif\n #if MLX5_PMD_MAX_INLINE > 0\n \tint (*send_pending_inline)();\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\tint (*send_pending_inline_vlan)();\n+#endif\n #endif\n #if MLX5_PMD_SGE_WR_N > 1\n \tint (*send_pending_sg_list)();\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\tint (*send_pending_sg_list_vlan)();\n+#endif\n #endif\n \tint (*send_flush)(struct ibv_qp *qp);\n \tstruct ibv_cq *cq; /* Completion Queue. */\n@@ -282,7 +291,11 @@ struct txq {\n \t/* Elements used only for init part are here. */\n \tlinear_t (*elts_linear)[]; /* Linearized buffers. */\n \tstruct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */\n+#ifdef HAVE_VERBS_VLAN_INSERTION\n+\tstruct ibv_exp_qp_burst_family_v1 *if_qp; /* QP burst interface. */\n+#else\n \tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n+#endif\n \tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n \tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n \tunsigned int socket; /* CPU socket ID for allocations. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 6700af4..c643cf4 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -400,7 +400,11 @@ txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,\n \t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n \t\t.intf = IBV_EXP_INTF_QP_BURST,\n \t\t.obj = tmpl.qp,\n-#ifdef HAVE_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR\n+#ifdef HAVE_VERBS_VLAN_INSERTION\n+\t\t.intf_version = 1,\n+#endif\n+#if defined(HAVE_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR) && \\\n+\t!defined(MLX5_VERBS_VLAN_INSERTION)\n \t\t/* Multi packet send WR can only be used outside of VF. */\n \t\t.family_flags =\n \t\t\t(!priv->vf ?\n@@ -422,11 +426,20 @@ txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,\n \ttxq->poll_cnt = txq->if_cq->poll_cnt;\n #if MLX5_PMD_MAX_INLINE > 0\n \ttxq->send_pending_inline = txq->if_qp->send_pending_inline;\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\ttxq->send_pending_inline_vlan = txq->if_qp->send_pending_inline_vlan;\n+#endif\n #endif\n #if MLX5_PMD_SGE_WR_N > 1\n \ttxq->send_pending_sg_list = txq->if_qp->send_pending_sg_list;\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\ttxq->send_pending_sg_list_vlan = txq->if_qp->send_pending_sg_list_vlan;\n+#endif\n #endif\n \ttxq->send_pending = txq->if_qp->send_pending;\n+#ifdef MLX5_VERBS_VLAN_INSERTION\n+\ttxq->send_pending_vlan = txq->if_qp->send_pending_vlan;\n+#endif\n \ttxq->send_flush = txq->if_qp->send_flush;\n \tDEBUG(\"%p: txq updated with %p\", (void *)txq, (void *)&tmpl);\n \t/* Pre-register known mempools. */\n", "prefixes": [ "dpdk-dev", "4/4" ] }