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GET /api/patches/104623/?format=api
{ "id": 104623, "url": "https://patches.dpdk.org/api/patches/104623/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211123183805.2905792-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211123183805.2905792-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211123183805.2905792-2-michaelba@nvidia.com", "date": "2021-11-23T18:38:03", "name": "[1/3] common/mlx5: add min WQE size for striding RQ", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a77e205fe0c8dee36909be7c7fa26bef59e98273", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211123183805.2905792-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 20719, "url": "https://patches.dpdk.org/api/series/20719/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20719", "date": "2021-11-23T18:38:02", "name": "fix MPRQ prepare", "version": 1, "mbox": "https://patches.dpdk.org/series/20719/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/104623/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/104623/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D1219A0C4C;\n\tTue, 23 Nov 2021 19:38:39 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 73403410E5;\n\tTue, 23 Nov 2021 19:38:34 +0100 (CET)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2045.outbound.protection.outlook.com [40.107.223.45])\n by mails.dpdk.org (Postfix) with ESMTP id B487240040;\n Tue, 23 Nov 2021 19:38:32 +0100 (CET)", "from DM5PR22CA0016.namprd22.prod.outlook.com (2603:10b6:3:101::26)\n by DM4PR12MB5325.namprd12.prod.outlook.com (2603:10b6:5:39e::20) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.13; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Michael Baum\n <michaelba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 1/3] common/mlx5: add min WQE size for striding RQ", "Date": "Tue, 23 Nov 2021 20:38:03 +0200", "Message-ID": "<20211123183805.2905792-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211123183805.2905792-1-michaelba@nvidia.com>", "References": "<20211123183805.2905792-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e30f956d-d5f9-4612-dcf1-08d9aeb071f9", "X-MS-TrafficTypeDiagnostic": "DM4PR12MB5325:", "X-Microsoft-Antispam-PRVS": "\n <DM4PR12MB53259FCC39F884C77D5F3370CC609@DM4PR12MB5325.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4714;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 3pQZpvgDcsawpl9o9wvBvctMbpbMtuaYIgRNXqniRpCd3fWzO6W54e81lJFQF4aZs8pXBnV/vudz0Jbqs4J533aHRpPxgp+xUVSBRD9gVdJzcS4nUuUlmr+QrMGsC9MrUPO7WZaVn1wZCyRF9EXkYBRwDUTkAWunvkw2k7u/NU5+jva5mbQ7HJTJ/UyXzkIJ7dzPjQj8bqYJKA/3cVQ/Pid43qcohU5xlnqqmqKJbPV0IWoZjgK5FUMVpuFIvkMPbYUDSZmA+aONMqb57rHgrQVfcT5NXuB1fogKTv31v2Z+YxcOr8ZWdZ5GqPr9hE36JDq1Dvcz56psazZI/hdLVxyyDaSQrFNyqWTz5IlciUVupDEiFgRWZZaKhiaInnEAAfupc3IcN6rDidWzlGA5jl5fXdZhQgH6hlapvmERzCWHWl7g1zrqmHRqXXuRNeEUSw4+chLtEFbuC4MT/IbA4InVvDVeaCrU2c1axjrpFlxluVLxnDnisN5mACIuwAcpEt82WhsRHsB1mBJDHAGELr1LnraKgcMdo5CuGQCaZSDdwbcvPs3SGvwPKfl0HGVLoHKIGxR0bMTdmYtbskJp+4r4M4nUV1ajuC64jZFaKxWDAgwOTjKq+676RFncgBxt1DFflScnXNXWKMEuluiM77i3JUoZFyHjsz7OGx7EKby8In2tJ4BVgrhRcQWnBvI1KFcNoVLukHplY2YwjxVASA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(508600001)(336012)(6916009)(70586007)(16526019)(36860700001)(70206006)(55016003)(5660300002)(356005)(6286002)(7696005)(2906002)(1076003)(47076005)(54906003)(186003)(8676002)(7636003)(26005)(426003)(6666004)(86362001)(450100002)(2616005)(316002)(36756003)(2876002)(83380400001)(8936002)(82310400004)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Nov 2021 18:38:29.8323 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e30f956d-d5f9-4612-dcf1-08d9aeb071f9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT048.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5325", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nSome devices have a WQE size limit for striding RQ. On some newer\ndevices, this limitation is smaller and information on its size is\nprovided by the firmware.\n\nThis patch adds the attribute query from firmware: the minimum required\nsize of WQE in a strided RQ in granularity of Bytes.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 16 ++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 11 +++++++++--\n 3 files changed, 26 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex e52b995ee3..a8efdbe1ae 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -823,6 +823,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n {\n \tuint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};\n+\tbool hca_cap_2_sup;\n \tuint64_t general_obj_types_supported = 0;\n \tvoid *hcattr;\n \tint rc, i;\n@@ -832,6 +833,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tMLX5_HCA_CAP_OPMOD_GET_CUR);\n \tif (!hcattr)\n \t\treturn rc;\n+\thca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);\n \tattr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);\n \tattr->flow_counter_bulk_alloc_bitmap =\n \t\t\tMLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);\n@@ -967,6 +969,20 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t\t general_obj_types) &\n \t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);\n \tattr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);\n+\tif (hca_cap_2_sup) {\n+\t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n+\t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |\n+\t\t\t\tMLX5_HCA_CAP_OPMOD_GET_CUR);\n+\t\tif (!hcattr) {\n+\t\t\tDRV_LOG(DEBUG,\n+\t\t\t\t\"Failed to query DevX HCA capabilities 2.\");\n+\t\t\treturn rc;\n+\t\t}\n+\t\tattr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,\n+\t\t\t\t\t\t log_min_stride_wqe_sz);\n+\t}\n+\tif (attr->log_min_stride_wqe_sz == 0)\n+\t\tattr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;\n \tif (attr->qos.sup) {\n \t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n \t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex d7f71646a3..37821b493e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -251,6 +251,7 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_mmo_decompress:5;\n \tuint32_t umr_modify_entity_size_disabled:1;\n \tuint32_t umr_indirect_mkey_disabled:1;\n+\tuint32_t log_min_stride_wqe_sz:5;\n \tuint16_t max_wqe_sz_sq;\n };\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 2ded67e85e..8a7cb0e673 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -264,6 +264,9 @@\n /* The maximum log value of segments per RQ WQE. */\n #define MLX5_MAX_LOG_RQ_SEGS 5u\n \n+/* Log 2 of the default size of a WQE for Multi-Packet RQ. */\n+#define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U\n+\n /* The alignment needed for WQ buffer. */\n #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()\n \n@@ -1342,7 +1345,9 @@ enum {\n #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1\n \n struct mlx5_ifc_cmd_hca_cap_bits {\n-\tu8 reserved_at_0[0x30];\n+\tu8 reserved_at_0[0x20];\n+\tu8 hca_cap_2[0x1];\n+\tu8 reserved_at_21[0xf];\n \tu8 vhca_id[0x10];\n \tu8 reserved_at_40[0x20];\n \tu8 reserved_at_60[0x3];\n@@ -1909,7 +1914,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 max_reformat_insert_offset[0x8];\n \tu8 max_reformat_remove_size[0x8];\n \tu8 max_reformat_remove_offset[0x8]; /* End of DW6. */\n-\tu8 aso_conntrack_reg_id[0x8];\n+\tu8 reserved_at_c0[0x3];\n+\tu8 log_min_stride_wqe_sz[0x5];\n \tu8 reserved_at_c8[0x3];\n \tu8 log_conn_track_granularity[0x5];\n \tu8 reserved_at_d0[0x3];\n@@ -1922,6 +1928,7 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n+\tstruct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;\n \tstruct mlx5_ifc_per_protocol_networking_offload_caps_bits\n \t per_protocol_networking_offload_caps;\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n", "prefixes": [ "1/3" ] }