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GET /api/patches/103601/?format=api
{ "id": 103601, "url": "https://patches.dpdk.org/api/patches/103601/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211103044003.4058866-2-junfeng.guo@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211103044003.4058866-2-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211103044003.4058866-2-junfeng.guo@intel.com", "date": "2021-11-03T04:40:00", "name": "[v10,1/4] net/ice/base: add method to disable FDIR SWAP option", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "03cce0009e1b2ee2d58f3f6087c59da73f0a63b0", "submitter": { "id": 1785, "url": "https://patches.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211103044003.4058866-2-junfeng.guo@intel.com/mbox/", "series": [ { "id": 20254, "url": "https://patches.dpdk.org/api/series/20254/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20254", "date": "2021-11-03T04:39:59", "name": "enable protocol agnostic flow offloading in FDIR", "version": 10, "mbox": "https://patches.dpdk.org/series/20254/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103601/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/103601/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 471D9A0C53;\n\tWed, 3 Nov 2021 05:41:20 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 367BF41130;\n\tWed, 3 Nov 2021 05:41:16 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 91E3141123\n for <dev@dpdk.org>; Wed, 3 Nov 2021 05:41:14 +0100 (CET)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Nov 2021 21:41:14 -0700", "from dpdk-junfengguo-v1.sh.intel.com ([10.67.119.216])\n by orsmga008.jf.intel.com with ESMTP; 02 Nov 2021 21:41:11 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10156\"; a=\"211483815\"", "E=Sophos;i=\"5.87,204,1631602800\"; d=\"scan'208\";a=\"211483815\"", "E=Sophos;i=\"5.87,204,1631602800\"; d=\"scan'208\";a=\"500890000\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com,\n\tjingjing.wu@intel.com,\n\tbeilei.xing@intel.com", "Cc": "dev@dpdk.org, ferruh.yigit@intel.com, ting.xu@intel.com,\n junfeng.guo@intel.com", "Date": "Wed, 3 Nov 2021 12:40:00 +0800", "Message-Id": "<20211103044003.4058866-2-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211103044003.4058866-1-junfeng.guo@intel.com>", "References": "<20211102053918.4063391-5-junfeng.guo@intel.com>\n <20211103044003.4058866-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v10 1/4] net/ice/base: add method to disable FDIR\n SWAP option", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In this patch, we introduced a new parameter to enable/disable the\nFDIR SWAP option by setting the swap and inset register set with\ncertain values.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nAcked-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 44 ++++++++++++++++++++++++++--\n drivers/net/ice/base/ice_flex_pipe.h | 3 +-\n drivers/net/ice/base/ice_flow.c | 2 +-\n 3 files changed, 45 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex f35d59f4f5..06a233990f 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -4952,6 +4952,43 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype,\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_disable_fd_swap - set register appropriately to disable FD swap\n+ * @hw: pointer to the HW struct\n+ * @prof_id: profile ID\n+ */\n+void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id)\n+{\n+\tu8 swap_val = ICE_SWAP_VALID;\n+\tu8 i;\n+\t/* Since the SWAP Flag in the Programming Desc doesn't work,\n+\t * here add method to disable the SWAP Option via setting\n+\t * certain SWAP and INSET register set.\n+\t */\n+\tfor (i = 0; i < hw->blk[ICE_BLK_FD].es.fvw / 4; i++) {\n+\t\tu32 raw_swap = 0;\n+\t\tu32 raw_in = 0;\n+\t\tu8 j;\n+\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\traw_swap |= (swap_val++) << (j * BITS_PER_BYTE);\n+\t\t\traw_in |= ICE_INSET_DFLT << (j * BITS_PER_BYTE);\n+\t\t}\n+\n+\t\t/* write the FDIR swap register set */\n+\t\twr32(hw, GLQF_FDSWAP(prof_id, i), raw_swap);\n+\n+\t\tice_debug(hw, ICE_DBG_INIT, \"swap wr(%d, %d): %x = %08x\\n\",\n+\t\t\t\tprof_id, i, GLQF_FDSWAP(prof_id, i), raw_swap);\n+\n+\t\t/* write the FDIR inset register set */\n+\t\twr32(hw, GLQF_FDINSET(prof_id, i), raw_in);\n+\n+\t\tice_debug(hw, ICE_DBG_INIT, \"inset wr(%d, %d): %x = %08x\\n\",\n+\t\t\t\tprof_id, i, GLQF_FDINSET(prof_id, i), raw_in);\n+\t}\n+}\n+\n /**\n * ice_add_prof - add profile\n * @hw: pointer to the HW struct\n@@ -4962,6 +4999,7 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype,\n * @attr_cnt: number of elements in attrib array\n * @es: extraction sequence (length of array is determined by the block)\n * @masks: mask for extraction sequence\n+ * @fd_swap: enable/disable FDIR paired src/dst fields swap option\n *\n * This function registers a profile, which matches a set of PTYPES with a\n * particular extraction sequence. While the hardware profile is allocated\n@@ -4971,7 +5009,7 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype,\n enum ice_status\n ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t const struct ice_ptype_attributes *attr, u16 attr_cnt,\n-\t struct ice_fv_word *es, u16 *masks)\n+\t struct ice_fv_word *es, u16 *masks, bool fd_swap)\n {\n \tu32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);\n \tice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);\n@@ -4991,7 +5029,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\tstatus = ice_alloc_prof_id(hw, blk, &prof_id);\n \t\tif (status)\n \t\t\tgoto err_ice_add_prof;\n-\t\tif (blk == ICE_BLK_FD) {\n+\t\tif (blk == ICE_BLK_FD && fd_swap) {\n \t\t\t/* For Flow Director block, the extraction sequence may\n \t\t\t * need to be altered in the case where there are paired\n \t\t\t * fields that have no match. This is necessary because\n@@ -5002,6 +5040,8 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\t\tstatus = ice_update_fd_swap(hw, prof_id, es);\n \t\t\tif (status)\n \t\t\t\tgoto err_ice_add_prof;\n+\t\t} else if (blk == ICE_BLK_FD) {\n+\t\t\tice_disable_fd_swap(hw, prof_id);\n \t\t}\n \t\tstatus = ice_update_prof_masking(hw, blk, prof_id, masks);\n \t\tif (status)\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex 9733c4b214..dd332312dd 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -61,10 +61,11 @@ bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype);\n /* XLT2/VSI group functions */\n enum ice_status\n ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);\n+void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id);\n enum ice_status\n ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t const struct ice_ptype_attributes *attr, u16 attr_cnt,\n-\t struct ice_fv_word *es, u16 *masks);\n+\t struct ice_fv_word *es, u16 *masks, bool fd_swap);\n void ice_init_all_prof_masks(struct ice_hw *hw);\n void ice_shutdown_all_prof_masks(struct ice_hw *hw);\n struct ice_prof_map *\ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 96d54b494d..77b6b130c1 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -2244,7 +2244,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,\n \t/* Add a HW profile for this flow profile */\n \tstatus = ice_add_prof(hw, blk, prof_id, (u8 *)params->ptypes,\n \t\t\t params->attr, params->attr_cnt, params->es,\n-\t\t\t params->mask);\n+\t\t\t params->mask, true);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_FLOW, \"Error adding a HW flow profile\\n\");\n \t\tgoto out;\n", "prefixes": [ "v10", "1/4" ] }