Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/103314/?format=api
{ "id": 103314, "url": "https://patches.dpdk.org/api/patches/103314/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211101085143.2472241-6-g.singh@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211101085143.2472241-6-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211101085143.2472241-6-g.singh@nxp.com", "date": "2021-11-01T08:51:42", "name": "[v2,5/6] dma/dpaa: support DMA operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7c77ca69853e6820fccf2c767bb8067acdb798d2", "submitter": { "id": 1068, "url": "https://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211101085143.2472241-6-g.singh@nxp.com/mbox/", "series": [ { "id": 20166, "url": "https://patches.dpdk.org/api/series/20166/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20166", "date": "2021-11-01T08:51:37", "name": "Introduce DPAA DMA driver", "version": 2, "mbox": "https://patches.dpdk.org/series/20166/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103314/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/103314/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 30E1BA0C57;\n\tMon, 1 Nov 2021 09:52:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EC15C41103;\n\tMon, 1 Nov 2021 09:52:19 +0100 (CET)", "from EUR02-VE1-obe.outbound.protection.outlook.com\n (mail-eopbgr20050.outbound.protection.outlook.com [40.107.2.50])\n by mails.dpdk.org (Postfix) with ESMTP id 64845410FD\n for <dev@dpdk.org>; Mon, 1 Nov 2021 09:52:18 +0100 (CET)", "from VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10)\n by VI1PR04MB5086.eurprd04.prod.outlook.com (2603:10a6:803:62::31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Mon, 1 Nov\n 2021 08:52:17 +0000", "from VI1PR04MB6960.eurprd04.prod.outlook.com\n ([fe80::11d9:6f32:90e:80c1]) by VI1PR04MB6960.eurprd04.prod.outlook.com\n ([fe80::11d9:6f32:90e:80c1%7]) with mapi id 15.20.4649.019; Mon, 1 Nov 2021\n 08:52:17 +0000", "from lsv03457.swis.in-blr01.nxp.com (14.142.151.118) by\n SG2PR02CA0092.apcprd02.prod.outlook.com (2603:1096:4:90::32) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4649.15 via Frontend Transport; Mon, 1 Nov 2021 08:52:15 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=SXIEfy9DVlX1IqSWEX68wilDOHAEff+vpnTVfHYvS9Y+/kNIVQiD0CKbuN+ZZ1vEV0AhEoTr9jioxIJR3G/nHa+OuJXVKKqaQKOPCIoE/FzpkZ5pihwAfliG1daZPFsg6BnJ9QW5xAiC/bZkuUbi2B8MO2NxLBmAgKwUvZRI55z2lylj1A+Ze9J1EUvSM+k/6SW4+/ids8RfUwFcUbuzr9wxzoE2D/EDmrEI7vh2VkZHzKCEBSKnvLjucrozQQp5vyxtt4KHF6AR0CItxjGR0/0IVx8SDEXUd6MbqgvxR4g69nUlPNJUStaJ2ps3KqgXunwiqpqBz34VztINaokLrA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Yzlxrgqh3TPALwq5k296KcHjF4i2nefv9nc6rSBNCW8=;\n b=NNjHv7NabZVdgretxEFFtgcBxIxPspmhFFLwD3B2cmqi+cvfUswEpa4vvHYkRbcf07QlIt+xtrhw/t52AC3ICRPM94RKmi+184vCBy1h32XhESl8s0XJkEWRgxAEb6D9V2Pzc46yUyXdE92J+/J+3KV7AqP/LamnNHvrPMPG+c1XHSH9Pz/ePWJUO3nE3Tn9CpnUNEMdeqznLBoDZWyjDjznvCPlHbXuv/SXsas3dNrKbwk2hvGSsYEtGmQo7vEbFbEuxZYu9ZfHRvDKspFCgHSuCsuZV6J6R3f8L6yWMXRAzgPh2YqeQZDCFUKJW6YgpIdwMGQH089WkbgVyhpA7g==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Yzlxrgqh3TPALwq5k296KcHjF4i2nefv9nc6rSBNCW8=;\n b=r2aIKRWydXVrcqPUeXf9oPM7UmdSnwgEYTXbMEJotlcoZVALLvuNauSsrgvvrEfhrsYy8OHTv/hUk2PBL7Ws9gQF0RBaujaJGjC+QR6j9/vXYiutHTmvtDuzm0SiTVRGgx6i3ODyzwnA8sZb3U52OpSzNtpdMleVhKAWvx+FSZI=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "thomas@monjalon.net,\n\tdev@dpdk.org", "Cc": "nipun.gupta@nxp.com,\n\tGagandeep Singh <g.singh@nxp.com>", "Date": "Mon, 1 Nov 2021 14:21:42 +0530", "Message-Id": "<20211101085143.2472241-6-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211101085143.2472241-1-g.singh@nxp.com>", "References": "<20210909111500.3901706-1-g.singh@nxp.com>\n <20211101085143.2472241-1-g.singh@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR02CA0092.apcprd02.prod.outlook.com\n (2603:1096:4:90::32) To VI1PR04MB6960.eurprd04.prod.outlook.com\n (2603:10a6:803:12d::10)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e634c3f3-0163-4035-abf1-08d99d14e815", "X-MS-TrafficTypeDiagnostic": "VI1PR04MB5086:", "X-Microsoft-Antispam-PRVS": "\n <VI1PR04MB50860946984C04D6DD6FB448E18A9@VI1PR04MB5086.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 388c6DFgSDuB1bH7QquwmaFW/YNruY3rBI/faByjrTXtLwPUrYNRDEgwIIAKCsC1UjN/74OILrWgejEzzJcn/b16btIRpHRlgBBQCC6X6MU7JEvZFaJHGzelPPkX9gCDiKcCF2Gke2Zp29mR3ggc3J+U9gIAarbj0nW09pQa5LJ1pQ+9hvuDPrpYD4rHaxD/+dXuRXSePDBPpU12TqqZlyk17wt+Hke9vp4vlJ1AKnNVnYzxMg7U4/AHdVXcmkl6yP7mXE0bqeEWBEJrnfxr5/Zwfc1qvR+zxb0f4tZ+2TY90qbNREO2y3fe7KNHnsxidpyTFgZqkIxzRibhR7OA8dakcix4V3Cos/IdrEQVFog2Y+rInFMWvr/OtUQBL0cMnQsuZhmgf5W6KYj5d2kVQLZ78SMIzw+eutCqB25/uuSQFC/dTCbCZM6y360g4UvqobPyDo5+5LHyFo0SWii77qn17bPlwm5GNEfM7OgCHfB68oed1lJn43lUXDLORoZpPxZaGQCGxS12I2JFOPjghQISNbIiro8Aeh/nmxfbUAGHy7PV12LyO3yV4ybQM6EeE/lKGmmVKlNL2RZnXCpifemetDgornmm6lD0TKiQVxz8C/7zDGpSJO4q5reQp9oRxQa028qZLYiH0/RzHjkNbr5NC7sVbdQDMpo8B3wNkJRb8fF8y3sbbAx7OLQVekpoPc4zL321jXQ309fFx8PmgqhI5ppg87NA2ZNp09qzBss=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:VI1PR04MB6960.eurprd04.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(4636009)(366004)(38350700002)(38100700002)(55236004)(6486002)(6666004)(186003)(1006002)(30864003)(4326008)(5660300002)(316002)(956004)(2616005)(86362001)(66556008)(7696005)(66476007)(26005)(36756003)(52116002)(8936002)(2906002)(66946007)(8676002)(83380400001)(508600001)(1076003)(110426009);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n +y2+6F9IRZS0UJ2N40QIOutybejvXWOfnAy8rv3Fl6JlgYgvzhnkhBIyFMrc4zu5DIgBwcyumg5GHNxq0oaoIwbd4k06JYUL7O61kNNCzp6htvX2uNS8N/U2zIRURVeOFDE7hUindM3Xak/MpJoOjrjAtH40X4Oaop2K2oQzEgbXemD04h+R8RZuiG3+5fuIy/NrCufLEHIBX1tc13TM6arw559HsPAoHZ6NVerJ9lxFouDT8dpda3votqRi+cIrXn9jenjTHa58xGevT7e1w2GuoMeh7Derw6E/OafEaDx/AuZN4P8ag8MoDKRAlNT8GlbOhrlbEtlKdmNXu1zvZe5ZbaDwZ0i1Hhrdh/kCH1pjF2Wn1vFzJPjfa1YyrtCf35+rA4zOvTwqu6DdJrdBBx6HwyeIaSma8EXvvjrT76korS5NmcQJ5oEQImMesg7ordUZ9lWyja9LbFWaV2SHEjJgdaduqq59OhU5knjEyHUe7RVPYFsm0XLXp6o0VWJcFYwk8JovV8Ogkoq2lcr7itA2My42QPQyrSAv/Fc76wVVL1jX7DP+aSNL5D+I9yrAHzAV4MbBeR4fXiqxEKplHUrdJvTF2qYwPUaF32/vF7FAGQM0y8q5HrVYTHpXiYXoDCD2efHI4ABoqxSlGcom1hyLPd3oTAnSfWVxdZyWR3fY+lder41lMyt5Nhyus/doXDQ1K3ktWKSGg1ifO4Pe0hfC1dKM5sbFnKp5AbJNlmbkRsDOaftKnX8G+mA4m4iHKxtwgCexazU6WRS3sJnb3b/SEsSmNrd7tIl8xVpFvY1d/rAyYQpMXVpNUjbDJkyhhJZNZn28N8DStagNVy7apM1nPx/Czwv/b1spt9kYH738LZCcsr4NAah0R98dr6Dy4tZCZjHL6hs65m2pCvQKlMMevFYmXeZo577dgM9GKbaY+dEtBi+Y0wYNXEALcTfyGrhSI+bp6TLFAM/8mgHIz5LEwoFZ+5Fj5lzNEXGdqN2DgGf+mi5cuBoKaRezn1QJNH3pcndX2bP1PoAtoNGlDUUfOZuEtgpRsxLFtNfn3CCwWX6HTKObgWJ0D7OqS0xlTXbkiXpEHuHVGv6BwoNHqckQvB2q88j4h9Wvsn6WRbF7BA9WV0ifsBPr/TOZefqCsC49yppou0HaiR7EWzKWqR7jGqvHk5GPNESjk/kySVp7/a37IY6AQ5hLkr55BlOp6lb/H6cvi/+586F6cZvp+vPtTlgut3I0uI2hebNRe0jsRyxNXLvz+mXAkdeFDCsUQ4v3AmSuGQQ/Cvd4AJcsyVe6jHF6wXY7U/a0b1QgZXkq3QSSjBJ0Jq18KnsC8z35QhZ7PVXpAanzBejzhyw0wSqXm4w0KgcNr/nwtuRBtrdKhunUYcC7FDRHrHrgbrokotU4W6I9hyR7RegDd8tO4rNw9AM7iC2LmTfuUQYAAxgoUT0oxd7nm1l6Stx/KtvTRFNyoE05MQG5jY70b6OG6hGVQTZxbsCF4MtZetsrJMEGJG7uGQdMMUwHvFGo58WDJ6K4zRKOF8RUMHIrLufpg9uoEL9YbezRTTwXThw4ZVs=", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e634c3f3-0163-4035-abf1-08d99d14e815", "X-MS-Exchange-CrossTenant-AuthSource": "VI1PR04MB6960.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Nov 2021 08:52:17.3036 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n zmvuYZUHsLlb99aIy56DhxFomxdrPYkAYTxVhMX4JYqx5sqfywDq2IzlzC1Cy6vS", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR04MB5086", "Subject": "[dpdk-dev] [PATCH v2 5/6] dma/dpaa: support DMA operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch support copy, submit, completed and\ncompleted status functionality of DMA driver.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/dma/dpaa/dpaa_qdma.c | 344 +++++++++++++++++++++++++++++++++++\n drivers/dma/dpaa/dpaa_qdma.h | 4 +\n 2 files changed, 348 insertions(+)", "diff": "diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c\nindex 0240f40907..a5973c22ae 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.c\n+++ b/drivers/dma/dpaa/dpaa_qdma.c\n@@ -15,11 +15,48 @@ qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)\n \tccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr));\n }\n \n+static inline u64\n+qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn ccdf->cfg8b_w1 & 0xff;\n+}\n+\n+static inline int\n+qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn (rte_le_to_cpu_32(ccdf->cfg) & QDMA_CCDF_MASK)\n+\t\t>> QDMA_CCDF_OFFSET;\n+}\n+\n+static inline void\n+qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)\n+{\n+\tccdf->cfg = rte_cpu_to_le_32(QDMA_CCDF_FOTMAT | offset);\n+}\n+\n+static inline int\n+qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)\n+{\n+\treturn (rte_le_to_cpu_32(ccdf->status) & QDMA_CCDF_MASK)\n+\t\t>> QDMA_CCDF_STATUS;\n+}\n+\n+static inline void\n+qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)\n+{\n+\tccdf->status = rte_cpu_to_le_32(QDMA_CCDF_SER | status);\n+}\n+\n static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)\n {\n \tcsgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK);\n }\n \n+static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)\n+{\n+\tcsgf->cfg = rte_cpu_to_le_32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));\n+}\n+\n static inline int ilog2(int x)\n {\n \tint log = 0;\n@@ -43,6 +80,16 @@ static void qdma_writel(u32 val, void *addr)\n \tQDMA_OUT(addr, val);\n }\n \n+static u32 qdma_readl_be(void *addr)\n+{\n+\treturn QDMA_IN_BE(addr);\n+}\n+\n+static void qdma_writel_be(u32 val, void *addr)\n+{\n+\tQDMA_OUT_BE(addr, val);\n+}\n+\n static void *dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr)\n {\n \tvoid *virt_addr;\n@@ -97,6 +144,31 @@ static void fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan)\n \tfsl_qdma->desc_allocated--;\n }\n \n+static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,\n+\t\t\t\t dma_addr_t dst, dma_addr_t src, u32 len)\n+{\n+\tstruct fsl_qdma_format *csgf_src, *csgf_dest;\n+\n+\t/* Note: command table (fsl_comp->virt_addr) is getting filled\n+\t * directly in cmd descriptors of queues while enqueuing the descriptor\n+\t * please refer fsl_qdma_enqueue_desc\n+\t * frame list table (virt_addr) + 1) and source,\n+\t * destination descriptor table\n+\t * (fsl_comp->desc_virt_addr and fsl_comp->desc_virt_addr+1) move to\n+\t * the control path to fsl_qdma_pre_request_enqueue_comp_sd_desc\n+\t */\n+\tcsgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2;\n+\tcsgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3;\n+\n+\t/* Status notification is enqueued to status queue. */\n+\tqdma_desc_addr_set64(csgf_src, src);\n+\tqdma_csgf_set_len(csgf_src, len);\n+\tqdma_desc_addr_set64(csgf_dest, dst);\n+\tqdma_csgf_set_len(csgf_dest, len);\n+\t/* This entry is the last entry. */\n+\tqdma_csgf_set_f(csgf_dest, len);\n+}\n+\n /*\n * Pre-request command descriptor and compound S/G for enqueue.\n */\n@@ -153,6 +225,25 @@ static int fsl_qdma_pre_request_enqueue_comp_sd_desc(\n \treturn 0;\n }\n \n+/*\n+ * Request a command descriptor for enqueue.\n+ */\n+static struct fsl_qdma_comp *\n+fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)\n+{\n+\tstruct fsl_qdma_queue *queue = fsl_chan->queue;\n+\tstruct fsl_qdma_comp *comp_temp;\n+\n+\tif (!list_empty(&queue->comp_free)) {\n+\t\tcomp_temp = list_first_entry(&queue->comp_free,\n+\t\t\t\t\t struct fsl_qdma_comp,\n+\t\t\t\t\t list);\n+\t\tlist_del(&comp_temp->list);\n+\t\treturn comp_temp;\n+\t}\n+\n+\treturn NULL;\n+}\n \n static struct fsl_qdma_queue\n *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma)\n@@ -287,6 +378,54 @@ static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)\n \treturn 0;\n }\n \n+static int\n+fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,\n+\t\t\t\t void *block, int id, const uint16_t nb_cpls,\n+\t\t\t\t uint16_t *last_idx,\n+\t\t\t\t enum rte_dma_status_code *status)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;\n+\tstruct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];\n+\tstruct fsl_qdma_queue *temp_queue;\n+\tstruct fsl_qdma_format *status_addr;\n+\tstruct fsl_qdma_comp *fsl_comp = NULL;\n+\tu32 reg, i;\n+\tint count = 0;\n+\n+\twhile (count < nb_cpls) {\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BSQSR);\n+\t\tif (reg & FSL_QDMA_BSQSR_QE_BE)\n+\t\t\treturn count;\n+\n+\t\tstatus_addr = fsl_status->virt_head;\n+\n+\t\ti = qdma_ccdf_get_queue(status_addr) +\n+\t\t\tid * fsl_qdma->n_queues;\n+\t\ttemp_queue = fsl_queue + i;\n+\t\tfsl_comp = list_first_entry(&temp_queue->comp_used,\n+\t\t\t\t\t struct fsl_qdma_comp,\n+\t\t\t\t\t list);\n+\t\tlist_del(&fsl_comp->list);\n+\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BSQMR);\n+\t\treg |= FSL_QDMA_BSQMR_DI_BE;\n+\n+\t\tqdma_desc_addr_set64(status_addr, 0x0);\n+\t\tfsl_status->virt_head++;\n+\t\tif (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)\n+\t\t\tfsl_status->virt_head = fsl_status->cq;\n+\t\tqdma_writel_be(reg, block + FSL_QDMA_BSQMR);\n+\t\t*last_idx = fsl_comp->index;\n+\t\tif (status != NULL)\n+\t\t\tstatus[count] = RTE_DMA_STATUS_SUCCESSFUL;\n+\n+\t\tlist_add_tail(&fsl_comp->list, &temp_queue->comp_free);\n+\t\tcount++;\n+\n+\t}\n+\treturn count;\n+}\n+\n static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n {\n \tstruct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;\n@@ -381,6 +520,65 @@ static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n \treturn 0;\n }\n \n+static void *\n+fsl_qdma_prep_memcpy(void *fsl_chan, dma_addr_t dst,\n+\t\t\t dma_addr_t src, size_t len,\n+\t\t\t void *call_back,\n+\t\t\t void *param)\n+{\n+\tstruct fsl_qdma_comp *fsl_comp;\n+\n+\tfsl_comp =\n+\tfsl_qdma_request_enqueue_desc((struct fsl_qdma_chan *)fsl_chan);\n+\tif (!fsl_comp)\n+\t\treturn NULL;\n+\n+\tfsl_comp->qchan = fsl_chan;\n+\tfsl_comp->call_back_func = call_back;\n+\tfsl_comp->params = param;\n+\n+\tfsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);\n+\treturn (void *)fsl_comp;\n+}\n+\n+static int fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan,\n+\t\t\t\t struct fsl_qdma_comp *fsl_comp,\n+\t\t\t\t uint64_t flags)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tvoid *block = fsl_queue->block_base;\n+\tstruct fsl_qdma_format *ccdf;\n+\tu32 reg;\n+\n+\t/* retrieve and store the register value in big endian\n+\t * to avoid bits swap\n+\t */\n+\treg = qdma_readl_be(block +\n+\t\t\t FSL_QDMA_BCQSR(fsl_queue->id));\n+\tif (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE))\n+\t\treturn -1;\n+\n+\t/* filling descriptor command table */\n+\tccdf = (struct fsl_qdma_format *)fsl_queue->virt_head;\n+\tqdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);\n+\tqdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr));\n+\tqdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr));\n+\tfsl_comp->index = fsl_queue->virt_head - fsl_queue->cq;\n+\tfsl_queue->virt_head++;\n+\n+\tif (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)\n+\t\tfsl_queue->virt_head = fsl_queue->cq;\n+\n+\tlist_add_tail(&fsl_comp->list, &fsl_queue->comp_used);\n+\n+\tif (flags == RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\treg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t\treg |= FSL_QDMA_BCQMR_EI_BE;\n+\t\tqdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\t}\n+\treturn fsl_comp->index;\n+}\n+\n static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan)\n {\n \tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n@@ -492,6 +690,148 @@ dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev,\n \treturn dpaa_get_channel(fsl_qdma, vchan);\n }\n \n+static int\n+dpaa_qdma_submit(void *dev_private, uint16_t vchan)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tstruct fsl_qdma_chan *fsl_chan =\n+\t\t&fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tvoid *block = fsl_queue->block_base;\n+\tu32 reg;\n+\n+\treg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\treg |= FSL_QDMA_BCQMR_EI_BE;\n+\tqdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));\n+\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_qdma_enqueue(void *dev_private, uint16_t vchan,\n+\t\t rte_iova_t src, rte_iova_t dst,\n+\t\t uint32_t length, uint64_t flags)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tstruct fsl_qdma_chan *fsl_chan =\n+\t\t&fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];\n+\tint ret;\n+\n+\tvoid *fsl_comp = NULL;\n+\n+\tfsl_comp = fsl_qdma_prep_memcpy(fsl_chan,\n+\t\t\t(dma_addr_t)dst, (dma_addr_t)src,\n+\t\t\tlength, NULL, NULL);\n+\tif (!fsl_comp) {\n+\t\tDPAA_QDMA_DP_DEBUG(\"fsl_comp is NULL\\n\");\n+\t\treturn -1;\n+\t}\n+\tret = fsl_qdma_enqueue_desc(fsl_chan, fsl_comp, flags);\n+\n+\treturn ret;\n+}\n+\n+static uint16_t\n+dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan,\n+\t\t\t const uint16_t nb_cpls, uint16_t *last_idx,\n+\t\t\t enum rte_dma_status_code *st)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tint id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);\n+\tvoid *block;\n+\tunsigned int reg;\n+\tint intr;\n+\tvoid *status = fsl_qdma->status_base;\n+\n+\tintr = qdma_readl_be(status + FSL_QDMA_DEDR);\n+\tif (intr) {\n+\t\tDPAA_QDMA_ERR(\"DMA transaction error! %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW0R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW0R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW1R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW1R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW2R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW2R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW3R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW3R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFQIDR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFQIDR %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECBR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECBR %x\\n\", intr);\n+\t\tqdma_writel(0xffffffff,\n+\t\t\t status + FSL_QDMA_DEDR);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DEDR);\n+\t}\n+\n+\tblock = fsl_qdma->block_base +\n+\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);\n+\n+\tintr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,\n+\t\t\t\t\t\tlast_idx, st);\n+\tif (intr < 0) {\n+\t\tvoid *ctrl = fsl_qdma->ctrl_base;\n+\n+\t\treg = qdma_readl(ctrl + FSL_QDMA_DMR);\n+\t\treg |= FSL_QDMA_DMR_DQD;\n+\t\tqdma_writel(reg, ctrl + FSL_QDMA_DMR);\n+\t\tqdma_writel(0, block + FSL_QDMA_BCQIER(0));\n+\t\tDPAA_QDMA_ERR(\"QDMA: status err!\\n\");\n+\t}\n+\n+\treturn intr;\n+}\n+\n+\n+static uint16_t\n+dpaa_qdma_dequeue(void *dev_private,\n+\t\t uint16_t vchan, const uint16_t nb_cpls,\n+\t\t uint16_t *last_idx, __rte_unused bool *has_error)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private;\n+\tint id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES);\n+\tvoid *block;\n+\tunsigned int reg;\n+\tint intr;\n+\tvoid *status = fsl_qdma->status_base;\n+\n+\tintr = qdma_readl_be(status + FSL_QDMA_DEDR);\n+\tif (intr) {\n+\t\tDPAA_QDMA_ERR(\"DMA transaction error! %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW0R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW0R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW1R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW1R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW2R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW2R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFDW3R);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFDW3R %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECFQIDR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECFQIDR %x\\n\", intr);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DECBR);\n+\t\tDPAA_QDMA_INFO(\"reg FSL_QDMA_DECBR %x\\n\", intr);\n+\t\tqdma_writel(0xffffffff,\n+\t\t\t status + FSL_QDMA_DEDR);\n+\t\tintr = qdma_readl(status + FSL_QDMA_DEDR);\n+\t}\n+\n+\tblock = fsl_qdma->block_base +\n+\t\tFSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);\n+\n+\tintr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls,\n+\t\t\t\t\t\tlast_idx, NULL);\n+\tif (intr < 0) {\n+\t\tvoid *ctrl = fsl_qdma->ctrl_base;\n+\n+\t\treg = qdma_readl(ctrl + FSL_QDMA_DMR);\n+\t\treg |= FSL_QDMA_DMR_DQD;\n+\t\tqdma_writel(reg, ctrl + FSL_QDMA_DMR);\n+\t\tqdma_writel(0, block + FSL_QDMA_BCQIER(0));\n+\t\tDPAA_QDMA_ERR(\"QDMA: status err!\\n\");\n+\t}\n+\n+\treturn intr;\n+}\n+\n static struct rte_dma_dev_ops dpaa_qdma_ops = {\n \t.dev_info_get\t\t = dpaa_info_get,\n \t.dev_configure = dpaa_qdma_configure,\n@@ -609,6 +949,10 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv,\n \tdmadev->dev_ops = &dpaa_qdma_ops;\n \tdmadev->device = &dpaa_dev->device;\n \tdmadev->fp_obj->dev_private = dmadev->data->dev_private;\n+\tdmadev->fp_obj->copy = dpaa_qdma_enqueue;\n+\tdmadev->fp_obj->submit = dpaa_qdma_submit;\n+\tdmadev->fp_obj->completed = dpaa_qdma_dequeue;\n+\tdmadev->fp_obj->completed_status = dpaa_qdma_dequeue_status;\n \n \t/* Invoke PMD device initialization function */\n \tret = dpaa_qdma_init(dmadev);\ndiff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h\nindex f482b16334..ef3c37e3a8 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.h\n+++ b/drivers/dma/dpaa/dpaa_qdma.h\n@@ -5,6 +5,10 @@\n #ifndef _DPAA_QDMA_H_\n #define _DPAA_QDMA_H_\n \n+#ifndef BIT\n+#define BIT(nr)\t\t(1UL << (nr))\n+#endif\n+\n #define CORE_NUMBER 4\n #define RETRIES\t5\n \n", "prefixes": [ "v2", "5/6" ] }