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GET /api/patches/103014/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 103014,
    "url": "https://patches.dpdk.org/api/patches/103014/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211027072810.257795-2-aman.kumar@vvdntech.in/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211027072810.257795-2-aman.kumar@vvdntech.in>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211027072810.257795-2-aman.kumar@vvdntech.in",
    "date": "2021-10-27T07:28:10",
    "name": "[v4,2/2] lib/eal: add temporal store memcpy support for AMD platform",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "a5d3dc3faa01d4f7087a200b9c86a5f6de7decb2",
    "submitter": {
        "id": 1965,
        "url": "https://patches.dpdk.org/api/people/1965/?format=api",
        "name": "Aman Kumar",
        "email": "aman.kumar@vvdntech.in"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211027072810.257795-2-aman.kumar@vvdntech.in/mbox/",
    "series": [
        {
            "id": 20034,
            "url": "https://patches.dpdk.org/api/series/20034/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20034",
            "date": "2021-10-27T07:28:09",
            "name": "[v4,1/2] config/x86: add support for AMD platform",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/20034/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/103014/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/103014/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B6131A0547;\n\tWed, 27 Oct 2021 09:28:31 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2360B410F4;\n\tWed, 27 Oct 2021 09:28:31 +0200 (CEST)",
            "from mail-pj1-f45.google.com (mail-pj1-f45.google.com\n [209.85.216.45]) by mails.dpdk.org (Postfix) with ESMTP id 74E0C410F4\n for <dev@dpdk.org>; Wed, 27 Oct 2021 09:28:29 +0200 (CEST)",
            "by mail-pj1-f45.google.com with SMTP id np13so1380104pjb.4\n for <dev@dpdk.org>; Wed, 27 Oct 2021 00:28:29 -0700 (PDT)",
            "from 470--5GDC--BLR.blore.vvdntech.com ([106.51.39.131])\n by smtp.gmail.com with ESMTPSA id f4sm21087651pgn.93.2021.10.27.00.28.25\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 27 Oct 2021 00:28:28 -0700 (PDT)"
        ],
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        "X-Gm-Message-State": "AOAM532yWIlbJWYIWDoZSUmLMLufPe7is2yWJRPnBe0IcKVdoeuWu6up\n 523mdE9Zr7SH8QHKAKaAkasmRFlb0ypNM2jx",
        "X-Google-Smtp-Source": "\n ABdhPJzDDy98rMDFyJ3+2Q4Xzfn2AfFvUsAe6d6GIMI8CVhew5Pjlezur54NYAYtaC+CuubMsr2Ffw==",
        "X-Received": "by 2002:a17:90b:3910:: with SMTP id\n ob16mr4063367pjb.234.1635319708449;\n Wed, 27 Oct 2021 00:28:28 -0700 (PDT)",
        "From": "Aman Kumar <aman.kumar@vvdntech.in>",
        "To": "dev@dpdk.org",
        "Cc": "thomas@monjalon.net, viacheslavo@nvidia.com, anatoly.burakov@intel.com,\n keesang.song@amd.com, aman.kumar@vvdntech.in, jerinjacobk@gmail.com,\n konstantin.ananyev@intel.com, bruce.richardson@intel.com",
        "Date": "Wed, 27 Oct 2021 12:58:10 +0530",
        "Message-Id": "<20211027072810.257795-2-aman.kumar@vvdntech.in>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20211027072810.257795-1-aman.kumar@vvdntech.in>",
        "References": "<20211026155645.246783-1-aman.kumar@vvdntech.in>\n <20211027072810.257795-1-aman.kumar@vvdntech.in>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v4 2/2] lib/eal: add temporal store memcpy\n support for AMD platform",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch provides a rte_memcpy* call with temporal stores.\nUse -Dcpu_instruction_set=znverX with build to enable this API.\n\nSigned-off-by: Aman Kumar <aman.kumar@vvdntech.in>\n---\n config/x86/meson.build           |   2 +\n lib/eal/x86/include/rte_memcpy.h | 114 +++++++++++++++++++++++++++++++\n 2 files changed, 116 insertions(+)",
    "diff": "diff --git a/config/x86/meson.build b/config/x86/meson.build\nindex 21cda6fd33..56dae4aca7 100644\n--- a/config/x86/meson.build\n+++ b/config/x86/meson.build\n@@ -78,6 +78,8 @@ if get_option('cpu_instruction_set') == 'znver1'\n     dpdk_conf.set('RTE_MAX_LCORE', 256)\n elif get_option('cpu_instruction_set') == 'znver2'\n     dpdk_conf.set('RTE_MAX_LCORE', 512)\n+    dpdk_conf.set('RTE_MEMCPY_AMDEPYC', 1)\n elif get_option('cpu_instruction_set') == 'znver3'\n     dpdk_conf.set('RTE_MAX_LCORE', 512)\n+    dpdk_conf.set('RTE_MEMCPY_AMDEPYC', 1)\n endif\ndiff --git a/lib/eal/x86/include/rte_memcpy.h b/lib/eal/x86/include/rte_memcpy.h\nindex 1b6c6e585f..8fe7822cb4 100644\n--- a/lib/eal/x86/include/rte_memcpy.h\n+++ b/lib/eal/x86/include/rte_memcpy.h\n@@ -376,6 +376,120 @@ rte_mov128blocks(uint8_t *dst, const uint8_t *src, size_t n)\n \t}\n }\n \n+#if defined RTE_MEMCPY_AMDEPYC\n+\n+/**\n+ * Copy 16 bytes from one location to another,\n+ * with temporal stores\n+ */\n+static __rte_always_inline void\n+rte_copy16_ts(uint8_t *dst, uint8_t *src)\n+{\n+\t__m128i var128;\n+\n+\tvar128 = _mm_stream_load_si128((__m128i *)src);\n+\t_mm_storeu_si128((__m128i *)dst, var128);\n+}\n+\n+/**\n+ * Copy 32 bytes from one location to another,\n+ * with temporal stores\n+ */\n+static __rte_always_inline void\n+rte_copy32_ts(uint8_t *dst, uint8_t *src)\n+{\n+\t__m256i ymm0;\n+\n+\tymm0 = _mm256_stream_load_si256((const __m256i *)src);\n+\t_mm256_storeu_si256((__m256i *)dst, ymm0);\n+}\n+\n+/**\n+ * Copy 64 bytes from one location to another,\n+ * with temporal stores\n+ */\n+static __rte_always_inline void\n+rte_copy64_ts(uint8_t *dst, uint8_t *src)\n+{\n+\trte_copy32_ts(dst + 0 * 32, src + 0 * 32);\n+\trte_copy32_ts(dst + 1 * 32, src + 1 * 32);\n+}\n+\n+/**\n+ * Copy 128 bytes from one location to another,\n+ * with temporal stores\n+ */\n+static __rte_always_inline void\n+rte_copy128_ts(uint8_t *dst, uint8_t *src)\n+{\n+\trte_copy32_ts(dst + 0 * 32, src + 0 * 32);\n+\trte_copy32_ts(dst + 1 * 32, src + 1 * 32);\n+\trte_copy32_ts(dst + 2 * 32, src + 2 * 32);\n+\trte_copy32_ts(dst + 3 * 32, src + 3 * 32);\n+}\n+\n+/**\n+ * Copy len bytes from one location to another,\n+ * with temporal stores 16B aligned\n+ */\n+static __rte_always_inline void *\n+rte_memcpy_aligned_tstore16_generic(void *dst, void *src, int len)\n+{\n+\tvoid *dest = dst;\n+\n+\twhile (len >= 128) {\n+\t\trte_copy128_ts((uint8_t *)dst, (uint8_t *)src);\n+\t\tdst = (uint8_t *)dst + 128;\n+\t\tsrc = (uint8_t *)src + 128;\n+\t\tlen -= 128;\n+\t}\n+\twhile (len >= 64) {\n+\t\trte_copy64_ts((uint8_t *)dst, (uint8_t *)src);\n+\t\tdst = (uint8_t *)dst + 64;\n+\t\tsrc = (uint8_t *)src + 64;\n+\t\tlen -= 64;\n+\t}\n+\twhile (len >= 32) {\n+\t\trte_copy32_ts((uint8_t *)dst, (uint8_t *)src);\n+\t\tdst = (uint8_t *)dst + 32;\n+\t\tsrc = (uint8_t *)src + 32;\n+\t\tlen -= 32;\n+\t}\n+\tif (len >= 16) {\n+\t\trte_copy16_ts((uint8_t *)dst, (uint8_t *)src);\n+\t\tdst = (uint8_t *)dst + 16;\n+\t\tsrc = (uint8_t *)src + 16;\n+\t\tlen -= 16;\n+\t}\n+\tif (len >= 8) {\n+\t\t*(uint64_t *)dst = *(const uint64_t *)src;\n+\t\tdst = (uint8_t *)dst + 8;\n+\t\tsrc = (uint8_t *)src + 8;\n+\t\tlen -= 8;\n+\t}\n+\tif (len >= 4) {\n+\t\t*(uint32_t *)dst = *(const uint32_t *)src;\n+\t\tdst = (uint8_t *)dst + 4;\n+\t\tsrc = (uint8_t *)src + 4;\n+\t\tlen -= 4;\n+\t}\n+\tif (len != 0) {\n+\t\tdst = (uint8_t *)dst - (4 - len);\n+\t\tsrc = (uint8_t *)src - (4 - len);\n+\t\t*(uint32_t *)dst = *(const uint32_t *)src;\n+\t}\n+\n+\treturn dest;\n+}\n+\n+static __rte_always_inline void *\n+rte_memcpy_aligned_tstore16(void *dst, void *src, int len)\n+{\n+\treturn rte_memcpy_aligned_tstore16_generic(dst, src, len);\n+}\n+\n+#endif /* RTE_MEMCPY_AMDEPYC */\n+\n static __rte_always_inline void *\n rte_memcpy_generic(void *dst, const void *src, size_t n)\n {\n",
    "prefixes": [
        "v4",
        "2/2"
    ]
}