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GET /api/patches/102887/?format=api
{ "id": 102887, "url": "https://patches.dpdk.org/api/patches/102887/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211026092543.13224-2-getelson@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211026092543.13224-2-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211026092543.13224-2-getelson@nvidia.com", "date": "2021-10-26T09:25:43", "name": "[2/2] net/mlx5: fix integrity flow item validation and translation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "970ebc1d56f22c343b2395b1090397f0358bc86e", "submitter": { "id": 1882, "url": "https://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211026092543.13224-2-getelson@nvidia.com/mbox/", "series": [ { "id": 19991, "url": "https://patches.dpdk.org/api/series/19991/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19991", "date": "2021-10-26T09:25:42", "name": "[1/2] net/mlx5: fix integrity matching for inner and outer headers", "version": 1, "mbox": "https://patches.dpdk.org/series/19991/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/102887/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/102887/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D73FDA0C47;\n\tTue, 26 Oct 2021 11:26:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 41126426DF;\n\tTue, 26 Oct 2021 11:26:06 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2062.outbound.protection.outlook.com [40.107.94.62])\n by mails.dpdk.org (Postfix) with ESMTP id 6421D426D7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>, <getelson@nvidia.com>", "CC": "<matan@nvidia.com>, <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "Date": "Tue, 26 Oct 2021 12:25:43 +0300", "Message-ID": "<20211026092543.13224-2-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.33.1", "In-Reply-To": "<20211026092543.13224-1-getelson@nvidia.com>", "References": "<20211026092543.13224-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "102f4f1f-c003-4388-2e49-08d99862a036", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1215:", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB12151F52B4E18249033C7305A5849@MWHPR12MB1215.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2887;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n V7aTAycL3s2Zk6x1MCFmY3dJEUdsNx4Ne/r04EKVA6x2Dl/JJm0YpSh5BgiSP+pIF2FelvcUHWqqG8E9FjE2uCaBt3LKsccZq/32rOQAUSwjMgYIeUnMK2l88rkefT+lamISq4J07DrOLL6cnWTGtcUlOtTNCIJBXCncr9jACnmpiNIsSAcfi/O6+dFqWBw93rbAuNblswH6ZPkrUpeGoqmlGgkmoWXf6dxBcrFlhT6CQTIQJKFfHPfMgf4OctyXCh2T0ehHd4dJbjfAW7R37qL6LAolw1eBrtzJQWinIf3VjO11PY1jJzz02ExGZBTsVDDL+L9cqwBcr7Zdn5qN5IJmw8zKp12kf/HDldEpQXrBEb3NwhRXmXME/s6cvp6zMgXBi1A5fVoa33tYb68k0qerqS2WnenLwEQBnBTwM99FQthWtT5qcXjhpfR6KktgwWaVnQsfKfSBmsm+nXl/6wJukonNI4GXhTZW1vWxsgjOAJd68+NnU6fP9i19sEfIuErQOF+ds0a/WeZRaGNSzPVy0HCHZAki+8eaE4vu3epAokjAs0X9Pv1tilTGN07iLcounGD4iPsESQUZJtxNO6VMGXpjcWLFr0WOT5guBlaV8wmF4NINvTq75mJJ7odUyByI0ulD8V2zMyYQ8SsSM0C7HF50876xVMtL33RWfW1SD/+1DtuQBoqUZJIhDGanJDWVbciMzCKghpft5PMLvA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(54906003)(47076005)(36756003)(1076003)(110136005)(5660300002)(356005)(83380400001)(70586007)(7696005)(336012)(6666004)(26005)(8676002)(7049001)(107886003)(7636003)(70206006)(30864003)(16526019)(86362001)(36906005)(36860700001)(8936002)(316002)(2906002)(4326008)(426003)(2616005)(6286002)(508600001)(55016002)(82310400003)(186003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Oct 2021 09:26:00.9439 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 102f4f1f-c003-4388-2e49-08d99862a036", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT054.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1215", "Subject": "[dpdk-dev] [PATCH 2/2] net/mlx5: fix integrity flow item validation\n and translation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Integrity item validation and translation must verify that integrity\nitem bits match L3 and L4 items in flow rule pattern.\nFor cases when integrity item was positioned before L3 header, such\nverification must be split into two stages.\nThe first stage detects integrity flow item and makes intializations\nfor the second stage.\nThe second stage is activated after PMD completes processing of all\nflow items in rule pattern. PMD accumulates information about flow\nitems in flow pattern. When all pattern flow items were processed,\nPMD can apply that data to complete integrity item validation\nand translation.\n\nFixes: 79f8952783d0 (\"net/mlx5: support integrity flow item\")\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 2 +\n drivers/net/mlx5/mlx5_flow_dv.c | 293 +++++++++++++-------------------\n 2 files changed, 119 insertions(+), 176 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 41e24deec5..5a07afa8df 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -173,6 +173,8 @@ enum mlx5_feature_name {\n /* INTEGRITY item bits */\n #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)\n #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)\n+#define MLX5_FLOW_ITEM_INTEGRITY \\\n+\t(MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)\n \n /* Conntrack item. */\n #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex c27c2df5c4..a2bcaf0f1c 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -287,31 +287,6 @@ struct field_modify_info modify_tcp[] = {\n \t{0, 0, 0},\n };\n \n-static const struct rte_flow_item *\n-mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)\n-{\n-\tfor (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n-\t\tswitch (item->type) {\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n-\t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n-\t\tcase RTE_FLOW_ITEM_TYPE_MPLS:\n-\t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n-\t\tcase RTE_FLOW_ITEM_TYPE_GENEVE:\n-\t\t\treturn item;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\t\tif (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||\n-\t\t\t item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)\n-\t\t\t\treturn item;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn NULL;\n-}\n-\n static void\n mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,\n \t\t\t uint8_t next_protocol, uint64_t *item_flags,\n@@ -6581,114 +6556,74 @@ flow_dv_validate_attributes(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n-static uint16_t\n-mlx5_flow_locate_proto_l3(const struct rte_flow_item **head,\n-\t\t\t const struct rte_flow_item *end)\n+static int\n+validate_integrity_bits(const struct rte_flow_item_integrity *mask,\n+\t\t\tint64_t pattern_flags, uint64_t l3_flags,\n+\t\t\tuint64_t l4_flags, uint64_t ip4_flag,\n+\t\t\tstruct rte_flow_error *error)\n {\n-\tconst struct rte_flow_item *item = *head;\n-\tuint16_t l3_protocol;\n+\tif (mask->l3_ok && !(pattern_flags & l3_flags))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t NULL, \"missing L3 protocol\");\n+\n+\tif (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t NULL, \"missing IPv4 protocol\");\n+\n+\tif ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t NULL, \"missing L4 protocol\");\n \n-\tfor (; item != end; item++) {\n-\t\tswitch (item->type) {\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\t\tl3_protocol = RTE_ETHER_TYPE_IPV4;\n-\t\t\tgoto l3_ok;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\t\tl3_protocol = RTE_ETHER_TYPE_IPV6;\n-\t\t\tgoto l3_ok;\n-\t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n-\t\t\tif (item->mask && item->spec) {\n-\t\t\t\tMLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_eth,\n-\t\t\t\t\t\t\t type, item,\n-\t\t\t\t\t\t\t l3_protocol);\n-\t\t\t\tif (l3_protocol == RTE_ETHER_TYPE_IPV4 ||\n-\t\t\t\t l3_protocol == RTE_ETHER_TYPE_IPV6)\n-\t\t\t\t\tgoto l3_ok;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n-\t\t\tif (item->mask && item->spec) {\n-\t\t\t\tMLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_vlan,\n-\t\t\t\t\t\t\t inner_type, item,\n-\t\t\t\t\t\t\t l3_protocol);\n-\t\t\t\tif (l3_protocol == RTE_ETHER_TYPE_IPV4 ||\n-\t\t\t\t l3_protocol == RTE_ETHER_TYPE_IPV6)\n-\t\t\t\t\tgoto l3_ok;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n-\t}\n \treturn 0;\n-l3_ok:\n-\t*head = item;\n-\treturn l3_protocol;\n }\n \n-static uint8_t\n-mlx5_flow_locate_proto_l4(const struct rte_flow_item **head,\n-\t\t\t const struct rte_flow_item *end)\n+static int\n+flow_dv_validate_item_integrity_post(const struct\n+\t\t\t\t rte_flow_item *integrity_items[2],\n+\t\t\t\t int64_t pattern_flags,\n+\t\t\t\t struct rte_flow_error *error)\n {\n-\tconst struct rte_flow_item *item = *head;\n-\tuint8_t l4_protocol;\n+\tconst struct rte_flow_item_integrity *mask;\n+\tint ret;\n \n-\tfor (; item != end; item++) {\n-\t\tswitch (item->type) {\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n-\t\t\tl4_protocol = IPPROTO_TCP;\n-\t\t\tgoto l4_ok;\n-\t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n-\t\t\tl4_protocol = IPPROTO_UDP;\n-\t\t\tgoto l4_ok;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\t\tif (item->mask && item->spec) {\n-\t\t\t\tconst struct rte_flow_item_ipv4 *mask, *spec;\n-\n-\t\t\t\tmask = (typeof(mask))item->mask;\n-\t\t\t\tspec = (typeof(spec))item->spec;\n-\t\t\t\tl4_protocol = mask->hdr.next_proto_id &\n-\t\t\t\t\t spec->hdr.next_proto_id;\n-\t\t\t\tif (l4_protocol == IPPROTO_TCP ||\n-\t\t\t\t l4_protocol == IPPROTO_UDP)\n-\t\t\t\t\tgoto l4_ok;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\t\tif (item->mask && item->spec) {\n-\t\t\t\tconst struct rte_flow_item_ipv6 *mask, *spec;\n-\t\t\t\tmask = (typeof(mask))item->mask;\n-\t\t\t\tspec = (typeof(spec))item->spec;\n-\t\t\t\tl4_protocol = mask->hdr.proto & spec->hdr.proto;\n-\t\t\t\tif (l4_protocol == IPPROTO_TCP ||\n-\t\t\t\t l4_protocol == IPPROTO_UDP)\n-\t\t\t\t\tgoto l4_ok;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n+\tif (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {\n+\t\tmask = (typeof(mask))integrity_items[0]->mask;\n+\t\tret = validate_integrity_bits(mask, pattern_flags,\n+\t\t\t\t\t MLX5_FLOW_LAYER_OUTER_L3,\n+\t\t\t\t\t MLX5_FLOW_LAYER_OUTER_L4,\n+\t\t\t\t\t MLX5_FLOW_LAYER_OUTER_L3_IPV4,\n+\t\t\t\t\t error);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tif (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {\n+\t\tmask = (typeof(mask))integrity_items[1]->mask;\n+\t\tret = validate_integrity_bits(mask, pattern_flags,\n+\t\t\t\t\t MLX5_FLOW_LAYER_INNER_L3,\n+\t\t\t\t\t MLX5_FLOW_LAYER_INNER_L4,\n+\t\t\t\t\t MLX5_FLOW_LAYER_INNER_L3_IPV4,\n+\t\t\t\t\t error);\n+\t\tif (ret)\n+\t\t\treturn ret;\n \t}\n \treturn 0;\n-l4_ok:\n-\t*head = item;\n-\treturn l4_protocol;\n }\n \n static int\n flow_dv_validate_item_integrity(struct rte_eth_dev *dev,\n-\t\t\t\tconst struct rte_flow_item *rule_items,\n \t\t\t\tconst struct rte_flow_item *integrity_item,\n-\t\t\t\tuint64_t item_flags, uint64_t *last_item,\n+\t\t\t\tuint64_t pattern_flags, uint64_t *last_item,\n+\t\t\t\tconst struct rte_flow_item *integrity_items[2],\n \t\t\t\tstruct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tconst struct rte_flow_item *tunnel_item, *end_item, *item = rule_items;\n \tconst struct rte_flow_item_integrity *mask = (typeof(mask))\n \t\t\t\t\t\t integrity_item->mask;\n \tconst struct rte_flow_item_integrity *spec = (typeof(spec))\n \t\t\t\t\t\t integrity_item->spec;\n-\tuint32_t protocol;\n \n \tif (!priv->config.hca_attr.pkt_integrity_match)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n@@ -6707,47 +6642,23 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t integrity_item,\n \t\t\t\t\t \"unsupported integrity filter\");\n-\ttunnel_item = mlx5_flow_find_tunnel_item(rule_items);\n \tif (spec->level > 1) {\n-\t\tif (item_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)\n+\t\tif (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)\n \t\t\treturn rte_flow_error_set\n \t\t\t\t(error, ENOTSUP,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t NULL, \"multiple inner integrity items not supported\");\n-\t\tif (!tunnel_item)\n-\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t integrity_item,\n-\t\t\t\t\t\t \"missing tunnel item\");\n-\t\titem = tunnel_item;\n-\t\tend_item = mlx5_find_end_item(tunnel_item);\n+\t\tintegrity_items[1] = integrity_item;\n+\t\t*last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;\n \t} else {\n-\t\tif (item_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)\n+\t\tif (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)\n \t\t\treturn rte_flow_error_set\n \t\t\t\t(error, ENOTSUP,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t NULL, \"multiple outer integrity items not supported\");\n-\t\tend_item = tunnel_item ? tunnel_item :\n-\t\t\t mlx5_find_end_item(integrity_item);\n+\t\tintegrity_items[0] = integrity_item;\n+\t\t*last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n \t}\n-\tif (mask->l3_ok || mask->ipv4_csum_ok) {\n-\t\tprotocol = mlx5_flow_locate_proto_l3(&item, end_item);\n-\t\tif (!protocol)\n-\t\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t integrity_item,\n-\t\t\t\t\t\t \"missing L3 protocol\");\n-\t}\n-\tif (mask->l4_ok || mask->l4_csum_ok) {\n-\t\tprotocol = mlx5_flow_locate_proto_l4(&item, end_item);\n-\t\tif (!protocol)\n-\t\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t integrity_item,\n-\t\t\t\t\t\t \"missing L4 protocol\");\n-\t}\n-\t*last_item |= spec->level > 1 ? MLX5_FLOW_ITEM_INNER_INTEGRITY :\n-\t\t\t\t\tMLX5_FLOW_ITEM_OUTER_INTEGRITY;\n \treturn 0;\n }\n \n@@ -6843,7 +6754,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t.std_tbl_fix = true,\n \t};\n \tconst struct rte_eth_hairpin_conf *conf;\n-\tconst struct rte_flow_item *rule_items = items;\n+\tconst struct rte_flow_item *integrity_items[2] = {NULL, NULL};\n \tconst struct rte_flow_item *port_id_item = NULL;\n \tbool def_policy = false;\n \tuint16_t udp_dport = 0;\n@@ -7170,10 +7081,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n-\t\t\tret = flow_dv_validate_item_integrity(dev, rule_items,\n-\t\t\t\t\t\t\t items,\n+\t\t\tret = flow_dv_validate_item_integrity(dev, items,\n \t\t\t\t\t\t\t item_flags,\n \t\t\t\t\t\t\t &last_item,\n+\t\t\t\t\t\t\t integrity_items,\n \t\t\t\t\t\t\t error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n@@ -7196,6 +7107,12 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t}\n \t\titem_flags |= last_item;\n \t}\n+\tif (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {\n+\t\tret = flow_dv_validate_item_integrity_post(integrity_items,\n+\t\t\t\t\t\t\t item_flags, error);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n \tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n \t\tint type = actions->type;\n \t\tbool shared_count = false;\n@@ -12083,8 +12000,7 @@ flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,\n static void\n flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,\n \t\t\t const struct rte_flow_item_integrity *value,\n-\t\t\t void *headers_m, void *headers_v,\n-\t\t\t bool is_ipv4)\n+\t\t\t void *headers_m, void *headers_v, bool is_ipv4)\n {\n \tif (mask->l3_ok) {\n \t\t/* application l3_ok filter aggregates all hardware l3 filters\n@@ -12115,45 +12031,66 @@ flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,\n }\n \n static void\n-flow_dv_translate_item_integrity(void *matcher, void *key,\n-\t\t\t\t const struct rte_flow_item *head_item,\n-\t\t\t\t const struct rte_flow_item *integrity_item)\n+set_integrity_bits(void *headers_m, void *headers_v,\n+\t\t const struct rte_flow_item *integrity_item, bool is_l3_ip4)\n {\n+\tconst struct rte_flow_item_integrity *spec = integrity_item->spec;\n \tconst struct rte_flow_item_integrity *mask = integrity_item->mask;\n-\tconst struct rte_flow_item_integrity *value = integrity_item->spec;\n-\tconst struct rte_flow_item *tunnel_item, *end_item, *item;\n-\tvoid *headers_m;\n-\tvoid *headers_v;\n-\tuint32_t l3_protocol;\n \n-\tif (!value)\n-\t\treturn;\n+\t/* Integrity bits validation cleared spec pointer */\n+\tMLX5_ASSERT(spec != NULL);\n \tif (!mask)\n \t\tmask = &rte_flow_item_integrity_mask;\n-\tif (value->level > 1) {\n+\tflow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,\n+\t\t\t\t is_l3_ip4);\n+\tflow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);\n+}\n+\n+static void\n+flow_dv_translate_item_integrity_post(void *matcher, void *key,\n+\t\t\t\t const\n+\t\t\t\t struct rte_flow_item *integrity_items[2],\n+\t\t\t\t uint64_t pattern_flags)\n+{\n+\tvoid *headers_m, *headers_v;\n+\tbool is_l3_ip4;\n+\n+\tif (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {\n \t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n \t\t\t\t\t inner_headers);\n \t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);\n-\t} else {\n+\t\tis_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=\n+\t\t\t 0;\n+\t\tset_integrity_bits(headers_m, headers_v,\n+\t\t\t\t integrity_items[1], is_l3_ip4);\n+\t}\n+\tif (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {\n \t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n \t\t\t\t\t outer_headers);\n \t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);\n+\t\tis_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=\n+\t\t\t 0;\n+\t\tset_integrity_bits(headers_m, headers_v,\n+\t\t\t\t integrity_items[0], is_l3_ip4);\n \t}\n-\ttunnel_item = mlx5_flow_find_tunnel_item(head_item);\n-\tif (value->level > 1) {\n-\t\t/* tunnel item was verified during the item validation */\n-\t\titem = tunnel_item;\n-\t\tend_item = mlx5_find_end_item(tunnel_item);\n+}\n+\n+static void\n+flow_dv_translate_item_integrity(const struct rte_flow_item *item,\n+\t\t\t\t const struct rte_flow_item *integrity_items[2],\n+\t\t\t\t uint64_t *last_item)\n+{\n+\tconst struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;\n+\n+\t/* integrity bits validation cleared spec pointer */\n+\tMLX5_ASSERT(spec != NULL);\n+\tif (spec->level > 1) {\n+\t\tintegrity_items[1] = item;\n+\t\t*last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;\n \t} else {\n-\t\titem = head_item;\n-\t\tend_item = tunnel_item ? tunnel_item :\n-\t\t\t mlx5_find_end_item(integrity_item);\n+\t\tintegrity_items[0] = item;\n+\t\t*last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n \t}\n-\tl3_protocol = mask->l3_ok ?\n-\t\t mlx5_flow_locate_proto_l3(&item, end_item) : 0;\n-\tflow_dv_translate_integrity_l3(mask, value, headers_m, headers_v,\n-\t\t\t\t l3_protocol == RTE_ETHER_TYPE_IPV4);\n-\tflow_dv_translate_integrity_l4(mask, value, headers_m, headers_v);\n }\n \n /**\n@@ -12569,7 +12506,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t(1 << MLX5_SCALE_FLOW_GROUP_BIT),\n \t\t.std_tbl_fix = true,\n \t};\n-\tconst struct rte_flow_item *head_item = items;\n+\tconst struct rte_flow_item *integrity_items[2] = {NULL, NULL};\n \n \tif (!wks)\n \t\treturn rte_flow_error_set(error, ENOMEM,\n@@ -13462,9 +13399,8 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n-\t\t\tflow_dv_translate_item_integrity(match_mask,\n-\t\t\t\t\t\t\t match_value,\n-\t\t\t\t\t\t\t head_item, items);\n+\t\t\tflow_dv_translate_item_integrity(items, integrity_items,\n+\t\t\t\t\t\t\t &last_item);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \t\t\tflow_dv_translate_item_aso_ct(dev, match_mask,\n@@ -13488,6 +13424,11 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t match_value, NULL, attr))\n \t\t\treturn -rte_errno;\n \t}\n+\tif (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {\n+\t\tflow_dv_translate_item_integrity_post(match_mask, match_value,\n+\t\t\t\t\t\t integrity_items,\n+\t\t\t\t\t\t item_flags);\n+\t}\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n \tMLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,\n \t\t\t\t\t dev_flow->dv.value.buf));\n", "prefixes": [ "2/2" ] }