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GET /api/patches/102834/?format=api
{ "id": 102834, "url": "https://patches.dpdk.org/api/patches/102834/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211026041300.28924-3-radhac@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211026041300.28924-3-radhac@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211026041300.28924-3-radhac@marvell.com", "date": "2021-10-26T04:12:59", "name": "[3/4] dma/cnxk: add dma channel operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "7bd5af3e55de0b38accb1b146d03bba0c8d9b385", "submitter": { "id": 2007, "url": "https://patches.dpdk.org/api/people/2007/?format=api", "name": "Radha Chintakuntla", "email": "radhac@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211026041300.28924-3-radhac@marvell.com/mbox/", "series": [ { "id": 19972, "url": "https://patches.dpdk.org/api/series/19972/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19972", "date": "2021-10-26T04:12:58", "name": "[1/4] common/cnxk: add DPI DMA support", "version": 1, "mbox": "https://patches.dpdk.org/series/19972/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/102834/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/102834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1C006A0C47;\n\tTue, 26 Oct 2021 06:13:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DA3B241173;\n\tTue, 26 Oct 2021 06:13:29 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 847C740A4B\n for <dev@dpdk.org>; Tue, 26 Oct 2021 06:13:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 19PLKxk5012626;\n Mon, 25 Oct 2021 21:13:25 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3bx4dx1971-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 25 Oct 2021 21:13:24 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 25 Oct 2021 21:13:22 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 25 Oct 2021 21:13:22 -0700", "from rchintakuntla-lnx3.caveonetworks.com (unknown [10.111.140.81])\n by maili.marvell.com (Postfix) with ESMTP id 12BD53F7093;\n Mon, 25 Oct 2021 21:13:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=FIldgSkaVRSxmyGnW8mZPn07Z3dMpGtAT1dQgn1BRd8=;\n b=IocZIVt27ELjXoA+31/X98MQkjVkXEEe49QiqOpElHk4WLMiRGUvj56CULbyw6wjNsMO\n uIkNiKbGHbGZM3ia8NAp6jtVcir3IkB3HyUXrRG/OQ+ddR4HKFI0+NNU4uDYW9+9mrPu\n 5CGBYP9odTj14aRNkSvjT014L1zRhA8QLG3O9eKnr0IW/XbPXeRF3e4utmoGhaBfaA+y\n rNSRK0xYJRr+17C9y25do0pTeqoUeeGzQXE3sKRo03iUIFtzBLVN9PznrKB3qtpc2cwQ\n cfl7h+SYuwX+38K6JxuoE/ihFbZlhlO46gD5C8ZWQ2I69TcpbsaysB/oFnkGakunX3i0 Tg==", "From": "Radha Mohan Chintakuntla <radhac@marvell.com>", "To": "<thomas@monjalon.net>, <fengchengwen@huawei.com>,\n <ndabilpuram@marvell.com>, <kirankumark@marvell.com>,\n <skori@marvell.com>, <skoteshwar@marvell.com>, <jerinj@marvell.com>,\n <sburla@marvell.com>", "CC": "<dev@dpdk.org>, Radha Mohan Chintakuntla <radhac@marvell.com>", "Date": "Mon, 25 Oct 2021 21:12:59 -0700", "Message-ID": "<20211026041300.28924-3-radhac@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211026041300.28924-1-radhac@marvell.com>", "References": "<20211026041300.28924-1-radhac@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "c6yF7zaCDraoPPMrjjnTBF0nATeH5Tzi", "X-Proofpoint-ORIG-GUID": "c6yF7zaCDraoPPMrjjnTBF0nATeH5Tzi", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475\n definitions=2021-10-25_08,2021-10-25_02,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add functions for the dmadev vchan setup and DMA operations.\n\nSigned-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>\n---\n drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++\n drivers/dma/cnxk/cnxk_dmadev.h | 53 ++++++\n drivers/dma/cnxk/version.map | 3 +\n 3 files changed, 378 insertions(+)\n create mode 100644 drivers/dma/cnxk/version.map", "diff": "diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c\nindex 620766743d..8434579aa2 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev.c\n@@ -18,6 +18,322 @@\n #include <roc_api.h>\n #include <cnxk_dmadev.h>\n \n+static int\n+cnxk_dmadev_info_get(const struct rte_dma_dev *dev,\n+\t\t struct rte_dma_info *dev_info, uint32_t size)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(size);\n+\n+\tdev_info->max_vchans = 1;\n+\tdev_info->nb_vchans = 1;\n+\tdev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |\n+\t\tRTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |\n+\t\tRTE_DMA_CAPA_OPS_COPY;\n+\tdev_info->max_desc = DPI_MAX_DESC;\n+\tdev_info->min_desc = 1;\n+\tdev_info->max_sges = DPI_MAX_POINTER;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_dmadev_configure(struct rte_dma_dev *dev,\n+\t\t const struct rte_dma_conf *conf, uint32_t conf_sz)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = NULL;\n+\tint rc = 0;\n+\n+\tRTE_SET_USED(conf);\n+\tRTE_SET_USED(conf);\n+\tRTE_SET_USED(conf_sz);\n+\tRTE_SET_USED(conf_sz);\n+\tdpivf = dev->fp_obj->dev_private;\n+\trc = roc_dpi_queue_configure(&dpivf->rdpi);\n+\tif (rc < 0)\n+\t\tplt_err(\"DMA queue configure failed err = %d\", rc);\n+\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,\n+\t\t\tconst struct rte_dma_vchan_conf *conf,\n+\t\t\tuint32_t conf_sz)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;\n+\tstruct cnxk_dpi_compl_s *comp_data;\n+\tint i;\n+\n+\tRTE_SET_USED(vchan);\n+\tRTE_SET_USED(conf_sz);\n+\n+\tswitch (conf->direction) {\n+\tcase RTE_DMA_DIR_DEV_TO_MEM:\n+\t\tdpivf->conf.direction = DPI_XTYPE_INBOUND;\n+\t\tdpivf->conf.src_port = conf->src_port.pcie.coreid;\n+\t\tdpivf->conf.dst_port = 0;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_MEM_TO_DEV:\n+\t\tdpivf->conf.direction = DPI_XTYPE_OUTBOUND;\n+\t\tdpivf->conf.src_port = 0;\n+\t\tdpivf->conf.dst_port = conf->dst_port.pcie.coreid;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_MEM_TO_MEM:\n+\t\tdpivf->conf.direction = DPI_XTYPE_INTERNAL_ONLY;\n+\t\tdpivf->conf.src_port = 0;\n+\t\tdpivf->conf.dst_port = 0;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_DEV_TO_DEV:\n+\t\tdpivf->conf.direction = DPI_XTYPE_EXTERNAL_ONLY;\n+\t\tdpivf->conf.src_port = conf->src_port.pcie.coreid;\n+\t\tdpivf->conf.dst_port = conf->src_port.pcie.coreid;\n+\t};\n+\n+\tfor (i = 0; i < conf->nb_desc; i++) {\n+\t\tcomp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);\n+\t\tdpivf->conf.c_desc.compl_ptr[i] = comp_data;\n+\t};\n+\tdpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;\n+\tdpivf->conf.c_desc.head = 0;\n+\tdpivf->conf.c_desc.tail = 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_dmadev_start(struct rte_dma_dev *dev)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;\n+\n+\troc_dpi_queue_start(&dpivf->rdpi);\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_dmadev_stop(struct rte_dma_dev *dev)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;\n+\n+\troc_dpi_queue_stop(&dpivf->rdpi);\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_dmadev_close(struct rte_dma_dev *dev)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;\n+\n+\troc_dpi_queue_stop(&dpivf->rdpi);\n+\troc_dpi_dev_fini(&dpivf->rdpi);\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)\n+{\n+\tuint64_t *ptr = dpi->chunk_base;\n+\n+\tif ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||\n+\t cmds == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * Normally there is plenty of room in the current buffer for the\n+\t * command\n+\t */\n+\tif (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {\n+\t\tptr += dpi->chunk_head;\n+\t\tdpi->chunk_head += cmd_count;\n+\t\twhile (cmd_count--)\n+\t\t\t*ptr++ = *cmds++;\n+\t} else {\n+\t\tint count;\n+\t\tuint64_t *new_buff = dpi->chunk_next;\n+\n+\t\tdpi->chunk_next =\n+\t\t\t(void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);\n+\t\tif (!dpi->chunk_next) {\n+\t\t\tplt_err(\"Failed to alloc next buffer from NPA\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Figure out how many cmd words will fit in this buffer.\n+\t\t * One location will be needed for the next buffer pointer.\n+\t\t */\n+\t\tcount = dpi->pool_size_m1 - dpi->chunk_head;\n+\t\tptr += dpi->chunk_head;\n+\t\tcmd_count -= count;\n+\t\twhile (count--)\n+\t\t\t*ptr++ = *cmds++;\n+\n+\t\t/*\n+\t\t * chunk next ptr is 2 DWORDS\n+\t\t * second DWORD is reserved.\n+\t\t */\n+\t\t*ptr++ = (uint64_t)new_buff;\n+\t\t*ptr = 0;\n+\n+\t\t/*\n+\t\t * The current buffer is full and has a link to the next\n+\t\t * buffers. Time to write the rest of the commands into the new\n+\t\t * buffer.\n+\t\t */\n+\t\tdpi->chunk_base = new_buff;\n+\t\tdpi->chunk_head = cmd_count;\n+\t\tptr = new_buff;\n+\t\twhile (cmd_count--)\n+\t\t\t*ptr++ = *cmds++;\n+\n+\t\t/* queue index may be greater than pool size */\n+\t\tif (dpi->chunk_head >= dpi->pool_size_m1) {\n+\t\t\tnew_buff = dpi->chunk_next;\n+\t\t\tdpi->chunk_next =\n+\t\t\t\t(void *)roc_npa_aura_op_alloc(dpi->aura_handle,\n+\t\t\t\t\t\t\t 0);\n+\t\t\tif (!dpi->chunk_next) {\n+\t\t\t\tplt_err(\"Failed to alloc next buffer from NPA\");\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\t\t\t/* Write next buffer address */\n+\t\t\t*ptr = (uint64_t)new_buff;\n+\t\t\tdpi->chunk_base = new_buff;\n+\t\t\tdpi->chunk_head = 0;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,\n+\t\t rte_iova_t dst, uint32_t length, uint64_t flags)\n+{\n+\tuint64_t cmd[DPI_MAX_CMD_SIZE] = {0};\n+\tunion dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];\n+\trte_iova_t fptr, lptr;\n+\tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tint num_words = 0;\n+\tint rc;\n+\n+\tRTE_SET_USED(vchan);\n+\n+\theader->s.xtype = dpivf->conf.direction;\n+\theader->s.pt = DPI_HDR_PT_ZBW_CA;\n+\tcomp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];\n+\tcomp_ptr->cdata = DPI_REQ_CDATA;\n+\theader->s.ptr = (uint64_t)comp_ptr;\n+\tSTRM_INC(dpivf->conf.c_desc);\n+\n+\t/* pvfe should be set for inbound and outbound only */\n+\tif (header->s.xtype <= 1)\n+\t\theader->s.pvfe = 1;\n+\tnum_words += 4;\n+\n+\theader->s.nfst = 1;\n+\theader->s.nlst = 1;\n+\t/*\n+\t * For inbound case, src pointers are last pointers.\n+\t * For all other cases, src pointers are first pointers.\n+\t */\n+\tif (header->s.xtype == DPI_XTYPE_INBOUND) {\n+\t\tfptr = dst;\n+\t\tlptr = src;\n+\t\theader->s.fport = dpivf->conf.dst_port & 0x3;\n+\t\theader->s.lport = dpivf->conf.src_port & 0x3;\n+\t} else {\n+\t\tfptr = src;\n+\t\tlptr = dst;\n+\t\theader->s.fport = dpivf->conf.src_port & 0x3;\n+\t\theader->s.lport = dpivf->conf.dst_port & 0x3;\n+\t}\n+\n+\tcmd[num_words++] = length;\n+\tcmd[num_words++] = fptr;\n+\tcmd[num_words++] = length;\n+\tcmd[num_words++] = lptr;\n+\n+\trc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words);\n+\tif (!rc) {\n+\t\tif (flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\t\trte_wmb();\n+\t\t\tplt_write64(num_words,\n+\t\t\t\t dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\t\t}\n+\t\tdpivf->num_words = num_words;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static uint16_t\n+cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,\n+\t\t uint16_t *last_idx, bool *has_error)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n+\tint cnt;\n+\n+\tRTE_SET_USED(vchan);\n+\tRTE_SET_USED(last_idx);\n+\tRTE_SET_USED(has_error);\n+\tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n+\t\tstruct cnxk_dpi_compl_s *comp_ptr =\n+\t\t\tdpivf->conf.c_desc.compl_ptr[cnt];\n+\n+\t\tif (comp_ptr->cdata)\n+\t\t\tbreak;\n+\t}\n+\n+\tdpivf->conf.c_desc.tail = cnt;\n+\n+\treturn cnt;\n+}\n+\n+static uint16_t\n+cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,\n+\t\t\t const uint16_t nb_cpls, uint16_t *last_idx,\n+\t\t\t enum rte_dma_status_code *status)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n+\tint cnt;\n+\n+\tRTE_SET_USED(vchan);\n+\tRTE_SET_USED(last_idx);\n+\tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n+\t\tstruct cnxk_dpi_compl_s *comp_ptr =\n+\t\t\tdpivf->conf.c_desc.compl_ptr[cnt];\n+\t\tstatus[cnt] = comp_ptr->cdata;\n+\t}\n+\n+\tdpivf->conf.c_desc.tail = 0;\n+\treturn cnt;\n+}\n+\n+static int\n+cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)\n+{\n+\tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n+\n+\trte_wmb();\n+\tplt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_dma_dev_ops cnxk_dmadev_ops = {\n+\t.dev_info_get = cnxk_dmadev_info_get,\n+\t.dev_configure = cnxk_dmadev_configure,\n+\t.dev_start = cnxk_dmadev_start,\n+\t.dev_stop = cnxk_dmadev_stop,\n+\t.vchan_setup = cnxk_dmadev_vchan_setup,\n+\t.dev_close = cnxk_dmadev_close,\n+};\n+\n static int\n cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t struct rte_pci_device *pci_dev)\n@@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \n \tdmadev->device = &pci_dev->device;\n \tdmadev->fp_obj->dev_private = dpivf;\n+\tdmadev->dev_ops = &cnxk_dmadev_ops;\n+\n+\tdmadev->fp_obj->copy = cnxk_dmadev_copy;\n+\tdmadev->fp_obj->submit = cnxk_dmadev_submit;\n+\tdmadev->fp_obj->completed = cnxk_dmadev_completed;\n+\tdmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;\n \n \trdpi = &dpivf->rdpi;\n \ndiff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h\nindex 9e0bb7b2ce..ce301a5945 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.h\n+++ b/drivers/dma/cnxk/cnxk_dmadev.h\n@@ -4,8 +4,61 @@\n #ifndef _CNXK_DMADEV_H_\n #define _CNXK_DMADEV_H_\n \n+#define DPI_MAX_POINTER\t\t15\n+#define DPI_QUEUE_STOP\t\t0x0\n+#define DPI_QUEUE_START\t\t0x1\n+#define STRM_INC(s)\t\t((s).tail = ((s).tail + 1) % (s).max_cnt)\n+#define DPI_MAX_DESC\t\tDPI_MAX_POINTER\n+\n+/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */\n+#define DPI_XTYPE_OUTBOUND (0)\n+#define DPI_XTYPE_INBOUND (1)\n+#define DPI_XTYPE_INTERNAL_ONLY (2)\n+#define DPI_XTYPE_EXTERNAL_ONLY (3)\n+#define DPI_XTYPE_MASK\t\t0x3\n+#define DPI_HDR_PT_ZBW_CA\t0x0\n+#define DPI_HDR_PT_ZBW_NC\t0x1\n+#define DPI_HDR_PT_WQP\t\t0x2\n+#define DPI_HDR_PT_WQP_NOSTATUS\t0x0\n+#define DPI_HDR_PT_WQP_STATUSCA\t0x1\n+#define DPI_HDR_PT_WQP_STATUSNC\t0x3\n+#define DPI_HDR_PT_CNT\t\t0x3\n+#define DPI_HDR_PT_MASK\t\t0x3\n+#define DPI_W0_TT_MASK\t\t0x3\n+#define DPI_W0_GRP_MASK\t\t0x3FF\n+\n+/* Set Completion data to 0xFF when request submitted,\n+ * upon successful request completion engine reset to completion status\n+ */\n+#define DPI_REQ_CDATA\t\t0xFF\n+\n+#define DPI_MIN_CMD_SIZE\t8\n+#define DPI_MAX_CMD_SIZE\t64\n+\n+struct cnxk_dpi_compl_s {\n+\tuint64_t cdata;\n+\tvoid *cb_data;\n+};\n+\n+struct cnxk_dpi_cdesc_data_s {\n+\tstruct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];\n+\tuint16_t max_cnt;\n+\tuint16_t head;\n+\tuint16_t tail;\n+};\n+\n+struct cnxk_dpi_queue_conf {\n+\tuint8_t direction;\n+\tuint8_t src_port;\n+\tuint8_t dst_port;\n+\tuint64_t comp_ptr;\n+\tstruct cnxk_dpi_cdesc_data_s c_desc;\n+};\n+\n struct cnxk_dpi_vf_s {\n \tstruct roc_dpi rdpi;\n+\tstruct cnxk_dpi_queue_conf conf;\n+\tuint32_t num_words;\n };\n \n #endif\ndiff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map\nnew file mode 100644\nindex 0000000000..4a76d1d52d\n--- /dev/null\n+++ b/drivers/dma/cnxk/version.map\n@@ -0,0 +1,3 @@\n+DPDK_21 {\n+\tlocal: *;\n+};\n", "prefixes": [ "3/4" ] }