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{
    "id": 102692,
    "url": "https://patches.dpdk.org/api/patches/102692/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211022170354.13503-10-roy.fan.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211022170354.13503-10-roy.fan.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211022170354.13503-10-roy.fan.zhang@intel.com",
    "date": "2021-10-22T17:03:54",
    "name": "[v4,9/9] crypto/qat: add gen specific implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "eabe4c9aa3a57490358017ffd0fb70fb93936c7d",
    "submitter": {
        "id": 304,
        "url": "https://patches.dpdk.org/api/people/304/?format=api",
        "name": "Fan Zhang",
        "email": "roy.fan.zhang@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "https://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211022170354.13503-10-roy.fan.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 19924,
            "url": "https://patches.dpdk.org/api/series/19924/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19924",
            "date": "2021-10-22T17:03:45",
            "name": "drivers/qat: isolate implementations of qat generations",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/19924/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/102692/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/102692/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A12BA0C43;\n\tFri, 22 Oct 2021 19:05:08 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C773C4115E;\n\tFri, 22 Oct 2021 19:04:40 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 9D05C41144\n for <dev@dpdk.org>; Fri, 22 Oct 2021 19:04:14 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Oct 2021 10:04:14 -0700",
            "from silpixa00400885.ir.intel.com ([10.243.23.122])\n by FMSMGA003.fm.intel.com with ESMTP; 22 Oct 2021 10:04:12 -0700"
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10145\"; a=\"315546624\"",
            "E=Sophos;i=\"5.87,173,1631602800\"; d=\"scan'208\";a=\"315546624\"",
            "E=Sophos;i=\"5.87,173,1631602800\"; d=\"scan'208\";a=\"569279824\""
        ],
        "X-ExtLoop1": "1",
        "From": "Fan Zhang <roy.fan.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, Fan Zhang <roy.fan.zhang@intel.com>,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>, Kai Ji <kai.ji@intel.com>",
        "Date": "Fri, 22 Oct 2021 18:03:54 +0100",
        "Message-Id": "<20211022170354.13503-10-roy.fan.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20211022170354.13503-1-roy.fan.zhang@intel.com>",
        "References": "<20211014161137.1405168-1-roy.fan.zhang@intel.com>\n <20211022170354.13503-1-roy.fan.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [dpdk-dev v4 9/9] crypto/qat: add gen specific\n implementation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch replaces the mixed QAT symmetric and asymmetric\nsupport implementation by separate files with shared or\nindividual implementation for specific QAT generation.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/meson.build               |   7 +-\n drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |  76 +++++\n drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 224 +++++++++++++++\n drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 164 +++++++++++\n drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 124 ++++++++\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  36 +++\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    | 283 +++++++++++++++++++\n drivers/crypto/qat/qat_crypto.h              |   3 -\n 8 files changed, 913 insertions(+), 4 deletions(-)\n create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c",
    "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 29fd0168ea..ce9959d103 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -71,7 +71,12 @@ endif\n \n if qat_crypto\n     foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',\n-            'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']\n+            'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',\n+\t    'dev/qat_sym_pmd_gen1.c',\n+            'dev/qat_asym_pmd_gen1.c',\n+            'dev/qat_crypto_pmd_gen2.c',\n+            'dev/qat_crypto_pmd_gen3.c',\n+            'dev/qat_crypto_pmd_gen4.c']\n         sources += files(join_paths(qat_crypto_relpath, f))\n     endforeach\n     deps += ['security']\ndiff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\nnew file mode 100644\nindex 0000000000..9ed1f21d9d\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c\n@@ -0,0 +1,76 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+#include \"qat_pke_functionality_arrays.h\"\n+\n+struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_cryptodev_config,\n+\t.dev_start\t\t= qat_cryptodev_start,\n+\t.dev_stop\t\t= qat_cryptodev_stop,\n+\t.dev_close\t\t= qat_cryptodev_close,\n+\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n+\n+\t.stats_get\t\t= qat_cryptodev_stats_get,\n+\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n+\t.queue_pair_setup\t= qat_cryptodev_qp_setup,\n+\t.queue_pair_release\t= qat_cryptodev_qp_release,\n+\n+\t/* Crypto related operations */\n+\t.asym_session_get_size\t= qat_asym_session_get_private_size,\n+\t.asym_session_configure\t= qat_asym_session_configure,\n+\t.asym_session_clear\t= qat_asym_session_clear\n+};\n+\n+static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {\n+\tQAT_ASYM_CAP(MODEX,\n+\t\t0, 1, 512, 1),\n+\tQAT_ASYM_CAP(MODINV,\n+\t\t0, 1, 512, 1),\n+\tQAT_ASYM_CAP(RSA,\n+\t\t\t((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n+\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |\n+\t\t\t(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |\n+\t\t\t(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),\n+\t\t\t64, 512, 64),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+\n+struct qat_capabilities_info\n+qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_capabilities_info capa_info;\n+\tcapa_info.data = qat_asym_crypto_caps_gen1;\n+\tcapa_info.size = sizeof(qat_asym_crypto_caps_gen1);\n+\treturn capa_info;\n+}\n+\n+uint64_t\n+qat_asym_crypto_feature_flags_get_gen1(\n+\tstruct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tuint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |\n+\t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\tRTE_CRYPTODEV_FF_ASYM_SESSIONLESS |\n+\t\t\tRTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |\n+\t\t\tRTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;\n+\n+\treturn feature_flags;\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen1_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =\n+\t\t\t&qat_asym_crypto_ops_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN1].get_capabilities =\n+\t\t\tqat_asym_crypto_cap_get_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN1].get_feature_flags =\n+\t\t\tqat_asym_crypto_feature_flags_get_gen1;\n+}\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\nnew file mode 100644\nindex 0000000000..b4ec440e05\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n@@ -0,0 +1,224 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen2[] = {\n+\tQAT_SYM_PLAIN_AUTH_CAP(SHA1,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 1, 20, 1)),\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(AES_CCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),\n+\t\tCAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),\n+\tQAT_SYM_AUTH_CAP(AES_GMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AUTH_CAP(AES_CMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),\n+\t\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA1_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(MD5_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_XCBC_MAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SNOW3G_UIA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(KASUMI_F9,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_XTS,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(SNOW3G_UEA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(KASUMI_F8,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CTR,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(ZUC_EEA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(ZUC_EIA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static int\n+qat_sym_crypto_qp_setup_gen2(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\tconst struct rte_cryptodev_qp_conf *qp_conf, int socket_id)\n+{\n+\tstruct qat_cryptodev_private *qat_sym_private = dev->data->dev_private;\n+\tstruct qat_qp *qp;\n+\tint ret;\n+\n+\tif (qat_cryptodev_qp_setup(dev, qp_id, qp_conf, socket_id)) {\n+\t\tQAT_LOG(DEBUG, \"QAT qp setup failed\");\n+\t\treturn -1;\n+\t}\n+\n+\tqp = qat_sym_private->qat_dev->qps_in_use[QAT_SERVICE_SYMMETRIC][qp_id];\n+\tret = qat_cq_get_fw_version(qp);\n+\tif (ret < 0) {\n+\t\tqat_cryptodev_qp_release(dev, qp_id);\n+\t\treturn ret;\n+\t}\n+\n+\tif (ret != 0)\n+\t\tQAT_LOG(DEBUG, \"QAT firmware version: %d.%d.%d\",\n+\t\t\t\t(ret >> 24) & 0xff,\n+\t\t\t\t(ret >> 16) & 0xff,\n+\t\t\t\t(ret >> 8) & 0xff);\n+\telse\n+\t\tQAT_LOG(DEBUG, \"unknown QAT firmware version\");\n+\n+\t/* set capabilities based on the fw version */\n+\tqat_sym_private->internal_capabilities = QAT_SYM_CAP_VALID |\n+\t\t\t((ret >= MIXED_CRYPTO_MIN_FW_VER) ?\n+\t\t\t\t\tQAT_SYM_CAP_MIXED_CRYPTO : 0);\n+\treturn 0;\n+}\n+\n+struct rte_cryptodev_ops qat_sym_crypto_ops_gen2 = {\n+\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_cryptodev_config,\n+\t.dev_start\t\t= qat_cryptodev_start,\n+\t.dev_stop\t\t= qat_cryptodev_stop,\n+\t.dev_close\t\t= qat_cryptodev_close,\n+\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n+\n+\t.stats_get\t\t= qat_cryptodev_stats_get,\n+\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n+\t.queue_pair_setup\t= qat_sym_crypto_qp_setup_gen2,\n+\t.queue_pair_release\t= qat_cryptodev_qp_release,\n+\n+\t/* Crypto related operations */\n+\t.sym_session_get_size\t= qat_sym_session_get_private_size,\n+\t.sym_session_configure\t= qat_sym_session_configure,\n+\t.sym_session_clear\t= qat_sym_session_clear,\n+\n+\t/* Raw data-path API related operations */\n+\t.sym_get_raw_dp_ctx_size = qat_sym_get_dp_ctx_size,\n+\t.sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx,\n+};\n+\n+static struct qat_capabilities_info\n+qat_sym_crypto_cap_get_gen2(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_capabilities_info capa_info;\n+\tcapa_info.data = qat_sym_crypto_caps_gen2;\n+\tcapa_info.size = sizeof(qat_sym_crypto_caps_gen2);\n+\treturn capa_info;\n+}\n+\n+RTE_INIT(qat_sym_crypto_gen2_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN2].cryptodev_ops = &qat_sym_crypto_ops_gen2;\n+\tqat_sym_gen_dev_ops[QAT_GEN2].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen2;\n+\tqat_sym_gen_dev_ops[QAT_GEN2].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+\n+#ifdef RTE_LIB_SECURITY\n+\tqat_sym_gen_dev_ops[QAT_GEN2].create_security_ctx =\n+\t\t\tqat_sym_create_security_gen1;\n+#endif\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen2_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN2].cryptodev_ops =\n+\t\t\t&qat_asym_crypto_ops_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN2].get_capabilities =\n+\t\t\tqat_asym_crypto_cap_get_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN2].get_feature_flags =\n+\t\t\tqat_asym_crypto_feature_flags_get_gen1;\n+}\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\nnew file mode 100644\nindex 0000000000..d3336cf4a1\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n@@ -0,0 +1,164 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {\n+\tQAT_SYM_PLAIN_AUTH_CAP(SHA1,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 1, 20, 1)),\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(AES_CCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),\n+\t\tCAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),\n+\tQAT_SYM_AUTH_CAP(AES_GMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AUTH_CAP(AES_CMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),\n+\t\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA1_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(MD5_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_XCBC_MAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SNOW3G_UIA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(KASUMI_F9,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_XTS,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(SNOW3G_UEA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(KASUMI_F8,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CTR,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(ZUC_EEA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(ZUC_EIA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AEAD_CAP(CHACHA20_POLY1305,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 32, 32, 0),\n+\t\tCAP_RNG(digest_size, 16, 16, 0),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static struct qat_capabilities_info\n+qat_sym_crypto_cap_get_gen3(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_capabilities_info capa_info;\n+\tcapa_info.data = qat_sym_crypto_caps_gen3;\n+\tcapa_info.size = sizeof(qat_sym_crypto_caps_gen3);\n+\treturn capa_info;\n+}\n+\n+RTE_INIT(qat_sym_crypto_gen3_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN3].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN3].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen3;\n+\tqat_sym_gen_dev_ops[QAT_GEN3].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+#ifdef RTE_LIB_SECURITY\n+\tqat_sym_gen_dev_ops[QAT_GEN3].create_security_ctx =\n+\t\t\tqat_sym_create_security_gen1;\n+#endif\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen3_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN3].cryptodev_ops = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN3].get_capabilities = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN3].get_feature_flags = NULL;\n+}\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\nnew file mode 100644\nindex 0000000000..37a58c026f\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n@@ -0,0 +1,124 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {\n+\tQAT_SYM_CIPHER_CAP(AES_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(SHA1_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_XCBC_MAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_CMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_PLAIN_AUTH_CAP(SHA1,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 1, 20, 1)),\n+\tQAT_SYM_AUTH_CAP(SHA224,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(AES_CCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),\n+\t\tCAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),\n+\tQAT_SYM_AUTH_CAP(AES_GMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(CHACHA20_POLY1305,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 32, 32, 0),\n+\t\tCAP_RNG(digest_size, 16, 16, 0),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static struct qat_capabilities_info\n+qat_sym_crypto_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_capabilities_info capa_info;\n+\tcapa_info.data = qat_sym_crypto_caps_gen4;\n+\tcapa_info.size = sizeof(qat_sym_crypto_caps_gen4);\n+\treturn capa_info;\n+}\n+\n+RTE_INIT(qat_sym_crypto_gen4_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN4].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen4;\n+\tqat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+#ifdef RTE_LIB_SECURITY\n+\tqat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx =\n+\t\t\tqat_sym_create_security_gen1;\n+#endif\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen4_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = NULL;\n+}\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nnew file mode 100644\nindex 0000000000..67a4d2cb2c\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#ifndef _QAT_CRYPTO_PMD_GENS_H_\n+#define _QAT_CRYPTO_PMD_GENS_H_\n+\n+#include <rte_cryptodev.h>\n+#include \"qat_crypto.h\"\n+#include \"qat_sym_session.h\"\n+\n+extern struct rte_cryptodev_ops qat_sym_crypto_ops_gen1;\n+extern struct rte_cryptodev_ops qat_asym_crypto_ops_gen1;\n+\n+/* -----------------GENx control path APIs ---------------- */\n+uint64_t\n+qat_sym_crypto_feature_flags_get_gen1(struct qat_pci_device *qat_dev);\n+\n+void\n+qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,\n+\t\tuint8_t hash_flag);\n+\n+struct qat_capabilities_info\n+qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev);\n+\n+uint64_t\n+qat_asym_crypto_feature_flags_get_gen1(struct qat_pci_device *qat_dev);\n+\n+#ifdef RTE_LIB_SECURITY\n+extern struct rte_security_ops security_qat_ops_gen1;\n+\n+void *\n+qat_sym_create_security_gen1(void *cryptodev);\n+#endif\n+\n+#endif\ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nnew file mode 100644\nindex 0000000000..e156f194e2\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -0,0 +1,283 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017-2021 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#ifdef RTE_LIB_SECURITY\n+#include <rte_security_driver.h>\n+#endif\n+\n+#include \"adf_transport_access_macros.h\"\n+#include \"icp_qat_fw.h\"\n+#include \"icp_qat_fw_la.h\"\n+\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_sym_session.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen1[] = {\n+\tQAT_SYM_PLAIN_AUTH_CAP(SHA1,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 1, 20, 1)),\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(AES_CCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),\n+\t\tCAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),\n+\tQAT_SYM_AUTH_CAP(AES_GMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AUTH_CAP(AES_CMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),\n+\t\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA1_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(MD5_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_XCBC_MAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SNOW3G_UIA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(KASUMI_F9,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_XTS,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(AES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(SNOW3G_UEA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(KASUMI_F8,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(3DES_CTR,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_CBC,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),\n+\tQAT_SYM_CIPHER_CAP(DES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 8),\n+\t\tCAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+struct rte_cryptodev_ops qat_sym_crypto_ops_gen1 = {\n+\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_cryptodev_config,\n+\t.dev_start\t\t= qat_cryptodev_start,\n+\t.dev_stop\t\t= qat_cryptodev_stop,\n+\t.dev_close\t\t= qat_cryptodev_close,\n+\t.dev_infos_get\t\t= qat_cryptodev_info_get,\n+\n+\t.stats_get\t\t= qat_cryptodev_stats_get,\n+\t.stats_reset\t\t= qat_cryptodev_stats_reset,\n+\t.queue_pair_setup\t= qat_cryptodev_qp_setup,\n+\t.queue_pair_release\t= qat_cryptodev_qp_release,\n+\n+\t/* Crypto related operations */\n+\t.sym_session_get_size\t= qat_sym_session_get_private_size,\n+\t.sym_session_configure\t= qat_sym_session_configure,\n+\t.sym_session_clear\t= qat_sym_session_clear,\n+\n+\t/* Raw data-path API related operations */\n+\t.sym_get_raw_dp_ctx_size = qat_sym_get_dp_ctx_size,\n+\t.sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx,\n+};\n+\n+static struct qat_capabilities_info\n+qat_sym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_capabilities_info capa_info;\n+\tcapa_info.data = qat_sym_crypto_caps_gen1;\n+\tcapa_info.size = sizeof(qat_sym_crypto_caps_gen1);\n+\treturn capa_info;\n+}\n+\n+uint64_t\n+qat_sym_crypto_feature_flags_get_gen1(\n+\tstruct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tuint64_t feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_DIGEST_ENCRYPTED |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_RAW_DP;\n+\n+\treturn feature_flags;\n+}\n+\n+#ifdef RTE_LIB_SECURITY\n+\n+#define QAT_SECURITY_SYM_CAPABILITIES\t\t\t\t\t\\\n+\t{\t/* AES DOCSIS BPI */\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\t\\\n+\t\t\t{.cipher = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_DOCSISBPI,\\\n+\t\t\t\t.block_size = 16,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 16\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 16,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n+#define QAT_SECURITY_CAPABILITIES(sym)\t\t\t\t\t\\\n+\t[0] = {\t/* DOCSIS Uplink */\t\t\t\t\t\\\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\t\\\n+\t\t.protocol = RTE_SECURITY_PROTOCOL_DOCSIS,\t\t\\\n+\t\t.docsis = {\t\t\t\t\t\t\\\n+\t\t\t.direction = RTE_SECURITY_DOCSIS_UPLINK\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.crypto_capabilities = (sym)\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t[1] = {\t/* DOCSIS Downlink */\t\t\t\t\t\\\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\t\\\n+\t\t.protocol = RTE_SECURITY_PROTOCOL_DOCSIS,\t\t\\\n+\t\t.docsis = {\t\t\t\t\t\t\\\n+\t\t\t.direction = RTE_SECURITY_DOCSIS_DOWNLINK\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.crypto_capabilities = (sym)\t\t\t\t\\\n+\t}\n+\n+static const struct rte_cryptodev_capabilities\n+\t\t\t\t\tqat_security_sym_capabilities[] = {\n+\tQAT_SECURITY_SYM_CAPABILITIES,\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static const struct rte_security_capability qat_security_capabilities_gen1[] = {\n+\tQAT_SECURITY_CAPABILITIES(qat_security_sym_capabilities),\n+\t{\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_NONE\n+\t}\n+};\n+\n+static const struct rte_security_capability *\n+qat_security_cap_get_gen1(void *dev __rte_unused)\n+{\n+\treturn qat_security_capabilities_gen1;\n+}\n+\n+struct rte_security_ops security_qat_ops_gen1 = {\n+\t\t.session_create = qat_security_session_create,\n+\t\t.session_update = NULL,\n+\t\t.session_stats_get = NULL,\n+\t\t.session_destroy = qat_security_session_destroy,\n+\t\t.set_pkt_metadata = NULL,\n+\t\t.capabilities_get = qat_security_cap_get_gen1\n+};\n+\n+void *\n+qat_sym_create_security_gen1(void *cryptodev)\n+{\n+\tstruct rte_security_ctx *security_instance;\n+\n+\tsecurity_instance = rte_malloc(NULL, sizeof(struct rte_security_ctx),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (security_instance == NULL)\n+\t\treturn NULL;\n+\n+\tsecurity_instance->device = cryptodev;\n+\tsecurity_instance->ops = &security_qat_ops_gen1;\n+\tsecurity_instance->sess_cnt = 0;\n+\n+\treturn (void *)security_instance;\n+}\n+\n+#endif\n+\n+RTE_INIT(qat_sym_crypto_gen1_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN1].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN1].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN1].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+#ifdef RTE_LIB_SECURITY\n+\tqat_sym_gen_dev_ops[QAT_GEN1].create_security_ctx =\n+\t\t\tqat_sym_create_security_gen1;\n+#endif\n+}\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 0a8afb0b31..6eaa15b975 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -6,9 +6,6 @@\n  #define _QAT_CRYPTO_H_\n \n #include <rte_cryptodev.h>\n-#ifdef RTE_LIB_SECURITY\n-#include <rte_security.h>\n-#endif\n \n #include \"qat_device.h\"\n \n",
    "prefixes": [
        "v4",
        "9/9"
    ]
}