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GET /api/patches/101210/?format=api
{ "id": 101210, "url": "https://patches.dpdk.org/api/patches/101210/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211012124554.21296-2-talshn@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211012124554.21296-2-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211012124554.21296-2-talshn@nvidia.com", "date": "2021-10-12T12:45:42", "name": "[v2,01/13] net/mlx5: fix software parsing support query", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "636fb8bad70a256d4013065e1627255f28b5f312", "submitter": { "id": 1893, "url": "https://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211012124554.21296-2-talshn@nvidia.com/mbox/", "series": [ { "id": 19558, "url": "https://patches.dpdk.org/api/series/19558/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19558", "date": "2021-10-12T12:45:41", "name": "Expand NIC offloads support on Windows", "version": 2, "mbox": "https://patches.dpdk.org/series/19558/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/101210/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/101210/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7129DA0C47;\n\tTue, 12 Oct 2021 14:46:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5B57941143;\n\tTue, 12 Oct 2021 14:46:38 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2079.outbound.protection.outlook.com [40.107.236.79])\n by mails.dpdk.org (Postfix) with ESMTP id 5E0A141135;\n Tue, 12 Oct 2021 14:46:37 +0200 (CEST)", "from DM6PR02CA0146.namprd02.prod.outlook.com (2603:10b6:5:332::13)\n by MWHPR12MB1248.namprd12.prod.outlook.com (2603:10b6:300:12::21) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.22; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <asafp@nvidia.com>, <viacheslavo@nvidia.com>, <eilong@nvidia.com>,\n <kcollins@nvidia.com>, <idanhac@nvidia.com>, <stable@dpdk.org>", "Date": "Tue, 12 Oct 2021 15:45:42 +0300", "Message-ID": "<20211012124554.21296-2-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211012124554.21296-1-talshn@nvidia.com>", "References": "<20211012124554.21296-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "9dd00dba-fb03-4922-520b-08d98d7e5299", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1248:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB1248D8F29F4D6B7FFB110FD8A4B69@MWHPR12MB1248.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1824;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Hkno35KMk8gMTqsXN8k2mdkwt61dehUyMy06/wz1LOCBBoyGho4LKDDnhF51OkuM74XMYVuj4jN3o9c7135GqT+jm7gmIhFRq16tWRMCOAynggi00O2hbqTzpMFCBRTzp5xIdnVc6mAUWsjnOyCYpuBI8qAACEh+ux2lc9ddS1VOEjm+hnaP/wYKc/kAHwyo6tXCfj6IpMLw68ybBWeTAcwkOQ8Y5+GWfDG48wgzwytVJAXph4N6Fh1e9/L0uYqVx12qYSUSnsd2xYpemLYqFqczXky3tx1I74hT1Pv6+BW/bdUX7apUi93mVSBnf0Cf3GQg/vCyQop7fH3/R4ba1E90ENnyDnVA5S0rBG1iHnFc/93D+rE6c48cBHbDzednwA1FeBZKeWhASpoQ+qtqJH8XzHD02PWQdx9ulYL/eQDhCz6VDncGGIZaw4/CMeEkx5WolCVjrcK+t8IhYyDzgxodQ9T2NQPz8ynaVXR5/bF08rY89YykFOtxt1lad4DEx9tTzeqFaJDoEP0YsWq4GiNRrOXMUtkf24jvW8XMSOTUVY9keKdiTcgUFXBoJMNuvI+3ywTZEy99D6r50qyOJJlgz4dOKUleyWfUDVadbn2l5syhocLs6O+C/a5WMVA9PXHHDY5gsaBfKwpIA/TpvtQhVVMfDYs00Yw+OUF4nC20UZCP6xbaabn5ztiKcVwKuhIFSVb6D6BdJcdqaB7Xm39PZn4WNYB+iF/PVqGAr7Q=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(36860700001)(83380400001)(54906003)(36756003)(186003)(7636003)(4326008)(316002)(1076003)(26005)(508600001)(16526019)(2616005)(8936002)(8676002)(356005)(70586007)(336012)(6916009)(2906002)(426003)(5660300002)(86362001)(6286002)(6666004)(82310400003)(70206006)(7696005)(47076005)(55016002)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Oct 2021 12:46:33.9513 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9dd00dba-fb03-4922-520b-08d98d7e5299", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT008.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1248", "Subject": "[dpdk-dev] [PATCH v2 01/13] net/mlx5: fix software parsing support\n query", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, the PMD decides if the software parsing\noffload can enable outer IPv4 checksum and tunneled\nTSO support by checking config->hw_csum and config->tso\nrespectively.\n\nThis is incorrect, the right way is to check the following\nflags returned by the mlx5dv_query_device function:\n\nMLX5DV_SW_PARSING - check general swp support.\nMLX5DV_SW_PARSING_CSUM - check swp checksum support.\nMLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.\n\nThe fix enables the offloads according to the correct\nflags returned by the kernel.\n\nFixes: e46821e9fcdc60 (\"net/mlx5: separate generic tunnel TSO from the standard one\")\nCc: stable@dpdk.org\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nTested-by: Idan Hackmon <idanhac@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 3 ++-\n drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_txq.c | 15 +++++++++------\n 4 files changed, 24 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 3746057673..a6542629c7 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1112,7 +1112,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tswp = dv_attr.sw_parsing_caps.sw_parsing_offloads;\n \tDRV_LOG(DEBUG, \"SWP support: %u\", swp);\n #endif\n-\tconfig->swp = !!swp;\n+\tconfig->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |\n+\t\tMLX5_SW_PARSING_TSO_CAP);\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n \tif (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {\n \t\tstruct mlx5dv_striding_rq_caps mprq_caps =\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h\nindex 2991d37df2..da036edb72 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_os.h\n@@ -21,4 +21,16 @@ enum {\n \n int mlx5_auxiliary_get_ifindex(const char *sf_name);\n \n+\n+enum mlx5_sw_parsing_offloads {\n+#ifdef HAVE_IBV_MLX5_MOD_SWP\n+\tMLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING,\n+\tMLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,\n+\tMLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO,\n+#else\n+\tMLX5_SW_PARSING_CAP = 0,\n+\tMLX5_SW_PARSING_CSUM_CAP = 0,\n+\tMLX5_SW_PARSING_TSO_CAP = 0,\n+#endif\n+};\n #endif /* RTE_PMD_MLX5_OS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 3581414b78..edb4f26d42 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -260,7 +260,7 @@ struct mlx5_dev_config {\n \tunsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */\n \tunsigned int lacp_by_user:1;\n \t/* Enable user to manage LACP traffic. */\n-\tunsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */\n+\tunsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */\n \tunsigned int devx:1; /* Whether devx interface is available or not. */\n \tunsigned int dest_tir:1; /* Whether advanced DR API is available. */\n \tunsigned int reclaim_mode:2; /* Memory reclaim mode. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex eb4d34ca55..8dca2b7f79 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)\n \tif (config->tx_pp)\n \t\toffloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;\n \tif (config->swp) {\n-\t\tif (config->hw_csum)\n+\t\tif (config->swp & MLX5_SW_PARSING_CSUM_CAP)\n \t\t\toffloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n-\t\tif (config->tso)\n+\t\tif (config->swp & MLX5_SW_PARSING_TSO_CAP)\n \t\t\toffloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |\n \t\t\t\t DEV_TX_OFFLOAD_UDP_TNL_TSO);\n \t}\n@@ -979,10 +979,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\ttxq_ctrl->txq.tso_en = 1;\n \t}\n \ttxq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;\n-\ttxq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |\n-\t\t\t\t DEV_TX_OFFLOAD_UDP_TNL_TSO |\n-\t\t\t\t DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &\n-\t\t\t\ttxq_ctrl->txq.offloads) && config->swp;\n+\ttxq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |\n+\t\t\t\t DEV_TX_OFFLOAD_UDP_TNL_TSO) &\n+\t\t\t\t txq_ctrl->txq.offloads) && (config->swp &\n+\t\t\t\t MLX5_SW_PARSING_TSO_CAP)) |\n+\t\t\t\t((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &\n+\t\t\t\t txq_ctrl->txq.offloads) && (config->swp &\n+\t\t\t\t MLX5_SW_PARSING_CSUM_CAP));\n }\n \n /**\n", "prefixes": [ "v2", "01/13" ] }