Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 100780,
    "url": "https://patches.dpdk.org/api/patches/100780/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211007184350.73858-13-srikanth.k@oneconvergence.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211007184350.73858-13-srikanth.k@oneconvergence.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211007184350.73858-13-srikanth.k@oneconvergence.com",
    "date": "2021-10-07T18:43:21",
    "name": "[v2,12/41] net/mlx5: add helpers for MR & HW operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "deferred",
    "archived": false,
    "hash": "f799a941b1d46164180818d9dfb33c3e53e48b98",
    "submitter": {
        "id": 2368,
        "url": "https://patches.dpdk.org/api/people/2368/?format=api",
        "name": "Srikanth Kaka",
        "email": "srikanth.k@oneconvergence.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211007184350.73858-13-srikanth.k@oneconvergence.com/mbox/",
    "series": [
        {
            "id": 19455,
            "url": "https://patches.dpdk.org/api/series/19455/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19455",
            "date": "2021-10-07T18:43:09",
            "name": "add MLX5 FreeBSD support",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/19455/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/100780/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/100780/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D145FA034F;\n\tFri,  8 Oct 2021 12:57:04 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D370B4116F;\n\tFri,  8 Oct 2021 12:56:10 +0200 (CEST)",
            "from mail-pf1-f178.google.com (mail-pf1-f178.google.com\n [209.85.210.178])\n by mails.dpdk.org (Postfix) with ESMTP id CB12E411E0\n for <dev@dpdk.org>; Thu,  7 Oct 2021 20:44:46 +0200 (CEST)",
            "by mail-pf1-f178.google.com with SMTP id u7so6048681pfg.13\n for <dev@dpdk.org>; Thu, 07 Oct 2021 11:44:46 -0700 (PDT)",
            "from srikanth-ThinkPad-T450.domain.name ([136.185.113.102])\n by smtp.gmail.com with ESMTPSA id c11sm3311586pji.38.2021.10.07.11.44.43\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 07 Oct 2021 11:44:45 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oneconvergence.com; s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=4DQccZQK3bweOQCf19XtuFwbaasousWbx7iFsMziCZI=;\n b=XQ71u3SeTxby+tfk0qEXjkFZDzeycZ0/8+vVWAeugQn4UaDrhsEScTnJWxLJzlVMDL\n qbSMn4eAb8bzH5Ld4m8l5iCxyd9cEmpSPAwx6xW4qr8cgzw5F9daUeQIPluXIhqmBGiR\n HQhlYioeK2COFR6G8XS0RWmpEO/TnslW/XrVs=",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=4DQccZQK3bweOQCf19XtuFwbaasousWbx7iFsMziCZI=;\n b=Sab/C6LLOD0v9MzeKfeo9x4Vosz2hCXi61+gCAzOzsmVbuTRbZTD7giQan4MA4/x+6\n 6jOCWQbyZscs3GRBIqYBav6qShIGfDoFLRq6rE3blVDmAJ+PVuKNNXGMvJp7LpZ5okyQ\n eteBLsGj2nHntRTL8vKSmcNu6j9QUAZQiTqf0MDDpKytzMwV8pJlihw0NGnn5LwXJXGW\n IQwqHDR86Nv2iPkPin6iwMhlPUC/g0lTCL+hr4dmo0k8SUxUQZx9uP/fn5zKGPg5Ntdk\n SaH3DsOULlla2XFO/6kz+sKlcpcMj7/2SDF2U4HASl8GGQ6i5EXaNdfRpuPDbEzy8hiY\n q6zQ==",
        "X-Gm-Message-State": "AOAM532GsLhGUP9gYG92qIYrOf8GLcfyRq7y3kMLh7C/vDjjIlf1x43V\n I4bX7fMXB+PW3r1fn8RL1rap5w==",
        "X-Google-Smtp-Source": "\n ABdhPJygXHFpCpaKYSmp4rayV88rATcDTewXweFdAaNyc0rLjDwOK/hrWZTiC2bh7OmIoDrkw51OWg==",
        "X-Received": "by 2002:a63:4344:: with SMTP id q65mr1024232pga.450.1633632285704;\n Thu, 07 Oct 2021 11:44:45 -0700 (PDT)",
        "From": "Srikanth Kaka <srikanth.k@oneconvergence.com>",
        "To": "Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Cc": "dev@dpdk.org, Vag Singh <vag.singh@oneconvergence.com>,\n Anand Thulasiram <avelu@juniper.net>,\n Srikanth Kaka <srikanth.k@oneconvergence.com>",
        "Date": "Fri,  8 Oct 2021 00:13:21 +0530",
        "Message-Id": "<20211007184350.73858-13-srikanth.k@oneconvergence.com>",
        "X-Mailer": "git-send-email 2.30.2",
        "In-Reply-To": "<20211007184350.73858-1-srikanth.k@oneconvergence.com>",
        "References": "<20211007184350.73858-1-srikanth.k@oneconvergence.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Approved-At": "Fri, 08 Oct 2021 12:55:54 +0200",
        "Subject": "[dpdk-dev] [PATCH v2 12/41] net/mlx5: add helpers for MR & HW\n operations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Given protection domain pointer, pointer to addr and length,\nregister the memory region.\n\nThis patch also defines mlx5_obj_ops.\n\nmlx5_verbs.h & mlx5_verbs.c are equivalent to their Linux\ncounterparts.\n\nSigned-off-by: Srikanth Kaka <srikanth.k@oneconvergence.com>\nSigned-off-by: Vag Singh <vag.singh@oneconvergence.com>\nSigned-off-by: Anand Thulasiram <avelu@juniper.net>\n---\n drivers/net/mlx5/freebsd/mlx5_verbs.c | 1208 +++++++++++++++++++++++++\n drivers/net/mlx5/freebsd/mlx5_verbs.h |   18 +\n 2 files changed, 1226 insertions(+)\n create mode 100644 drivers/net/mlx5/freebsd/mlx5_verbs.c\n create mode 100644 drivers/net/mlx5/freebsd/mlx5_verbs.h",
    "diff": "diff --git a/drivers/net/mlx5/freebsd/mlx5_verbs.c b/drivers/net/mlx5/freebsd/mlx5_verbs.c\nnew file mode 100644\nindex 0000000000..d4fa202ac4\n--- /dev/null\n+++ b/drivers/net/mlx5/freebsd/mlx5_verbs.c\n@@ -0,0 +1,1208 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include <stddef.h>\n+#include <errno.h>\n+#include <string.h>\n+#include <stdint.h>\n+#include <unistd.h>\n+#include <inttypes.h>\n+#include <sys/queue.h>\n+\n+#include \"mlx5_autoconf.h\"\n+\n+#include <rte_mbuf.h>\n+#include <rte_malloc.h>\n+#include <ethdev_driver.h>\n+#include <rte_common.h>\n+\n+#include <mlx5_glue.h>\n+#include <mlx5_common.h>\n+#include <mlx5_common_mr.h>\n+#include <mlx5_verbs.h>\n+#include <mlx5_rx.h>\n+#include <mlx5_tx.h>\n+#include <mlx5_utils.h>\n+#include <mlx5_malloc.h>\n+\n+/**\n+ * Register mr. Given protection domain pointer, pointer to addr and length\n+ * register the memory region.\n+ *\n+ * @param[in] pd\n+ *   Pointer to protection domain context.\n+ * @param[in] addr\n+ *   Pointer to memory start address.\n+ * @param[in] length\n+ *   Length of the memory to register.\n+ * @param[out] pmd_mr\n+ *   pmd_mr struct set with lkey, address, length and pointer to mr object\n+ *\n+ * @return\n+ *   0 on successful registration, -1 otherwise\n+ */\n+static int\n+mlx5_reg_mr(void *pd, void *addr, size_t length,\n+\t\t struct mlx5_pmd_mr *pmd_mr)\n+{\n+\treturn mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr);\n+}\n+\n+/**\n+ * Deregister mr. Given the mlx5 pmd MR - deregister the MR\n+ *\n+ * @param[in] pmd_mr\n+ *   pmd_mr struct set with lkey, address, length and pointer to mr object\n+ *\n+ */\n+static void\n+mlx5_dereg_mr(struct mlx5_pmd_mr *pmd_mr)\n+{\n+\tmlx5_common_verbs_dereg_mr(pmd_mr);\n+}\n+\n+/* verbs operations. */\n+const struct mlx5_mr_ops mlx5_mr_verbs_ops = {\n+\t.reg_mr = mlx5_reg_mr,\n+\t.dereg_mr = mlx5_dereg_mr,\n+};\n+\n+/**\n+ * Modify Rx WQ vlan stripping offload\n+ *\n+ * @param rxq_obj\n+ *   Rx queue object.\n+ *\n+ * @return 0 on success, non-0 otherwise\n+ */\n+static int\n+mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)\n+{\n+\tuint16_t vlan_offloads =\n+\t\t(on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) |\n+\t\t0;\n+\tstruct ibv_wq_attr mod;\n+\tmod = (struct ibv_wq_attr){\n+\t\t.attr_mask = IBV_WQ_ATTR_FLAGS,\n+\t\t.flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING,\n+\t\t.flags = vlan_offloads,\n+\t};\n+\n+\treturn mlx5_glue->modify_wq(rxq_obj->wq, &mod);\n+}\n+\n+/**\n+ * Modifies the attributes for the specified WQ.\n+ *\n+ * @param rxq_obj\n+ *   Verbs Rx queue object.\n+ * @param type\n+ *   Type of change queue state.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_ibv_modify_wq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)\n+{\n+\tstruct ibv_wq_attr mod = {\n+\t\t.attr_mask = IBV_WQ_ATTR_STATE,\n+\t\t.wq_state = (enum ibv_wq_state)type,\n+\t};\n+\n+\treturn mlx5_glue->modify_wq(rxq_obj->wq, &mod);\n+}\n+\n+/**\n+ * Modify QP using Verbs API.\n+ *\n+ * @param txq_obj\n+ *   Verbs Tx queue object.\n+ * @param type\n+ *   Type of change queue state.\n+ * @param dev_port\n+ *   IB device port number.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,\n+\t\t   uint8_t dev_port)\n+{\n+\tstruct ibv_qp_attr mod = {\n+\t\t.qp_state = IBV_QPS_RESET,\n+\t\t.port_num = dev_port,\n+\t};\n+\tint attr_mask = (IBV_QP_STATE | IBV_QP_PORT);\n+\tint ret;\n+\n+\tif (type != MLX5_TXQ_MOD_RST2RDY) {\n+\t\tret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Cannot change Tx QP state to RESET %s\",\n+\t\t\t\tstrerror(errno));\n+\t\t\trte_errno = errno;\n+\t\t\treturn ret;\n+\t\t}\n+\t\tif (type == MLX5_TXQ_MOD_RDY2RST)\n+\t\t\treturn 0;\n+\t}\n+\tif (type == MLX5_TXQ_MOD_ERR2RDY)\n+\t\tattr_mask = IBV_QP_STATE;\n+\tmod.qp_state = IBV_QPS_INIT;\n+\tret = mlx5_glue->modify_qp(obj->qp, &mod, attr_mask);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Cannot change Tx QP state to INIT %s\",\n+\t\t\tstrerror(errno));\n+\t\trte_errno = errno;\n+\t\treturn ret;\n+\t}\n+\tmod.qp_state = IBV_QPS_RTR;\n+\tret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Cannot change Tx QP state to RTR %s\",\n+\t\t\tstrerror(errno));\n+\t\trte_errno = errno;\n+\t\treturn ret;\n+\t}\n+\tmod.qp_state = IBV_QPS_RTS;\n+\tret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Cannot change Tx QP state to RTS %s\",\n+\t\t\tstrerror(errno));\n+\t\trte_errno = errno;\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * Create a CQ Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Rx queue array.\n+ *\n+ * @return\n+ *   The Verbs CQ object initialized, NULL otherwise and rte_errno is set.\n+ */\n+static struct ibv_cq *\n+mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;\n+\tunsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);\n+\tstruct {\n+\t\tstruct ibv_cq_init_attr_ex ibv;\n+\t\tstruct mlx5dv_cq_init_attr mlx5;\n+\t} cq_attr;\n+\n+\tcq_attr.ibv = (struct ibv_cq_init_attr_ex){\n+\t\t.cqe = cqe_n,\n+\t\t.channel = rxq_obj->ibv_channel,\n+\t\t.comp_mask = 0,\n+\t};\n+\tcq_attr.mlx5 = (struct mlx5dv_cq_init_attr){\n+\t\t.comp_mask = 0,\n+\t};\n+\tif (priv->config.cqe_comp && !rxq_data->hw_timestamp) {\n+\t\tcq_attr.mlx5.comp_mask |=\n+\t\t\t\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;\n+\t\trxq_data->byte_mask = UINT32_MAX;\n+#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n+\t\tif (mlx5_rxq_mprq_enabled(rxq_data)) {\n+\t\t\tcq_attr.mlx5.cqe_comp_res_format =\n+\t\t\t\t\tMLX5DV_CQE_RES_FORMAT_CSUM_STRIDX;\n+\t\t\trxq_data->mcqe_format =\n+\t\t\t\t\tMLX5_CQE_RESP_FORMAT_CSUM_STRIDX;\n+\t\t} else {\n+\t\t\tcq_attr.mlx5.cqe_comp_res_format =\n+\t\t\t\t\tMLX5DV_CQE_RES_FORMAT_HASH;\n+\t\t\trxq_data->mcqe_format =\n+\t\t\t\t\tMLX5_CQE_RESP_FORMAT_HASH;\n+\t\t}\n+#else\n+\t\tcq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;\n+\t\trxq_data->mcqe_format = MLX5_CQE_RESP_FORMAT_HASH;\n+#endif\n+\t\t/*\n+\t\t * For vectorized Rx, it must not be doubled in order to\n+\t\t * make cq_ci and rq_ci aligned.\n+\t\t */\n+\t\tif (mlx5_rxq_check_vec_support(rxq_data) < 0)\n+\t\t\tcq_attr.ibv.cqe *= 2;\n+\t} else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {\n+\t\tDRV_LOG(DEBUG,\n+\t\t\t\"Port %u Rx CQE compression is disabled for HW\"\n+\t\t\t\" timestamp.\",\n+\t\t\tdev->data->port_id);\n+\t}\n+#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n+\tif (RTE_CACHE_LINE_SIZE == 128) {\n+\t\tcq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;\n+\t\tcq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;\n+\t}\n+#endif\n+\treturn mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,\n+\t\t\t\t\t\t\t      &cq_attr.ibv,\n+\t\t\t\t\t\t\t      &cq_attr.mlx5));\n+}\n+\n+/**\n+ * Create a WQ Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Rx queue array.\n+ *\n+ * @return\n+ *   The Verbs WQ object initialized, NULL otherwise and rte_errno is set.\n+ */\n+static struct ibv_wq *\n+mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;\n+\tunsigned int wqe_n = 1 << rxq_data->elts_n;\n+\tstruct {\n+\t\tstruct ibv_wq_init_attr ibv;\n+#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n+\t\tstruct mlx5dv_wq_init_attr mlx5;\n+#endif\n+\t} wq_attr;\n+\n+\twq_attr.ibv = (struct ibv_wq_init_attr){\n+\t\t.wq_context = NULL, /* Could be useful in the future. */\n+\t\t.wq_type = IBV_WQT_RQ,\n+\t\t/* Max number of outstanding WRs. */\n+\t\t.max_wr = wqe_n >> rxq_data->sges_n,\n+\t\t/* Max number of scatter/gather elements in a WR. */\n+\t\t.max_sge = 1 << rxq_data->sges_n,\n+\t\t.pd = priv->sh->pd,\n+\t\t.cq = rxq_obj->ibv_cq,\n+\t\t.comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,\n+\t\t.create_flags = (rxq_data->vlan_strip ?\n+\t\t\t\t IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),\n+\t};\n+\t/* By default, FCS (CRC) is stripped by hardware. */\n+\tif (rxq_data->crc_present) {\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+\t}\n+\tif (priv->config.hw_padding) {\n+#if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+#elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+#endif\n+\t}\n+#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n+\twq_attr.mlx5 = (struct mlx5dv_wq_init_attr){\n+\t\t.comp_mask = 0,\n+\t};\n+\tif (mlx5_rxq_mprq_enabled(rxq_data)) {\n+\t\tstruct mlx5dv_striding_rq_init_attr *mprq_attr =\n+\t\t\t\t\t\t&wq_attr.mlx5.striding_rq_attrs;\n+\n+\t\twq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;\n+\t\t*mprq_attr = (struct mlx5dv_striding_rq_init_attr){\n+\t\t\t.single_stride_log_num_of_bytes = rxq_data->strd_sz_n,\n+\t\t\t.single_wqe_log_num_of_strides = rxq_data->strd_num_n,\n+\t\t\t.two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,\n+\t\t};\n+\t}\n+\trxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,\n+\t\t\t\t\t      &wq_attr.mlx5);\n+#else\n+\trxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);\n+#endif\n+\tif (rxq_obj->wq) {\n+\t\t/*\n+\t\t * Make sure number of WRs*SGEs match expectations since a queue\n+\t\t * cannot allocate more than \"desc\" buffers.\n+\t\t */\n+\t\tif (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||\n+\t\t    wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Port %u Rx queue %u requested %u*%u but got\"\n+\t\t\t\t\" %u*%u WRs*SGEs.\",\n+\t\t\t\tdev->data->port_id, idx,\n+\t\t\t\twqe_n >> rxq_data->sges_n,\n+\t\t\t\t(1 << rxq_data->sges_n),\n+\t\t\t\twq_attr.ibv.max_wr, wq_attr.ibv.max_sge);\n+\t\t\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n+\t\t\trxq_obj->wq = NULL;\n+\t\t\trte_errno = EINVAL;\n+\t\t}\n+\t}\n+\treturn rxq_obj->wq;\n+}\n+\n+/**\n+ * Create the Rx queue Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Rx queue array.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n+\tstruct mlx5dv_cq cq_info;\n+\tstruct mlx5dv_rwq rwq;\n+\tint ret = 0;\n+\tstruct mlx5dv_obj obj;\n+\n+\tMLX5_ASSERT(rxq_data);\n+\tMLX5_ASSERT(tmpl);\n+\ttmpl->rxq_ctrl = rxq_ctrl;\n+\tif (rxq_ctrl->irq) {\n+\t\ttmpl->ibv_channel =\n+\t\t\t\tmlx5_glue->create_comp_channel(priv->sh->ctx);\n+\t\tif (!tmpl->ibv_channel) {\n+\t\t\tDRV_LOG(ERR, \"Port %u: comp channel creation failure.\",\n+\t\t\t\tdev->data->port_id);\n+\t\t\trte_errno = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\ttmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd;\n+\t}\n+\t/* Create CQ using Verbs API. */\n+\ttmpl->ibv_cq = mlx5_rxq_ibv_cq_create(dev, idx);\n+\tif (!tmpl->ibv_cq) {\n+\t\tDRV_LOG(ERR, \"Port %u Rx queue %u CQ creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tobj.cq.in = tmpl->ibv_cq;\n+\tobj.cq.out = &cq_info;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);\n+\tif (ret) {\n+\t\trte_errno = ret;\n+\t\tgoto error;\n+\t}\n+\tif (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Port %u wrong MLX5_CQE_SIZE environment \"\n+\t\t\t\"variable value: it should be set to %u.\",\n+\t\t\tdev->data->port_id, RTE_CACHE_LINE_SIZE);\n+\t\trte_errno = EINVAL;\n+\t\tgoto error;\n+\t}\n+\t/* Fill the rings. */\n+\trxq_data->cqe_n = log2above(cq_info.cqe_cnt);\n+\trxq_data->cq_db = cq_info.dbrec;\n+\trxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;\n+\trxq_data->cq_uar = cq_info.cq_uar;\n+\trxq_data->cqn = cq_info.cqn;\n+\t/* Create WQ (RQ) using Verbs API. */\n+\ttmpl->wq = mlx5_rxq_ibv_wq_create(dev, idx);\n+\tif (!tmpl->wq) {\n+\t\tDRV_LOG(ERR, \"Port %u Rx queue %u WQ creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\t/* Change queue state to ready. */\n+\tret = mlx5_ibv_modify_wq(tmpl, IBV_WQS_RDY);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = ret;\n+\t\tgoto error;\n+\t}\n+\tobj.rwq.in = tmpl->wq;\n+\tobj.rwq.out = &rwq;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);\n+\tif (ret) {\n+\t\trte_errno = ret;\n+\t\tgoto error;\n+\t}\n+\trxq_data->wqes = rwq.buf;\n+\trxq_data->rq_db = rwq.dbrec;\n+\trxq_data->cq_arm_sn = 0;\n+\tmlx5_rxq_initialize(rxq_data);\n+\trxq_data->cq_ci = 0;\n+\tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n+\trxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;\n+\treturn 0;\n+error:\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (tmpl->wq)\n+\t\tclaim_zero(mlx5_glue->destroy_wq(tmpl->wq));\n+\tif (tmpl->ibv_cq)\n+\t\tclaim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));\n+\tif (tmpl->ibv_channel)\n+\t\tclaim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));\n+\trte_errno = ret; /* Restore rte_errno. */\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Release an Rx verbs queue object.\n+ *\n+ * @param rxq_obj\n+ *   Verbs Rx queue object.\n+ */\n+static void\n+mlx5_rxq_ibv_obj_release(struct mlx5_rxq_obj *rxq_obj)\n+{\n+\tMLX5_ASSERT(rxq_obj);\n+\tMLX5_ASSERT(rxq_obj->wq);\n+\tMLX5_ASSERT(rxq_obj->ibv_cq);\n+\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n+\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));\n+\tif (rxq_obj->ibv_channel)\n+\t\tclaim_zero(mlx5_glue->destroy_comp_channel\n+\t\t\t\t\t\t\t(rxq_obj->ibv_channel));\n+}\n+\n+/**\n+ * Get event for an Rx verbs queue object.\n+ *\n+ * @param rxq_obj\n+ *   Verbs Rx queue object.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj)\n+{\n+\tstruct ibv_cq *ev_cq;\n+\tvoid *ev_ctx;\n+\tint ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel,\n+\t\t\t\t\t  &ev_cq, &ev_ctx);\n+\n+\tif (ret < 0 || ev_cq != rxq_obj->ibv_cq)\n+\t\tgoto exit;\n+\tmlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);\n+\treturn 0;\n+exit:\n+\tif (ret < 0)\n+\t\trte_errno = errno;\n+\telse\n+\t\trte_errno = EINVAL;\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Creates a receive work queue as a filed of indirection table.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param log_n\n+ *   Log of number of queues in the array.\n+ * @param ind_tbl\n+ *   Verbs indirection table object.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,\n+\t\t       struct mlx5_ind_table_obj *ind_tbl)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct ibv_wq *wq[1 << log_n];\n+\tunsigned int i, j;\n+\n+\tMLX5_ASSERT(ind_tbl);\n+\tfor (i = 0; i != ind_tbl->queues_n; ++i) {\n+\t\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\t\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n+\n+\t\twq[i] = rxq_ctrl->obj->wq;\n+\t}\n+\tMLX5_ASSERT(i > 0);\n+\t/* Finalise indirection table. */\n+\tfor (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)\n+\t\twq[i] = wq[j];\n+\tind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx,\n+\t\t\t\t\t&(struct ibv_rwq_ind_table_init_attr){\n+\t\t\t\t\t\t.log_ind_tbl_size = log_n,\n+\t\t\t\t\t\t.ind_tbl = wq,\n+\t\t\t\t\t\t.comp_mask = 0,\n+\t\t\t\t\t});\n+\tif (!ind_tbl->ind_table) {\n+\t\trte_errno = errno;\n+\t\treturn -rte_errno;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * Destroys the specified Indirection Table.\n+ *\n+ * @param ind_table\n+ *   Indirection table to release.\n+ */\n+static void\n+mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)\n+{\n+\tclaim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));\n+}\n+\n+/**\n+ * Create an Rx Hash queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param hrxq\n+ *   Pointer to Rx Hash queue.\n+ * @param tunnel\n+ *   Tunnel type.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n+\t\t  int tunnel __rte_unused)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct ibv_qp *qp = NULL;\n+\tstruct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;\n+\tconst uint8_t *rss_key = hrxq->rss_key;\n+\tuint64_t hash_fields = hrxq->hash_fields;\n+\tint err;\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\tstruct mlx5dv_qp_init_attr qp_init_attr;\n+\n+\tmemset(&qp_init_attr, 0, sizeof(qp_init_attr));\n+\tif (tunnel) {\n+\t\tqp_init_attr.comp_mask =\n+\t\t\t\t       MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n+\t\tqp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;\n+\t}\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tif (dev->data->dev_conf.lpbk_mode) {\n+\t\t/* Allow packet sent from NIC loop back w/o source MAC check. */\n+\t\tqp_init_attr.comp_mask |=\n+\t\t\t\tMLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n+\t\tqp_init_attr.create_flags |=\n+\t\t\t\tMLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;\n+\t}\n+#endif\n+\tqp = mlx5_glue->dv_create_qp\n+\t\t\t(priv->sh->ctx,\n+\t\t\t &(struct ibv_qp_init_attr_ex){\n+\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t\t.comp_mask =\n+\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n+\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n+\t\t\t\t\t.rx_hash_function =\n+\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n+\t\t\t\t\t.rx_hash_key_len = hrxq->rss_key_len,\n+\t\t\t\t\t.rx_hash_key =\n+\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n+\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n+\t\t\t\t},\n+\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n+\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t  },\n+\t\t\t  &qp_init_attr);\n+#else\n+\tqp = mlx5_glue->create_qp_ex\n+\t\t\t(priv->sh->ctx,\n+\t\t\t &(struct ibv_qp_init_attr_ex){\n+\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t\t.comp_mask =\n+\t\t\t\t\tIBV_QP_INIT_ATTR_PD |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_IND_TABLE |\n+\t\t\t\t\tIBV_QP_INIT_ATTR_RX_HASH,\n+\t\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n+\t\t\t\t\t.rx_hash_function =\n+\t\t\t\t\t\tIBV_RX_HASH_FUNC_TOEPLITZ,\n+\t\t\t\t\t.rx_hash_key_len = hrxq->rss_key_len,\n+\t\t\t\t\t.rx_hash_key =\n+\t\t\t\t\t\t(void *)(uintptr_t)rss_key,\n+\t\t\t\t\t.rx_hash_fields_mask = hash_fields,\n+\t\t\t\t},\n+\t\t\t\t.rwq_ind_tbl = ind_tbl->ind_table,\n+\t\t\t\t.pd = priv->sh->pd,\n+\t\t\t });\n+#endif\n+\tif (!qp) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\thrxq->qp = qp;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\thrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);\n+\tif (!hrxq->action) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+#endif\n+\treturn 0;\n+error:\n+\terr = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (qp)\n+\t\tclaim_zero(mlx5_glue->destroy_qp(qp));\n+\trte_errno = err; /* Restore rte_errno. */\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Destroy a Verbs queue pair.\n+ *\n+ * @param hrxq\n+ *   Hash Rx queue to release its qp.\n+ */\n+static void\n+mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)\n+{\n+\tclaim_zero(mlx5_glue->destroy_qp(hrxq->qp));\n+}\n+\n+/**\n+ * Release a drop Rx queue Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ */\n+static void\n+mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;\n+\n+\tif (rxq->wq)\n+\t\tclaim_zero(mlx5_glue->destroy_wq(rxq->wq));\n+\tif (rxq->ibv_cq)\n+\t\tclaim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));\n+\tmlx5_free(rxq);\n+\tpriv->drop_queue.rxq = NULL;\n+}\n+\n+/**\n+ * Create a drop Rx queue Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct ibv_context *ctx = priv->sh->ctx;\n+\tstruct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;\n+\n+\tif (rxq)\n+\t\treturn 0;\n+\trxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);\n+\tif (!rxq) {\n+\t\tDRV_LOG(DEBUG, \"Port %u cannot allocate drop Rx queue memory.\",\n+\t\t      dev->data->port_id);\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->drop_queue.rxq = rxq;\n+\trxq->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);\n+\tif (!rxq->ibv_cq) {\n+\t\tDRV_LOG(DEBUG, \"Port %u cannot allocate CQ for drop queue.\",\n+\t\t      dev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\trxq->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){\n+\t\t\t\t\t\t    .wq_type = IBV_WQT_RQ,\n+\t\t\t\t\t\t    .max_wr = 1,\n+\t\t\t\t\t\t    .max_sge = 1,\n+\t\t\t\t\t\t    .pd = priv->sh->pd,\n+\t\t\t\t\t\t    .cq = rxq->ibv_cq,\n+\t\t\t\t\t      });\n+\tif (!rxq->wq) {\n+\t\tDRV_LOG(DEBUG, \"Port %u cannot allocate WQ for drop queue.\",\n+\t\t      dev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tpriv->drop_queue.rxq = rxq;\n+\treturn 0;\n+error:\n+\tmlx5_rxq_ibv_obj_drop_release(dev);\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Create a Verbs drop action for Rx Hash queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;\n+\tstruct ibv_rwq_ind_table *ind_tbl = NULL;\n+\tstruct mlx5_rxq_obj *rxq;\n+\tint ret;\n+\n+\tMLX5_ASSERT(hrxq && hrxq->ind_table);\n+\tret = mlx5_rxq_ibv_obj_drop_create(dev);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\trxq = priv->drop_queue.rxq;\n+\tind_tbl = mlx5_glue->create_rwq_ind_table\n+\t\t\t\t(priv->sh->ctx,\n+\t\t\t\t &(struct ibv_rwq_ind_table_init_attr){\n+\t\t\t\t\t.log_ind_tbl_size = 0,\n+\t\t\t\t\t.ind_tbl = (struct ibv_wq **)&rxq->wq,\n+\t\t\t\t\t.comp_mask = 0,\n+\t\t\t\t });\n+\tif (!ind_tbl) {\n+\t\tDRV_LOG(DEBUG, \"Port %u\"\n+\t\t\t\" cannot allocate indirection table for drop queue.\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\thrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx,\n+\t\t &(struct ibv_qp_init_attr_ex){\n+\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t.comp_mask = IBV_QP_INIT_ATTR_PD |\n+\t\t\t\t     IBV_QP_INIT_ATTR_IND_TABLE |\n+\t\t\t\t     IBV_QP_INIT_ATTR_RX_HASH,\n+\t\t\t.rx_hash_conf = (struct ibv_rx_hash_conf){\n+\t\t\t\t.rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,\n+\t\t\t\t.rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,\n+\t\t\t\t.rx_hash_key = rss_hash_default_key,\n+\t\t\t\t.rx_hash_fields_mask = 0,\n+\t\t\t\t},\n+\t\t\t.rwq_ind_tbl = ind_tbl,\n+\t\t\t.pd = priv->sh->pd\n+\t\t });\n+\tif (!hrxq->qp) {\n+\t\tDRV_LOG(DEBUG, \"Port %u cannot allocate QP for drop queue.\",\n+\t\t      dev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\thrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);\n+\tif (!hrxq->action) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+#endif\n+\thrxq->ind_table->ind_table = ind_tbl;\n+\treturn 0;\n+error:\n+\tif (hrxq->qp)\n+\t\tclaim_zero(mlx5_glue->destroy_qp(hrxq->qp));\n+\tif (ind_tbl)\n+\t\tclaim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));\n+\tif (priv->drop_queue.rxq)\n+\t\tmlx5_rxq_ibv_obj_drop_release(dev);\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Release a drop hash Rx queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ */\n+static void\n+mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;\n+\tstruct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table;\n+\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tclaim_zero(mlx5_glue->destroy_flow_action(hrxq->action));\n+#endif\n+\tclaim_zero(mlx5_glue->destroy_qp(hrxq->qp));\n+\tclaim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));\n+\tmlx5_rxq_ibv_obj_drop_release(dev);\n+}\n+\n+/**\n+ * Create a QP Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Tx queue array.\n+ *\n+ * @return\n+ *   The QP Verbs object, NULL otherwise and rte_errno is set.\n+ */\n+static struct ibv_qp *\n+mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n+\tstruct ibv_qp *qp_obj = NULL;\n+\tstruct ibv_qp_init_attr_ex qp_attr = { 0 };\n+\tconst int desc = 1 << txq_data->elts_n;\n+\n+\tMLX5_ASSERT(txq_ctrl->obj->cq);\n+\t/* CQ to be associated with the send queue. */\n+\tqp_attr.send_cq = txq_ctrl->obj->cq;\n+\t/* CQ to be associated with the receive queue. */\n+\tqp_attr.recv_cq = txq_ctrl->obj->cq;\n+\t/* Max number of outstanding WRs. */\n+\tqp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ?\n+\t\t\t\t   priv->sh->device_attr.max_qp_wr : desc);\n+\t/*\n+\t * Max number of scatter/gather elements in a WR, must be 1 to prevent\n+\t * libmlx5 from trying to affect must be 1 to prevent libmlx5 from\n+\t * trying to affect too much memory. TX gather is not impacted by the\n+\t * device_attr.max_sge limit and will still work properly.\n+\t */\n+\tqp_attr.cap.max_send_sge = 1;\n+\tqp_attr.qp_type = IBV_QPT_RAW_PACKET,\n+\t/* Do *NOT* enable this, completions events are managed per Tx burst. */\n+\tqp_attr.sq_sig_all = 0;\n+\tqp_attr.pd = priv->sh->pd;\n+\tqp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;\n+\tif (txq_data->inlen_send)\n+\t\tqp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;\n+\tif (txq_data->tso_en) {\n+\t\tqp_attr.max_tso_header = txq_ctrl->max_tso_header;\n+\t\tqp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;\n+\t}\n+\tqp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr);\n+\tif (qp_obj == NULL) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u QP creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = errno;\n+\t}\n+\treturn qp_obj;\n+}\n+\n+/**\n+ * Create the Tx queue Verbs object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Tx queue array.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n+\tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n+\tunsigned int cqe_n;\n+\tstruct mlx5dv_qp qp;\n+\tstruct mlx5dv_cq cq_info;\n+\tstruct mlx5dv_obj obj;\n+\tconst int desc = 1 << txq_data->elts_n;\n+\tint ret = 0;\n+\n+\tMLX5_ASSERT(txq_data);\n+\tMLX5_ASSERT(txq_obj);\n+\ttxq_obj->txq_ctrl = txq_ctrl;\n+\tif (mlx5_getenv_int(\"MLX5_ENABLE_CQE_COMPRESSION\")) {\n+\t\tDRV_LOG(ERR, \"Port %u MLX5_ENABLE_CQE_COMPRESSION \"\n+\t\t\t\"must never be set.\", dev->data->port_id);\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tcqe_n = desc / MLX5_TX_COMP_THRESH +\n+\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n+\ttxq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);\n+\tif (txq_obj->cq == NULL) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\ttxq_obj->qp = mlx5_txq_ibv_qp_create(dev, idx);\n+\tif (txq_obj->qp == NULL) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tret = mlx5_ibv_modify_qp(txq_obj, MLX5_TXQ_MOD_RST2RDY,\n+\t\t\t\t (uint8_t)priv->dev_port);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u QP state modifying failed.\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tqp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t/* If using DevX, need additional mask to read tisn value. */\n+\tif (priv->sh->devx && !priv->sh->tdn)\n+\t\tqp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;\n+#endif\n+\tobj.cq.in = txq_obj->cq;\n+\tobj.cq.out = &cq_info;\n+\tobj.qp.in = txq_obj->qp;\n+\tobj.qp.out = &qp;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);\n+\tif (ret != 0) {\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tif (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Port %u wrong MLX5_CQE_SIZE environment variable\"\n+\t\t\t\" value: it should be set to %u.\",\n+\t\t\tdev->data->port_id, RTE_CACHE_LINE_SIZE);\n+\t\trte_errno = EINVAL;\n+\t\tgoto error;\n+\t}\n+\ttxq_data->cqe_n = log2above(cq_info.cqe_cnt);\n+\ttxq_data->cqe_s = 1 << txq_data->cqe_n;\n+\ttxq_data->cqe_m = txq_data->cqe_s - 1;\n+\ttxq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;\n+\ttxq_data->wqes = qp.sq.buf;\n+\ttxq_data->wqe_n = log2above(qp.sq.wqe_cnt);\n+\ttxq_data->wqe_s = 1 << txq_data->wqe_n;\n+\ttxq_data->wqe_m = txq_data->wqe_s - 1;\n+\ttxq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;\n+\ttxq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];\n+\ttxq_data->cq_db = cq_info.dbrec;\n+\ttxq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;\n+\ttxq_data->cq_ci = 0;\n+\ttxq_data->cq_pi = 0;\n+\ttxq_data->wqe_ci = 0;\n+\ttxq_data->wqe_pi = 0;\n+\ttxq_data->wqe_comp = 0;\n+\ttxq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t/*\n+\t * If using DevX need to query and store TIS transport domain value.\n+\t * This is done once per port.\n+\t * Will use this value on Rx, when creating matching TIR.\n+\t */\n+\tif (priv->sh->devx && !priv->sh->tdn) {\n+\t\tret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,\n+\t\t\t\t\t\t    &priv->sh->tdn);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Fail to query port %u Tx queue %u QP TIS \"\n+\t\t\t\t\"transport domain.\", dev->data->port_id, idx);\n+\t\t\trte_errno = EINVAL;\n+\t\t\tgoto error;\n+\t\t} else {\n+\t\t\tDRV_LOG(DEBUG, \"Port %u Tx queue %u TIS number %d \"\n+\t\t\t\t\"transport domain %d.\", dev->data->port_id,\n+\t\t\t\tidx, qp.tisn, priv->sh->tdn);\n+\t\t}\n+\t}\n+#endif\n+\ttxq_ctrl->bf_reg = qp.bf.reg;\n+\tif (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {\n+\t\ttxq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;\n+\t\tDRV_LOG(DEBUG, \"Port %u: uar_mmap_offset 0x%\" PRIx64 \".\",\n+\t\t\tdev->data->port_id, txq_ctrl->uar_mmap_offset);\n+\t} else {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Port %u failed to retrieve UAR info, invalid\"\n+\t\t\t\" libmlx5.so\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EINVAL;\n+\t\tgoto error;\n+\t}\n+\ttxq_uar_init(txq_ctrl);\n+\tdev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n+\treturn 0;\n+error:\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (txq_obj->cq)\n+\t\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+\tif (txq_obj->qp)\n+\t\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n+\trte_errno = ret; /* Restore rte_errno. */\n+\treturn -rte_errno;\n+}\n+\n+/*\n+ * Create the dummy QP with minimal resources for loopback.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev)\n+{\n+#if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT)\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct ibv_context *ctx = sh->ctx;\n+\tstruct mlx5dv_qp_init_attr qp_init_attr = {0};\n+\tstruct {\n+\t\tstruct ibv_cq_init_attr_ex ibv;\n+\t\tstruct mlx5dv_cq_init_attr mlx5;\n+\t} cq_attr = {{0}};\n+\n+\tif (dev->data->dev_conf.lpbk_mode) {\n+\t\t/* Allow packet sent from NIC loop back w/o source MAC check. */\n+\t\tqp_init_attr.comp_mask |=\n+\t\t\t\tMLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;\n+\t\tqp_init_attr.create_flags |=\n+\t\t\t\tMLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;\n+\t} else {\n+\t\treturn 0;\n+\t}\n+\t/* Only need to check refcnt, 0 after \"sh\" is allocated. */\n+\tif (!!(__atomic_fetch_add(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED))) {\n+\t\tMLX5_ASSERT(sh->self_lb.ibv_cq && sh->self_lb.qp);\n+\t\tpriv->lb_used = 1;\n+\t\treturn 0;\n+\t}\n+\tcq_attr.ibv = (struct ibv_cq_init_attr_ex){\n+\t\t.cqe = 1,\n+\t\t.channel = NULL,\n+\t\t.comp_mask = 0,\n+\t};\n+\tcq_attr.mlx5 = (struct mlx5dv_cq_init_attr){\n+\t\t.comp_mask = 0,\n+\t};\n+\t/* Only CQ is needed, no WQ(RQ) is required in this case. */\n+\tsh->self_lb.ibv_cq = mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(ctx,\n+\t\t\t\t\t\t\t&cq_attr.ibv,\n+\t\t\t\t\t\t\t&cq_attr.mlx5));\n+\tif (!sh->self_lb.ibv_cq) {\n+\t\tDRV_LOG(ERR, \"Port %u cannot allocate CQ for loopback.\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tsh->self_lb.qp = mlx5_glue->dv_create_qp(ctx,\n+\t\t\t\t&(struct ibv_qp_init_attr_ex){\n+\t\t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t\t\t\t.comp_mask = IBV_QP_INIT_ATTR_PD,\n+\t\t\t\t\t.pd = sh->pd,\n+\t\t\t\t\t.send_cq = sh->self_lb.ibv_cq,\n+\t\t\t\t\t.recv_cq = sh->self_lb.ibv_cq,\n+\t\t\t\t\t.cap.max_recv_wr = 1,\n+\t\t\t\t},\n+\t\t\t\t&qp_init_attr);\n+\tif (!sh->self_lb.qp) {\n+\t\tDRV_LOG(DEBUG, \"Port %u cannot allocate QP for loopback.\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tpriv->lb_used = 1;\n+\treturn 0;\n+error:\n+\tif (sh->self_lb.ibv_cq) {\n+\t\tclaim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq));\n+\t\tsh->self_lb.ibv_cq = NULL;\n+\t}\n+\t(void)__atomic_sub_fetch(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED);\n+\treturn -rte_errno;\n+#else\n+\tRTE_SET_USED(dev);\n+\treturn 0;\n+#endif\n+}\n+\n+/*\n+ * Release the dummy queue resources for loopback.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ */\n+void\n+mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev *dev)\n+{\n+#if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT)\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\n+\tif (!priv->lb_used)\n+\t\treturn;\n+\tMLX5_ASSERT(__atomic_load_n(&sh->self_lb.refcnt, __ATOMIC_RELAXED));\n+\tif (!(__atomic_sub_fetch(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED))) {\n+\t\tif (sh->self_lb.qp) {\n+\t\t\tclaim_zero(mlx5_glue->destroy_qp(sh->self_lb.qp));\n+\t\t\tsh->self_lb.qp = NULL;\n+\t\t}\n+\t\tif (sh->self_lb.ibv_cq) {\n+\t\t\tclaim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq));\n+\t\t\tsh->self_lb.ibv_cq = NULL;\n+\t\t}\n+\t}\n+\tpriv->lb_used = 0;\n+#else\n+\tRTE_SET_USED(dev);\n+\treturn;\n+#endif\n+}\n+\n+/**\n+ * Release an Tx verbs queue object.\n+ *\n+ * @param txq_obj\n+ *   Verbs Tx queue object..\n+ */\n+void\n+mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj)\n+{\n+\tMLX5_ASSERT(txq_obj);\n+\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n+\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+}\n+\n+struct mlx5_obj_ops ibv_obj_ops = {\n+\t.rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,\n+\t.rxq_obj_new = mlx5_rxq_ibv_obj_new,\n+\t.rxq_event_get = mlx5_rx_ibv_get_event,\n+\t.rxq_obj_modify = mlx5_ibv_modify_wq,\n+\t.rxq_obj_release = mlx5_rxq_ibv_obj_release,\n+\t.ind_table_new = mlx5_ibv_ind_table_new,\n+\t.ind_table_destroy = mlx5_ibv_ind_table_destroy,\n+\t.hrxq_new = mlx5_ibv_hrxq_new,\n+\t.hrxq_destroy = mlx5_ibv_qp_destroy,\n+\t.drop_action_create = mlx5_ibv_drop_action_create,\n+\t.drop_action_destroy = mlx5_ibv_drop_action_destroy,\n+\t.txq_obj_new = mlx5_txq_ibv_obj_new,\n+\t.txq_obj_modify = mlx5_ibv_modify_qp,\n+\t.txq_obj_release = mlx5_txq_ibv_obj_release,\n+\t.lb_dummy_queue_create = NULL,\n+\t.lb_dummy_queue_release = NULL,\n+};\ndiff --git a/drivers/net/mlx5/freebsd/mlx5_verbs.h b/drivers/net/mlx5/freebsd/mlx5_verbs.h\nnew file mode 100644\nindex 0000000000..f7e8e2fe98\n--- /dev/null\n+++ b/drivers/net/mlx5/freebsd/mlx5_verbs.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef RTE_PMD_MLX5_VERBS_H_\n+#define RTE_PMD_MLX5_VERBS_H_\n+\n+#include \"mlx5.h\"\n+\n+int mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n+void mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj);\n+int mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev);\n+void mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev *dev);\n+\n+/* Verbs ops struct */\n+extern const struct mlx5_mr_ops mlx5_mr_verbs_ops;\n+extern struct mlx5_obj_ops ibv_obj_ops;\n+#endif /* RTE_PMD_MLX5_VERBS_H_ */\n",
    "prefixes": [
        "v2",
        "12/41"
    ]
}